EP4643338A1

EP4643338A1 - Cell-aware chain diagnosis

Info

Publication number: EP4643338A1
Application number: EP23708650.9A
Authority: EP
Inventors: Szczepan Urban; Jakub JANICKI; Manish Sharma
Original assignee: Siemens Industry Software Inc
Current assignee: Siemens Industry Software Inc
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2025-11-05
Also published as: CN120641984A; WO2024163015A1

Abstract

Chain pattern results are analyzed to identify a faulty scan chain in a circuit and a fault associated with the faulty scan chain. Scan pattern results are analyzed to identify one or more faulty scan element candidates on the faulty scan chain. Analog simulation is then performed to identify faulty component candidates in the one or more faulty scan element candidates. During the process, components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates can be determined. Physical failure analysis can be performed on the circuit to locate one or more defective components in the faulty component candidates.

Description

Cell-Aware Chain Diagnosis

Cell-Aware Chain Diagnosis FIELD OF THE DISCLOSED TECHNIQUES [01] The presently disclosed techniques relates to circuit testing and diagnosis. Various implementations of the disclosed techniques may be particularly useful for scan chain diagnosis. BACKGROUND OF THE DISCLOSED TECHNIQUES [02] Building circuits on silicon as test chips can provide insight into how a new fabrication process works. Traditionally, semiconductor manufacturers relied mainly on bitmapping SRAMs (static random-access memory) test chips for ramping up, qualifying and monitoring new semiconductor fabrication processes. For the advanced technology nodes, however, being able to manufacture these regular structures does not guarantee that logic circuits can be successfully fabricated. Logic circuits often have irregular structures and represent a large fraction of the transistor and circuit geometries found in a real product. [03] To check whether a logic test chip is fabricated according to the design and to locate potential defects, scan testing and diagnosis are usually employed. In this technique, a series of known values (test stimuli or test pattern) are shifted into (or loaded into) state elements called scan cells through their sequential inputs. These scan cells are interconnected to form scan chains for scan testing. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” by and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of a new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be called as test mode. [04] Automatic diagnosis of scan test failures has proven to be a useful tool for identifying systematic defects in a real product and speeding up the turn-around time of yield learning cycles. When a circuit fails a scan test, scan test diagnosis (sometimes also referred to as fault diagnosis or defect diagnosis) uses the failure data outputted from the tester along with the design information to determine a set of most likely defect locations and defect mechanisms for the failing circuit. These diagnosis results can guide physical failure analysis (PFA) to search for the defect in a small area of the failing circuit. This can improve the success rate of locating the defect and discovering the physical feature that triggers the defect. The physical feature information can ultimately lead to yield loss mechanism identification and then to yield improvement either through design or manufacture process changes. [05] Scan chains and their associated clock circuitry are themselves a major source of circuit failures. It has been reported that defects occurring on scan chains account for about 30% to 50% of all failing chips. Thus, scan chains need to be tested and diagnosed first. As discussed in detail below, faulty scan chains can be detected using relatively simple methods. Locating defective scan cells, however, are challenging. Physical failure analysis instruments, combined with a tester, are sometimes used to search for defective responses along scan chains. These hardware-based methods often rely on specially- designed scan chains and scan cells. While effective in isolating scan chain defects, the requirement of extra hardware may not be acceptable in many realistic products. Further, it is difficult to apply these methods to chips with embedded compression circuits without resorting to a bypass mode. [06] Software-based techniques use algorithmic diagnosis procedures to identify failing scan cells. It may run chain diagnosis with conventional scan chains with or without embedded test compressions. The current software-based chain diagnosis techniques may be further classified into three categories: model-based algorithms, profiling-based algorithms and machine-learning-based algorithms. While conventional methods may be able to determine a defective scan cell candidate on a faulty scan chain, a single scan cell still contains tens or hundreds of transistors. It would take significant time for PFA to locate the defective device from tens or hundreds of defective transistor candidates. A diagnosis tool that can single out some transistors or nets inside a defective scan cell candidate would improve PFA success rates and reduce turnaround time and costs. BRIEF SUMMARY OF THE DISCLOSED TECHNIQUES [07] Various aspects of the disclosed technology relate to chain diagnosis. In one aspect, there is a method, comprising: receiving chain pattern results and scan pattern results for a circuit, the chain pattern results obtained by shifting chain patterns through scan chains in the circuit, the scan pattern results obtained by shifting scan patterns into the scan chains, applying the scan patterns to the circuit, capturing test responses by the scan chains, and shifting the test responses out of the circuit; analyzing the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain; analyzing the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain, a faulty scan element candidate being a single-bit scan cell or a bit in a multi-bit scan cell; performing analog simulation to identify faulty component candidates in the one or more faulty scan element candidates, the identifying comprising determining components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates; and storing information of the faulty component candidates in a computer readable storage device. The method may further comprise: performing physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates. [08] The analog simulation may be transistor-level circuit simulation or switch-level circuit simulation. The analyzing the scan pattern results may employ a model-based technique, a profiling-based technique, a machine-learning-based technique, or any combination thereof. [09] The analyzing scan pattern results may determine that the fault is on a scan-only path of one of the one or more faulty scan element candidates, and the performing analog simulation to identify faulty component candidates may comprise: varying a signal at a serial input of the one of the one or more faulty scan element candidates to determine a scan path in the one of the one or more faulty scan element candidates; varying a signal at a parallel input of the one of the one or more faulty scan element candidates to determine a functional signal path of the one of the one or more faulty scan element candidates; and determining the faulty device candidates on part of the scan path that does not overlap with the functional signal path. [10] In another aspect, there is one or more computer-readable media storing computer- executable instructions for causing one or more processors to perform the above method. [11] In still another aspect, there is a system, comprising: one or more processors, the one or more processors programmed to perform the above method. [12] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims. [13] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed techniques. Thus, for example, those skilled in the art will recognize that the disclosed techniques may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS [14] Figure 1 illustrates a programmable computer system with which various embodiments of the disclosed technology may be employed. [15] Figure 2 illustrates an example of a cell-aware chain diagnosis tool that may be implemented according to various embodiments of the disclosed technology. [16] Figure 3 illustrates a flowchart showing a process of cell-aware chain diagnosis that may be implemented according to various examples of the disclosed technology. [17] Figure 4A illustrates an example of a scan chain. [18] Figure 4B illustrates another example of a scan chain. [19] Figure 5 illustrates an example process for obtaining chain pattern results. [20] Figure 6 illustrates an example of three scan chains, of which one has a fault. [21] Figure 7 illustrates an example of using scan patterns to identify faulty scan cells or faulty scan cell suspects for the faulty scan chain shown in Fig.6. [22] Figure 8 illustrates unloaded patterns for eight permanent fault models and eight intermittent fault models obtained by shifting in and out a chain pattern (“001100110011”). [23] Figure 9A illustrate an example of the front part of a scan cell circuit in which a scan path derived based on analog simulation is shown. [24] Figure 9B illustrate an example of the front part of a scan cell circuit in which a functional signal path derived based on analog simulation is shown. DETAILED DESCRIPTION OF THE DISCLOSED TECHNIQUES General Consideration [25] Various aspects of the disclosed technology relate to chain diagnosis. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the disclosed technology. [26] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers. [27] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods. [28] The detailed description of a method or a device sometimes uses terms like “analyze”, “perform”, “determine”, and “identify” to describe the disclosed method or the device function/structure. Such terms are high-level descriptions. The actual operations or functions/structures that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art. [29] Additionally, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device such as a portion of an integrated circuit device nevertheless. Illustrative Operating Environment [30] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105. [31] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 115, a removable magnetic disk drive 117, an optical disk drive 119, or a flash memory card 121. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection. [32] With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail. [33] It should be appreciated that the computer 101 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 101 illustrated in Fig. 1, which include only a subset of the components illustrated in Fig. 1, or which include an alternate combination of components, including components that are not shown in Fig. 1. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and/or multiprocessor computers arranged into a network, or some combination of both. Scan-Based Circuit Test And Diagnosis [34] The reduction in feature size increases the probability that a manufacture defect in the integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high- volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield. [35] Testing typically includes applying a set of test stimuli (test patterns) to the circuit- under-test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under- test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions. [36] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains – serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional/mission mode) and as a unit in a scan chain for scan (scan mode). A widely used type of scan cell include an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan_enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs/outputs and/or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element. [37] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gate-level fault model. A defect is an error caused in a device during the manufacturing process. A fault model is a description of how a defect alters design behavior. In another word, a defect is a flaw or physical imperfection that may lead to a fault. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault. Fault propagation propagates the fault effect forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults. [38] The most popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as, the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects. [39] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PFA) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file, or failure report). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. [40] Diagnosis includes logic diagnosis and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back-tracing), fault injection, and evaluation (fault simulation for both failing and passing test patterns). The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). To enhance the diagnosis quality, a diagnostic test pattern generation process may be employed. This process generates test patterns that can refine the set of defect suspects. [41] Chain diagnosis determines scan cells that are likely to be defective. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and/or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells. [42] The layout information and cell internal information of the circuit design may be employed to improve diagnosis resolution and to shrink defect suspect areas. This can help to identify physical features associated with defect suspects such as layout layer, via macro type, cell type, critical area, and specific layout pattern. A large volume of diagnosis reports containing physical features associated with each defect suspect can be statistically analyzed by a software tool to automatically identify systematic defects. This approach is sometimes referred to as diagnosis driven yield analysis (DDYA). [43] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in/out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit. [44] Various test compression techniques have been developed. In general, additional on- chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can reduce not only the amount of data stored on the tester but also the test time for a given test data bandwidth. Cell-Aware Chain Diagnosis Tool [45] Fig. 2 illustrates an example of a cell-aware chain diagnosis tool 200 that may be implemented according to various embodiments of the disclosed technology. As seen in this figure, the cell-aware chain diagnosis tool 200 includes a chain pattern result analysis unit 210, a scan pattern result analysis unit 220, and an analog simulation unit 230. Some implementations of the cell-aware chain diagnosis tool 200 may cooperate with (or incorporate) one or more of a physical failure analysis (PFA) tool 250, an input database 205 and an output database 255. [46] As will be discussed in more detail below, the cell-aware chain diagnosis tool 200 can receive chain pattern results and scan pattern results for a circuit from the input database 205. The chain pattern result analysis unit 210 can analyze the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain. The scan pattern result analysis unit 220 can analyze the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain. A faulty scan element candidate is a single-bit scan cell or a bit in a multi-bit scan cell. The analog simulation unit 230 can perform analog simulation to identify faulty component candidates in the one or more faulty scan element candidates. The identification comprises determining components of each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates. The components can comprise nets, transistors, or both. The cell-aware chain diagnosis tool 200 can store information of the faulty component candidates in the output database 255. Optionally, the physical failure analysis (PFA) tool 250 can perform physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates. [47] As previously noted, various examples of the disclosed technology may be implemented by one or more computing systems, such as the computing system illustrated in Fig. 1. Accordingly, one or more of the chain pattern result analysis unit 210, the scan pattern result analysis unit 220, and the analog simulation unit 230 may be implemented by executing programming instructions on one or more processors in one or more computing systems, such as the computing system illustrated in Fig. 1. Correspondingly, some other embodiments of the disclosed technology may be implemented by software instructions, stored on a non-transitory computer-readable medium, for instructing one or more programmable computers/computer systems to perform the functions of one or more of the chain pattern result analysis unit 210, the scan pattern result analysis unit 220, and the analog simulation unit 230. As used herein, the term “non-transitory computer-readable medium” refers to computer- readable medium that are capable of storing data for future retrieval, and not propagating electro-magnetic waves. The non-transitory computer-readable medium may be, for example, a magnetic storage device, an optical storage device, or a solid state storage device. [48] It also should be appreciated that, while the chain pattern result analysis unit 210, the scan pattern result analysis unit 220, and the analog simulation unit 230 are shown as separate units in Fig. 2, a single computer (or a single processor within a master computer) or a single computer system may be used to implement some or all of these units at different times, or components of these units at different times. [49] With various examples of the disclosed technology, the input database 205 and the output database 255 may be implemented using any suitable computer readable storage device. That is, either of the input database 205 and the output database 255 may be implemented using any combination of computer readable storage devices including, for example, microcircuit memory devices such as read-write memory (RAM), read- only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable storage devices may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. While the input database 205 and the output database 255 are shown as separate units in Fig. 2, a single data storage medium may be used to implement some or all of these databases. Process Of Cell-Aware Chain Diagnosis [50] Fig. 3 illustrates a flowchart 300 showing a process of cell-aware chain diagnosis that may be implemented according to various examples of the disclosed technology. For ease of understanding, methods of cell-aware chain diagnosis that may be employed according to various embodiments of the disclosed technology will be described with reference to the cell-aware chain diagnosis tool 200 in Fig. 2 and the flow chart 300 illustrated in Fig. 3. It should be appreciated, however, that alternate implementations of a cell-aware chain diagnosis tool may be used to perform the methods of cell-aware chain diagnosis illustrated by the flow chart 300 according to various embodiments of the disclosed technology. Likewise, the cell-aware chain diagnosis tool 200 may be employed to perform other methods of cell-aware chain diagnosis according to various embodiments of the disclosed technology. [51] In operation 310 of the flow chart 300, the cell-aware chain diagnosis tool 200 receives receive chain pattern results and scan pattern results for a circuit from the input database 205. The chain pattern results can be obtained by shifting chain patterns through scan chains in the circuit; and the scan pattern results can be obtained by shifting scan patterns into the scan chains, applying the scan patterns to the circuit, capturing test responses by the scan chains, and shifting the test responses out of the circuit. [52] Fig. 4A illustrates an example of a scan chain 400. The scan chain 400 comprises a plurality of scan cells 410. Each of the scan cells 410 comprises an edge-trigged flip- flop 420 with a two-way multiplexer 430 for the data input. The two-way multiplexer 430 is typically controlled by a control signal 440 (named “scan_enable” in the figure), which selects the input signal for the scan cell 410 from either a scan signal input port 450 (sometimes referred to as serial input) or a system signal input port 460 (sometimes referred to as parallel input). The scan signal input port 450 is typically connected to an output of another scan cell in the scan chain 400 while the system signal input port 460 is connected to functional circuitry 470. Each of the scan cells 410 fans out into two outputs: a serial output coupled to the scan cell in the scan chain 400 and a parallel output coupled to functional circuitry 470. [53] In test mode, a scan cell like the scan cell 410 can serve as a control point that applies a test stimulus bit to the circuit-under-test, an observation point that captures a test response bit generated by the circuit-under-test, or both. Test mode typically includes two types of operations: shift operation (shift mode) and capture operation (capture mode). In the shift operation, a series of clock pulses, called “shift pulses” or “shift clock pulses,” are applied to the scan cells. Each shift clock pulse pushes a bit of a test pattern into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. In the capture operation, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to both the scan cells and the circuit-under-test as they would be in normal operation. After the test pattern bits stored in the scan cells are injected into the circuit-under-test, the results of the test (test responses) are “captured” and stored in the scan cells. The scan cells then return to the shift operation, and with each additional clock pulse, a bit of the test responses is pushed or shifted out along the scan chains as each bit of a new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. [54] Fig. 4B illustrates another example of a scan chain 405. Unlike the scan chain 400 in Fig. 4A, parallel outputs of the scan chain 405 are coupled to functional circuitry 480 indirectly via update storage elements 490. The signals applied to the functional circuitry 480 can only change when an update clock signal 495 is toggled instead of whenever shifting occurs in the scan chain 405. This can prevent shifting from changing the state of the functional circuitry 480. Another benefit is the reduction of toggling activities in the shift operation which can significantly lower power consumptions and prevent the circuit from overheating. The update storage elements 490 can be implemented using latches or flip-flops. It should be noted that the disclosed technology can also be applied to diagnosing scan chains formed by state elements other than edge-trigged flip-flops. [55] Fig. 5 illustrates an example process for obtaining chain pattern results. In the figure, a faulty scan chain 500 has a stuck-at-zero fault 510 located at one of its scan cells. A chain pattern 520, “101010,” is shifted into the scan chain 500. Due to the stuck-at-zero fault 510, bits at and after the faulty scan cell become all zeros and the shifted-in (or loaded) pattern becomes “101000.” When the shifted-in pattern is being shifted out, the stuck-at-zero fault 510 causes the bits before the faulty scan cell becomes all zeros, forming the unloaded pattern 530, “000000.” If a scan chain has no defect, the unloaded pattern should be the same as the original chain pattern. Thus, a comparison of the unloaded pattern with the original pattern indicates whether the scan chain is faulty or not. Different fault types can lead to different unloaded patterns. An analysis of unloaded patterns can determine which fault type the faulty scan chain is associated with. The chain pattern results can comprise unloaded patterns. [56] Figs. 6 and 7 illustrate an example process for obtaining scan pattern results. Fig. 6 shows three scan chains 610, 620 and 630, among which the scan chain 620 is defective. The scan cells on each of the scan chains are numbered from “0” to “5” following the scan shift direction. On the scan chain 620, scan cell #3 has a stuck-at- zero fault 640. Fig. 7 illustrates a test pattern 700 and its various derivative patterns formed/predicted from scan shift, capture, simulation and comparison operations, respectively. After the test pattern 700 is shifted into the scan chains, a loaded test pattern 710 is formed. Due to the stuck-at-zero fault 640, the bits loaded in scan cells #3 and #4 change their values from “1” to “0.” After one or more capture clock cycles, the scan cells on the three scan chains capture the test response to the loaded test pattern 710. The captured test response bits form a captured test response pattern 720. A good-machine simulation can determine an expected good-machine test response pattern 740 assuming the scan chains 610-630 have no defect. [57] A comparison of the captured test response pattern 720 with the good-machine test response pattern 740 shows that scan cell #4 on the scan chain 610 and scan cell #1 on the scan chain 620 both capture values different from the good-machine values. These failing bits are caused by the wrong loaded values loaded in scan cells #3 and #4 on the scan chain 620, respectively. As Fig. 4 shows, the scan cell #3 on the scan chain 620 is connected to the scan cell #1 on the scan chain 620 through logic circuitry 650; and the scan cell #4 on the scan chain 620 is connected to the scan cell #4 on the scan chain 610 through logic circuitry 670. These two logic paths are responsible for the failing bits, respectively. [58] Most of the bits of the captured test response pattern 720 have the same values as the corresponding ones of the good-machine test response pattern 740. This may be because these scan cells have no paths connecting them to the scan cells loaded with wrong values. An alternative reason may be that the paths connecting the scan cells to the scan cells loaded with wrong values are not activated. An example of the latter case is shown in Fig. 6. While the wrong value loaded in scan cell #3 on the scan chain 620 can potentially affect the captured value in scan cell #1 on the scan chain 610 through a logic circuit 660, the path is blocked by the wrong value loaded in the scan cell #4 on the scan chain 620. As a result, scan cell #1 on the scan chain 610 captures a value conforming to a good-machine value. [59] The captured test response pattern 720 is not the observed pattern. After shifting out, the captured test response pattern 720 changes to an unloaded test response pattern 730. Three bits of the unloaded test response pattern 730 have values different from the corresponding bits of the good-machine test response pattern 740. These failing bits are represented by “1s” in an observed failing bit pattern 750. It should be noted that an observed failing bit pattern can alternatively use “0s” for failing bits and “1s” for “good” bits. [60] The observed failing bit pattern 750 can be treated as being obtained by combining the unloaded test response pattern 730 and the good-machine test response pattern 740 through an XOR gate 760. The failing bits of the observed failing bit pattern 750 are different from those of the captured test response pattern 720. Specifically, the failing bits on the faulty scan chain are different between the observed failing bit pattern 750 and the captured test response pattern 720. Because of the stuck-at-zero fault 640, two “good” bits (captured by scan cells #2 and #3) becomes failing bits while a failing bit (captured by scan cell #1) becomes a “good” bit. [61] The scan pattern results can comprise observed failing bit patterns or unloaded test response patterns. [62] Referring back to Fig. 3, in operation 320, the chain pattern result analysis unit 210 analyzes the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain. If one or more bits of a chain pattern unloaded from a scan chain are different from the original bits, the scan chain can be deemed as a faulty scan chain. Different faults can cause different bits unloaded from a faulty scan chain. Fig. 8 lists unloaded patterns for eight permanent fault models and eight intermittent fault models obtained by shifting in and out a chain pattern (“001100110011”). As the figure shows, this chain pattern has different unloaded values for sixteen different fault models. By comparing the unloaded chain pattern in the chain pattern results with the expected unloaded patterns for these different faults, the chain pattern result analysis unit 210 can determine the fault associated with the faulty scan chain. It should be noted that the chain pattern results may be obtained by using different chain patterns. Using conventional one-dimensional scan architecture, however, chain patterns alone usually cannot locate the faulty scan cell. [63] In operation 330, the scan pattern result analysis unit 220 can analyze the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain. A faulty scan element candidate is a single-bit scan cell or a bit in a multi-bit scan cell. If the scan pattern results comprise unloaded test response patterns, the scan pattern result analysis unit 220 can convert them into observed failing bit patterns. The scan pattern result analysis unit 220 can employ various software-based chain diagnosis techniques such as model-based, profiling-based, or machine-learning-based techniques for the analysis. A model-based chain diagnosis process relies on fault models and pattern simulation. A profiling-based chain diagnosis process employs signal profiling, filtering and edge detections. A machine-learning-based chain diagnosis process uses trained machine learning models for diagnosis. Examples for the three types of software-based chain diagnosis techniques are described below. [64] In a model-based chain diagnosis process, the fault identified in the previous operation is algorithmically “injected” to one scan cell on the faulty scan chain. The loaded values of the downstream cells are accordingly modified for all scan patterns. For example, suppose a scan pattern has good machine loaded value 001110011010 on the faulty scan chain. If a permanent stuck-at-1 fault is injected on scan cell 8 of this chain, the loaded values will be modified as 001111111111. After pulsing the capture clock, the simulated captured values in the upstream of the failing scan cell on this chain will also be modified. For example if the simulated captured value is 101011101011, the unloaded values will be 111111101011. The fault simulation is performed one cell at a time. The simulation results are compared with the scan pattern results. The cell(s) that matches the best are reported as suspect(s). [65] A profiling-based chain diagnosis technique can be a data-driven one or a hybrid one. A data-driven chain diagnosis technique can use special chain diagnosis patterns. These patterns can be either functional test patterns that start from an initial state, or scan patterns that start with all “0”s or all “1”s. The purpose of using such patterns is to avoid (or minimize) any faulty values introduced with the loading of scan chains. Therefore, all (or most) of the failing bits are caused in the process of unloading scan chains. Then the diagnosis can be performed by monitoring from which scan cell the signal probability has been significantly changed. These algorithms select scan patterns to randomize signal probability of scan cells before unloading. The failing scan cell position can be identified by comparing the observed signal profile on a tester and the expected signal profile. [66] A hybrid chain diagnosis technique combines a model-based technique with a data- driven technique. The combination allows manufacturing ATPG scan patterns to be utilized for chain diagnosis. Manufacturing ATPG scan patterns are preferred in a practical chain diagnosis application because these scan patterns are already available for testing circuits during manufacturing processes. If the diagnosis result from applying manufacturing ATPG scan patterns is not satisfactory, additional diagnostic patterns may be created. [67] A hybrid chain diagnosis technique often uses masking techniques to avoid or minimize any faulty values introduced during loading scan patterns to scan chains. One of the masking techniques is the X-masking technique. This technique identifies sensitive loading bits for each scan pattern and replaces each of them with an “X”. A sensitive loading bit of a test pattern corresponds to a scan cell of which a loaded value can be different from the good-machine loaded value due to a defect or defects existing in the scan chain. For different fault models, the sensitive loading bits may be different. For example, suppose a scan pattern has a good machine loaded value 001110011010 on the faulty chain. If a stuck-at-1 fault is identified, all “0”s are sensitive loading bits. The X-masking technique will replace “0”s with “X”s and thus the loaded value will become XX111XX11X1X. If a fast-to-rise fault is identified instead, all “0”s within the “10” transitions will become sensitive loading bits, and the loaded value will be changed to “00111X011X1X”. Once scan patterns are X-masked, simulations may be performed to derive expected unloading values. Based on the expected unloading values and the observed unloading values (test response data collected after applying the scan patterns), failing probabilities for scan cells in a faulty scan chain are calculated and failing scan cells may be identified. [68] Machine learning models can also be employed for chain diagnosis. If unloaded test response patterns are treated as failure images, then faulty scan cell identification is like image recognition. A large circuit nowadays has tens of millions of scan cells, which may be divided into hundreds of thousands of scan chains. Several thousands of test patterns are typically generated for testing circuits. Multiplying these numbers together (number of scan cells x number of test patterns), the total number of components of the input vector for a machine learning model can reach ten billion. To achieve “image compression/reduction, bit reduction can be performed on observed failing bit patterns. The bit reduction can comprise pattern-based bit compression or cycle-based bit compression for each of the scan chains. Both comprise bit combination that can be based on bit value addition or bit failing probability calculation. The bit reduction can further comprise bit filtering which can remove either bits of the compressed observed failing bit patterns that are associated with scan cells that have no logic path to any scan cells on a faulty scan chain from the training samples construction, or bits that never fail for any of the test patterns or for any of the fault injections into a faulty scan chain from the training samples construction, or both. Alternatively, bit filtering can keep only sensitive bits on faulty scan chains for the training samples construction, the faulty scan chains being scan chains with the faults being injected into, or any combination thereof. [69] Two-level machine learning models may be employed. Using a group of training samples, the first-level machine-learning models are trained. Affine scan cell groups are identified. The second group of training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, the second-level machine-learning models are trained. The first-level and second-level machine learning models can then be applied in a multi-stage machine learning-based chain diagnosis process. [70] In addition to identifying one or more faulty scan element candidates, the scan pattern result analysis unit 220 may be able to determine whether the fault is on a scan-only path of a faulty scan element candidate. The process can be illustrated using the example shown in Figs. 6 and 7. Assume that the value of “1” captured by the scan cell #3 on the scan chain 620 is unloaded without being changed, unlike the unloaded test response pattern 730 which shows an incorrect value of “0” for the corresponding bit. If the scan cell #3 on the scan chain 620 has been determined to be a faulty scan element candidate having a stuck-at-zero fault, the unchanged value of “1” for the corresponding bit of the unloaded test response pattern shows that the fault should not be on the functional path which shares part of the scan path. Therefore, the fault is probably on the scan-only path. For the scan cells 420 shown in Fig. 4A, the scan-only path is between the serial input and some device inside the multiplexers 430. [71] Referring back to Fig. 3, in operation 340, the analog simulation unit 230 performs analog simulation to identify faulty component candidates in the one or more faulty scan element candidates. The identification comprises determining components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates. A component can be a net, a transistor, or other circuit devices. A net is a conductor interconnecting two or more terminals of circuit devices (or a continuous piece of metal connecting a number of devices together). The analog simulation can be transistor-level circuit simulation or switch-level circuit simulation. [72] With various implementations of the disclosed technology, the analog simulation unit 230 can prepare patterns for each of the inputs of a scan cell for the analog simulation. The patterns can represent a signal change at an input of interest while keeping signals at the other inputs constant. The analog simulation unit 230 can compare the analog simulation results to identify components sensitive to the signal change at the input of interest. A component sensitive to the signal change is a component of which status changes with the signal change. For example, if a transistor changes from acting as an open switch to acting as a closed switch due to the signal change at the input of interest for the scan cell due to the signal change, the transistor is sensitive to it. Another example of a component sensitive to the signal change is the voltage of the component changes with the signal change. [73] If the scan pattern result analysis unit 220 in the previous operation determines that the fault is probably on the scan-only path of a faulty scan element candidate, the analog simulation unit 230 can perform analog simulation to determine both components sensitive to a signal change at the serial input of the faulty scan element candidate and components sensitive to a signal change at the parallel input of the faulty scan element candidate. The former should be on the scan path, and the latter should be on the functional signal path. Typically, part of the scan path merges with part of the functional signal path after a multiplexer in the scan cell. Thus the analog simulation unit 230 can compare the two paths to determine the scan-only path which is the part that does not overlap with the functional signal path. The components on the scan-only path can then be reported as the faulty component candidates. [74] Figs. 9A-B illustrate an example of the front part of a scan cell circuit 900. The scan cell circuit 900 is shown to have a serial input 910, a parallel input 920, a scan enable signal input 930, and a clock signal input 940. In Fig. 9A, a scan path 950 is indicated, which can be determined by identifying components that are sensitive to the signal at the serial input 910 based on analog simulation. In Fig. 9B, the functional signal path 960 is indicated, which can be determined by identifying components that are sensitive to the signal at the parallel input 920 also based on analog simulation. The scan path 950 and the functional signal path 960 are separated until they are merged at a net 970. The components before the net 970 essentially form a two-way multiplexer 980 which is controlled by the signal at the scan enable signal input 930. This control signal determines whether the signal at the serial input 910 or the signal at a parallel input 920 is allowed to enter the storage module in the scan cell circuit 900. If the fault is on the scan-only path, the faulty component candidates include just a handful of transistors, compared to 50 transistors which are contained in this particular type of scan cell (most of them are not shown in Figs. 9A-B. As mentioned previously, many other scan cells may have even more transistors, up to a couple of hundreds. Therefore, the disclosed technology can significantly speed up the PFA process. [75] If it is determined that multiple faulty scan element candidates exhibit similar faulty behaviors and that one of their control signal inputs (e.g., scan enable input) or clock signal inputs are coupled to the same net, the scan pattern result analysis unit 220 can perform analog simulation to determine components sensitive to a signal change at that control signal input or the clock signal input for each of the faulty scan element candidates. These components can then be reported as the faulty component candidates. This is particular useful for multi-bit scan cells. [76] Referring back to Fig. 3, in operation 350, the cell-aware chain diagnosis tool 200 stores information of the faulty component candidates in the output database 255. Optionally, in operation 360, the physical failure analysis (PFA) tool 250 performs physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates. The results may be used to help identify the root causes for the defects. The identified root causes can be used for adjusting the manufacturing process and/or manufacturing equipment to improve/maintain the yield. Alternatively or additionally, the circuit design may be modified based on the confirmed root causes to improve the yield. Conclusion [77] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is: 1. A method, executed by at least one processor of a computer, comprising: receiving chain pattern results and scan pattern results for a circuit, the chain pattern results obtained by shifting chain patterns through scan chains in the circuit, the scan pattern results obtained by shifting scan patterns into the scan chains, applying the scan patterns to the circuit, capturing test responses by the scan chains, and shifting the test responses out of the circuit; analyzing the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain; analyzing the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain, a faulty scan element candidate being a single-bit scan cell or a bit in a multi-bit scan cell; performing analog simulation to identify faulty component candidates in the one or more faulty scan element candidates, the identifying comprising determining components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates; and storing information of the faulty component candidates in a computer readable storage device.

2. The method recited in claim 1, further comprising: performing physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates.

3. The method recited in claim 1, wherein the analyzing scan pattern results determines that the fault is on a scan-only path of one of the one or more faulty scan element candidates, and wherein the performing analog simulation to identify faulty component candidates comprises: varying a signal at a serial input of the one of the one or more faulty scan element candidates to determine a scan path in the one of the one or more faulty scan element candidates; varying a signal at a parallel input of the one of the one or more faulty scan element candidates to determine a functional signal path of the one of the one or more faulty scan element candidates; and determining the faulty device candidates on part of the scan path that does not overlap with the functional signal path.

4. The method recited in claim 1, wherein the analog simulation is transistor-level circuit simulation or switch-level circuit simulation.

5. The method recited in claim 1, wherein the analyzing the scan pattern results employs a model-based technique, a profiling-based technique, a machine-learning-based technique, or any combination thereof.

6. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: receiving chain pattern results and scan pattern results for a circuit, the chain pattern results obtained by shifting chain patterns through scan chains in the circuit, the scan pattern results obtained by shifting scan patterns into the scan chains, applying the scan patterns to the circuit, capturing test responses by the scan chains, and shifting the test responses out of the circuit; analyzing the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain; analyzing the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain, a faulty scan element candidate being a single-bit scan cell or a bit in a multi-bit scan cell; performing analog simulation to identify faulty component candidates in the one or more faulty scan element candidates, the identifying comprising determining components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates; and storing information of the faulty component candidates in a computer readable storage device.

7. The one or more non-transitory computer-readable media recited in claim 6, wherein the method further comprises: performing physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates.

8. The one or more non-transitory computer-readable media recited in claim 6, wherein the analyzing scan pattern results determines that the fault is on a scan-only path of one of the one or more faulty scan element candidates, and wherein the performing analog simulation to identify faulty component candidates comprises: varying a signal at a serial input of the one of the one or more faulty scan element candidates to determine a scan path in the one of the one or more faulty scan element candidates; varying a signal at a parallel input of the one of the one or more faulty scan element candidates to determine a functional signal path of the one of the one or more faulty scan element candidates; and determining the faulty device candidates on part of the scan path that does not overlap with the functional signal path.

9. The one or more non-transitory computer-readable media recited in claim 6, wherein the analog simulation is transistor-level circuit simulation or switch-level circuit simulation.

10. The one or more non-transitory computer-readable media recited in claim 6, wherein the analyzing the scan pattern results employs a model-based technique, a profiling-based technique, a machine-learning-based technique, or any combination thereof.

11. A system, comprising: one or more processors, the one or more processors programmed to perform a method, the method comprising: receiving chain pattern results and scan pattern results for a circuit, the chain pattern results obtained by shifting chain patterns through scan chains in the circuit, the scan pattern results obtained by shifting scan patterns into the scan chains, applying the scan patterns to the circuit, capturing test responses by the scan chains, and shifting the test responses out of the circuit; analyzing the chain pattern results to identify a faulty scan chain in the circuit and a fault associated with the faulty scan chain; analyzing the scan pattern results to identify one or more faulty scan element candidates on the faulty scan chain, a faulty scan element candidate being a single-bit scan cell or a bit in a multi-bit scan cell; performing analog simulation to identify faulty component candidates in the one or more faulty scan element candidates, the identifying comprising determining components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates; and storing information of the faulty component candidates in a computer readable storage device.

12. The system recited in claim 11, wherein the method further comprises: performing physical failure analysis on the circuit to locate one or more defective components in the faulty component candidates.

13. The system recited in claim 11, wherein the analyzing scan pattern results determines that the fault is on a scan-only path of one of the one or more faulty scan element candidates, and wherein the performing analog simulation to identify faulty component candidates comprises: varying a signal at a serial input of the one of the one or more faulty scan element candidates to determine a scan path in the one of the one or more faulty scan element candidates; varying a signal at a parallel input of the one of the one or more faulty scan element candidates to determine a functional signal path of the one of the one or more faulty scan element candidates; and determining the faulty device candidates on part of the scan path that does not overlap with the functional signal path.

14. The system recited in claim 11, wherein the analog simulation is transistor-level circuit simulation or switch-level circuit simulation.

15. The system recited in claim 11, wherein the analyzing the scan pattern results employs a model-based technique, a profiling-based technique, a machine-learning-based technique, or any combination thereof.