EP4643281A1

EP4643281A1 - Y-basis measurement and initialization in the surface code

Info

Publication number: EP4643281A1
Application number: EP24712643.6A
Authority: EP
Inventors: Craig GIDNEY; Nathan Cody JONES
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2023-02-10
Filing date: 2024-02-08
Publication date: 2025-11-05
Also published as: WO2024168143A1

Abstract

Methods, systems, and apparatus for measuring a Y observable of a logical qubit that includes multiple physical qubits. In one aspect, a method includes performing a four coupler surface code cycle on a first subset of physical qubits to measure stabilizers of the first subset of physical qubits; performing a three coupler surface code cycle on a second subset of physical qubits to measure stabilizers of the second subset of physical qubits, where the first subset and the second subset intersect along a diagonal line of the logical qubit and performing the three coupler surface code cycle comprises applying a layer of Hadamard gates to the second subset of physical qubits; and applying quantum gates to physical qubits on the diagonal line such that error tracking of the surface code cycles is preserved; and multiplying measured X basis stabilizers to compute the Y observable of the logical qubit.

Description

Y-BASIS MEASUREMENT AND INITIALIZATION IN THE SURFACE CODE

BACKGROUND

This specification relates to quantum computing.

Quantum computing provides a means to solve certain problems that cannot be solved in a reasonable period of time using conventional classical computers. These problems include factoring very large numbers into their primes and searching large, unstructured data sets. A number of physical systems are being explored for their use in quantum computing, including ions, spins in semiconductors, and superconducting circuits. However, none of these systems perform sufficiently well to serve directly as computational qubits. For example, single two-state physical systems, which can be used as physical qubits, cannot reliably encode and retain information for long enough to be useful.

Therefore, scalable quantum computers require quantum error correction. Classical error correction employs redundancy. For example, in the repetition code information is copied and stored multiple times. If the copies are later found to disagree, it can be determined that an error has occurred and a majority vote can be taken to recover the information. Copying quantum information is not possible due to the no-cloning theorem. Therefore, quantum error correction codes spread the logical information of one qubit onto an entangled state of multiple physical qubits. The multiple physical qubits are collectively referred to as a logical qubit.

Surface codes are a family of quantum error correcting codes that are defined on a two-dimensional grid of qubits. In the surface code, physical qubits are entangled using a sequence of physical qubit CNOT operations, with subsequent measurements of the entangled states providing a means for error correction and error detection. A set of physical qubits entangled in this way is used to define a logical qubit, which due to the entanglement and measurement has far better performance than the underlying physical qubits. One of the significant advantages of surface codes is their relative tolerance to local errors. Surface codes can handle error rates of almost 3% per surface code clock cycle, which is far less stringent than that of other quantum computing approaches. This error tolerance, along with the simple two-dimensional qubit layout, makes a surface code architecture a realistic approach to building a solid-state quantum computer.

SUMMARY This specification descnbes technologies for Y-basis measurement and initialization in the surface code.

One innovative aspect of the subject matter described in this specification can be implemented in a method for measuring a Y observable of a logical qubit comprising a plurality of physical qubits, the method including: measuring surface code stabilizers of the physical qubits included in the logical qubit, comprising: performing a four coupler surface code cycle on a first subset of physical qubits included in the logical qubit to measure surface code stabilizers of the first subset of physical qubits; performing a three coupler surface code cycle on a second subset of physical qubits included in the logical qubit to measure surface code stabilizers of the second subset of physical qubits, wherein: the first subset of physical qubits and the second subset of physical qubits intersect along a diagonal line of physical qubits included in the logical qubit, the first subset of physical qubits is different from the second subset of physical qubits, and performing the three coupler surface code cycle comprises applying a layer of Hadamard gates to the second subset of physical qubits prior to measuring the surface code stabilizers of the second subset of physical qubits; and applying a plurality of quantum gates to physical qubits on the diagonal line such that error tracking of the four coupler surface code cycle and the three coupler surface code cycle is preserved; and multiplying measured X basis surface code stabilizers to compute the Y observable of the logical qubit.

Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more classical and quantum computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the four coupler surface code cycle and the three coupler surface code cycle are performed simultaneously.

In some implementations the pl urali t of quantum gates comprise a plurality of X- controlled Y gates, wherein each X-controlled Y gate applies a Y gate to a target physical qubit when a control physical qubit is in a minus state.

In some implementations he plurality of quantum gates comprise a plurality of square root X gates. In some implementations the plurality of quantum gates comprise single qubit gates, and applying the plurality of quantum gates to physical qubits on the diagonal line comprises applying a layer of the single qubit gates to the physical qubits on the diagonal line and applying the layer of Hadamard gates to the second subset of physical qubits simultaneously.

In some implementations the plurality of quantum gates comprise two-qubit gates, performing the four coupler surface code cycle and the three coupler surface code cycle comprises apply ing multiple layers of entangling operations to the first subset of physical qubits and the second subset of physical qubits, and applying the plurality of quantum gates to physical qubits on the diagonal line comprises applying a first layer of the two-qubit gates to the physical qubits on the diagonal line and applying one of the multiple layers of entangling operations to the first subset of physical qubits and the second subset of physical qubits simultaneously.

In some implementations the one of the multiple layers of entangling operations comprise a first set of entangling operations that are applied to the first subset of physical qubits and a second set of entangling operations that are applied to the second subset of physical qubits, and a direction of controls of the first set of entangling operations are different to a direction of controls of the second set of entangling operations.

In some implementations the method further comprises applying a second layer of the two-qubit gates to the physical qubits on the diagonal line prior to applying the layer of Hadamard gates to the second subset of physical qubits.

In some implementations applying the layer of Hadamard gates to the second subset of physical qubits changes boundary types of the logical qubit from XZXZ to XXZZ.

In some implementations the method further comprises repeatedly measuring surface code stabilizers of the physical qubits included in the logical qubit to compute the Y observable of the logical qubit to arbitrary accuracy.

In some implementations the plurality of physical qubits comprise data qubits and wherein the method further comprises measuring the data qubits, comprising measuring each data qubit in a basis of a boundary of the logical qubit that is closest to the data qubit.

In some implementations performing the three coupler surface code cycle on the second subset of physical qubits included in the logical qubit compnses measuring measure qubits included in the second subset of physical qubits, and performing the four coupler surface code cycle on the first subset of physical qubits included in the logical qubit comprises measuring measure qubits included in the first subset of physical qubits. In some implementations performing the four coupler surface code cycle on the first subset of physical qubits included in the logical qubit comprises initializing measure qubits included in the first subset of physical qubits, and performing the three coupler surface code cycle on the second subset of physical qubits included in the logical qubit comprises initializing measure qubits included in the second subset of physical qubits.

Another innovative aspect of the subject matter described in this specification can be implemented in a method that includes identifying a braiding of Y-type surface code defects for a target quantum computing operation; determining an optimized braiding of the Y-type surface code defects, wherein the optimized braiding of the Y-type surface code reduces a computational duration of the target quantum computing operation subject to logical error mechanisms for the target quantum computing operation; determining spacetime surface code defects for the optimized braiding of Y-type surface code defects based on the logical error mechanisms for the target quantum computing operation; determining a configuration of surface code stabilizers for implementing the target quantum computing operation using the spacetime surface code defects; and determining a quantum circuit that implements the determined configuration of surface code stabilizers.

Other implementations of these aspects includes corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations the logical error mechanisms comprise a time-like Y error mechanism and a time-like XZ error mechanism, wherein the time-like Y error mechanism and the time-like XZ error mechanism determine a minimum duration of the target quantum computing operation and bases for data qubit measurements.

In some implementations the logical error mechanisms comprise a space-like Y error mechanism, wherein the space-like Y error mechanism incentivizes the size of the logical qubit and orientation of two qubit operations in the quantum circuit. In some implementations the logical error mechanisms comprise a switch assisted error mechanism, wherein the switch assisted error mechanism incentivizes orderings of operations included in the quantum circuit.

In some implementations determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that: measures stabilizers of an input logical qubit that comprises a plurality of physical qubits; maintains boundary types of the logical qubit as specified by the spacetime surface code defects; and prepares stabilizers of an output of the logical qubit.

In some implementations the target quantum computing operation is a Y observable measurement.

In some implementations the braiding of Y-type surface code defects for the target quantum computing operation is equivalent to a braiding of Y-ty pe surface code defects for an S gate and a X basis measurement operation.

In some implementations determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that transforms boundary types of the logical qubit from XZXZ to xxzz

In some implementations the logical qubit with XXZZ boundary type stabilizes an observable running along an XX portion of the XXZZ boundary and the determined configuration of surface code stabilizers converts the observable into a Y observable.

In some implementations determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that: transforms a Y observable of a logical qubit that comprises a plurality of physical qubits into a product of X basis surface code stabilizers whilst measuring the surface code stabilizers.

In some implementations the spacetime surface code defects comprise X-type defects, Y-type defects, H-type defects, and I -type defects.

In some implementations the method further comprises implementing, by a quantum computer, the quantum circuit to perform the target quantum computing operation.

The subject matter described in this specification can be implemented in particular ways so as to realize one or more of the following advantages.

Because the surface code is a CSS code, its X and Z observables can be measured transversally. However, the Y observable cannot be measured transversally, and so must be measured by other means. The cost of Y basis measurement is relevant to the overall cost of surface code computations because, in many magic state factory designs, distilling a magic state involves hundreds of Y basis measurements. As an example, if running Shor’s algorithm costs a billion Toffoli gates then, by implication, running Shor’s algorithm also costs hundreds of billions of Y basis measurements. The inefficiency of magic state factories magnifies the benefits of improving the cost of Y basis measurement.

Some conventional strategies for Y basis measurement and initialization in the surface code are based on |i) states and include: double-defect qubits state distillation, double-defect qubits state catalysis, or patch qubits twist braiding that allows | i) states to be reached without distillation. Some realizations of the latter strategy can achieve a spacetime volume of 2d x 2d x d. However, a system implementing the presently described techniques can reduce the spacetime volume of such strategies. In particular, the presently described techniques can reduce the spacetime volume of Y basis measurement and initialization to d x d x | d, saving nearly another order of magnitude in the cost of reaching the Y basis.

Another conventional strategy for Y basis measurement and initialization in the surface code is based on folding the surface code patch. In a folded surface code patch, Y basis measurement can be performed in constant depth. However, folding the surface code patch requires non-planar connectivity (or substantial routing overhead) and is therefore not suitable for many quantum computing architectures, e.g., superconducting qubit chips. However, the presently described techniques do not require non-planar connectivity and can be applied to quantum computing architectures with planar connectivity without incurring routing overheads.

In addition, some conventional strategies for measuring a surface code qubit in the Y basis require the size of the surface code patch to be increased, in order to move twist defects without letting them get too close to each other. However, the presently described techniques do not require resizing of the surface code patch and therefore require less computational resources, e g., less physical qubits. In addition, the net logical error rate of the presently described techniques are lower than conventional strategies.

The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example system for performing Y basis measurements in the surface code.

FIG. 2 is a flowchart of an example process for measuring a Y observable of a logical qubit that includes a multiple physical qubits.

FIG. 3 illustrates an example flow of surface code stabilizers in a surface code patch during a Y observable measurement surface code cycle and after the Y observable measurement surface code cycle.

FIGS. 4A-D show layers of an example quantum circuit for measuring a Y observable of a logical qubit that includes a multiple physical qubits.

FIG. 5 is a flowchart of an example process for generating a quantum circuit that implements a target quantum computing operation in the surface code.

FIG. 6A shows an illustration of a braiding of Y-type surface code defects in a surface code patch for a Y-basis measurement operation.

FIG. 6B shows an example optimized braiding of Y-type defects for a Y-basis measurement.

FIG. 6C shows an example spacetime surface code defect diagram for an optimized braiding of Y-type defects for a Y-basis measurement.

FIG. 7 shows example observable slice diagrams of the surface code cycle where the Y observable of the logical qubit is transformed into a product of X basis surface code stabilizers.

FIG. 8A shows layers of an example quantum circuit for performing a Y basis memory experiment.

FIG. 8B shows a graph that plots number of padding rounds versus logical error rate (per shot) for various code distances in the Y basis memory experiment.

FIG. 9 depicts an example quantum computer.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of an example system for performing Y-basis measurements in the surface code. The example system 100 is an example of a system implemented as part of a classical and quantum computing device in which the systems, components and techniques described in this specification can be implemented.

The system 100 includes multiple qubits 102 in communication with control electronics 104. The qubits 102 are physical qubits, e.g., physical devices that behave as a two-state quantum system. Each qubit can be in a respective quantum state that occupies one or more levels. The levels include two computational levels, e.g., levels 0- and 1-, and one or more non-computational levels that are each higher than the computational qubit levels, e.g., levels 2- and 3-. Population of the higher, non-computational qubit levels can introduce errors in algorithmic operations or quantum computations performed using the qubit. For example, the occupation of qubit levels outside the computational subspace can hamper or prevent the implementation of quantum error correction operations.

In some implementations the qubits 102 can be superconducting qubits or semiconducting qubits. For example, the qubits 102 can include Xmon qubits, flux qubits, phase qubits, or qubits with frequency interactions. Generally, the qubits 102 are physical devices that are configured to meet basic requirements for quantum computation. For example, the qubits 102 include physical devices that can be initialized, can perform singlequbit rotations, can participate in two-qubit entangling operations, e.g., CZ and CNOT, gates, can perform a topological version of the Hadamard transformation, e.g., by exchanging their quantum states in a SWAP operation, and can be measured.

The qubits 102 are arranged in an array. For example, as shown in FIG. 1, in some implementations the qubits 102 can be arranged as a two dimensional square grid 110. The example two dimensional grid 110 depicted in FIG. 1 includes 11 x 7 = 77 qubits, however in some implementations the system 100 may include a smaller or a larger number of qubits.

The qubits 102 can interact with each other through multiple qubit couplers. The qubit couplers can define nearest neighbor interactions between qubits, e.g., such that in a square grid each qubit interacts with at most four neighboring qubits or in a hex grid each qubit interacts with at most three neighboring qubits. The couplers can, in principle, be any type of coupler, e.g., a capacitive or inductive coupler. In some implementations the strengths of the couplers can be controllable, e.g., frequency controllable. In other implementations the couplers can be couplers with a fixed coupling strength.

The control electronics 104 include control devices, e.g., arbitrary waveform generators, that can operate the multiple qubits 102. For example, the control electronics 104 can include control devices that tune operating frequencies of the qubits 102 by applying control signals, e.g., voltage pulses, to the qubits through respective control lines. As another example, the control electronics 104 can control individual frequencies of the qubits 102 such that the frequency of one or more of the qubits are adjusted towards or away from a frequency of an excitation pulse generated by an excitation pulse generator on an excitation driveline. The excitation pulses can include pulses with frequencies that implement quantum operations, e.g., quantum logic gates. The qubits 102 can be coupled to an excitation driveline via respective couplers. In some cases the couplers can be capacitive couplers, e.g., realized by a microwave line running adjacent to a qubit capacitor.

The control electronics 104 can also include control devices that tune frequencies of the couplers that couple the multiple qubits 102.

The type of control electronics 104 that the system 100 utilizes is dependent on the type of qubits the system uses. As an example, qubits that are realized via atomic, molecular or solid-state quantum systems typically have energy separation of the relevant qubit levels in the microwave or optical domain. The states of such qubits may be manipulated and controlled using external fields, such as microwave or optical fields. In such cases, as an example, mode-locked lasers may serve as control electronics due to their broad-band optical spectra that feature both radio frequency and microwave structure. In another example, the control electronics 104 could include a collection of individual qubit controllers realized by a radio frequency generator as well as one or a collection of global excitation controllers realized by a radio frequency or microwave generator. In both cases, the control electronics 104 can be operated manually or connected to a computer and controlled via suitable software allowing for specifying and automatically running the required qubit operations.

The control electronics 104 can be programmed to perform surface code quantum computations. To implement the surface code, each qubit in the multiple qubits 102 has one of two functional types: data qubits, e.g., qubit 106, and measure qubits, e.g., qubit 108. A data qubit, e.g., qubit 106, is a qubit that participates in quantum computations performed by the system 100 and stores quantum information corresponding to the quantum computations. That is, the state of the data qubit encodes logical information for a quantum computation. A measure qubit is a qubit that is used to determine an outcome of a computation performed by the data qubit. For example, during a computation an unknown state of the data qubit can be entangled with the state of the measure qubit using a suitable physical operation, after which the measure qubit can be measured. The measure qubits can include measure-X qubits, e g., measure qubits located in centers of light grey squares such as square 128, and measure-Z qubits, e.g., measure qubits located in centers of dark grey squares such as square 130. Each data qubit is directly coupled to multiple measure qubits (and is not directly coupled to any other data qubits) and each measure qubit is directly coupled to multiple data qubits (and is not directly coupled to any other measure qubits). For example, in a four coupler surface code each measurement qubit is coupled to four data qubits (if the measure qubit is in the bulk, if it is at the boundary it is coupled to less data qubits). Each data qubit is coupled to two measure-Z qubits and to two measure-X qubits (if the data qubit is at in the bulk, if the data qubit is at the boundary it is coupled to less measure qubits). In the four coupler surface code, a measure-Z qubit is a qubit that can be used to force its neighboring data qubits a, b, c and d into an eigenstate of the operator product Z_aZ_bZ_cZ_d where Z_a represents a Pauli-Z operator acting on qubit a. Each measure-Z qubit is therefore described as measuring a ZZZZ stabilizer. In the example array 102 of FIG. 1, ZZZZ stabilizers are represented by the darker grey squares, e.g., square 130, where data qubits exist at the vertices of the ZZZZ stabilizers and measure-Z qubits exist at the center of each ZZZZ stabilizer. A measure-X qubit is a qubit that can be used to force its neighboring data qubits a, b, c and d into an eigenstate of the operator product X_aX_bX_cX_d where X_a represents a Pauli-X operator acting on qubit a. Each measure-X qubit is therefore referred to as measuring a XXXX stabilizer. In the example array 102 of FIG. 1, XXXX stabilizers are represented by the lighter grey squares, e.g., square 128, where data qubits exist at the vertices of the XXXX stabilizers and measure-X qubits exist at the center of each XXXX stabilizer.

As another example, in a three coupler surface code each measurement qubit is coupled to three data qubits (if the measure qubit is in the bulk, if it is at the boundary it is coupled to less data qubits). Each data qubit is coupled to three measure qubits (if the data qubit is at in the bulk, if the data qubit is at the boundary it is coupled to less measure qubits).

A collection of measure qubits and data qubits is referred to as surface code patch and forms a logical qubit. The control electronics 104 can operate a surface code patch by repeatedly applying a quantum circuit to the measure qubits and data qubits included in the patch. Each application of the quantum circuit performs one surface code cycle. Each quantum circuit includes a sequence of operations. For example, in a four coupler surface code construction, first, each measure qubit is reset, e.g., in a ground state. Then, four layers of entangling operations, e.g., CNOT gates or CZ gates, are performed. For measure-Z qubits, each of the four layers of entangling operations targets the measure qubits and nearest-neighbor data qubits act as controls for respective entangling operations. For measure-X qubits, each of the four layers of entangling operations targets nearest-neighbor data qubits and the measure-X qubits act as controls for each of the four entangling operations. In this case, the sequence of operations also includes a layer of Hadamard gates applied to the measure qubits before and after the entangling operations. After the entangling operations are performed, the measure qubits are measured, e.g., through projective measurement. Following measurement, a subsequent surface code cycle is performed.

Errors on the physical qubits (either on the data qubits or measure qubits) can be detected at each surface code cycle using measurement results obtained during the surface code cycle. Errors can occur due to single qubit errors (erroneous X, Y or Z operations), measurement errors (reporting the incorrect outcome and projecting to the wrong state), initialization errors (setting a qubit to the wrong state), Hadamard errors (performing a Hadamard but in addition performing an erroneous X, Y, or Z), and CNOT errors. Concatenations of errors can also occur. Once errors are detected, subsequent measurement outcomes can be appropriately corrected, e.g., using classical control software.

Detection events in the surface code can be classified into two types (X and Z), based on whether they are associated with measurement results indicating that an X type or Z type stabilizer has changed unexpectedly. In the bulk of a surface code circuit, all errors produce an even number of detection events of each type. In other words, the bulk of the surface code “conserves X parity” and “conserves Z parity”. These two conservation properties are what define the bulk. Any circuit location where Pauli errors conserve X detection event parity and conserve Z detection event parity is part of the bulk, regardless of the specific implementation details of the circuit.

Defects are circuit locations where X parity conservation and/or Z parity conservation is broken, because errors can produce an odd number of X detection events and/or an odd number of Z detection events. Locations in the circuit where an odd number of X detection events can be produced by an error are X type defects and are sometimes referred to as “X boundaries”. X type defects effectively absorb X detection events. Locations where an odd number of Z detection events can be produced by an error are Z type defects and are sometimes referred to as “Z boundaries". Z type defects effectively absorb Z detection events. Locations where an error can produce one X detection event paired with one Z detection event, breaking the individual X and Z parities but not necessarily the combined X + Z parity, are H type defects or Y type defects. H type defects effectively cross link X e Z detection events across the domain wall and are sometimes referred to as “domain walls”. Y type defects effectively absorb adjacent X ■ Z detection events and are referred to herein as “twists”. A surface code patch has four Y-type defects, one at each comer of the patch.

The distinction between H type defects and Y type defects is whether or not it is possible to use the defect to terminate a combined chain of X errors and Z errors arriving from the same direction. An H ty pe defect cannot be used to terminate such a chain, because the relevant errors always place the relevant X/Z detection events on opposite sides of the wall. A Y type defect differs in that it can terminate such a chain. For example, when a domain wall ends in the bulk, it always ends on a Y type defect because at that location one of the errors can go around the wall to meet the detection event hiding on the other side of the wall.

Defects can span across time. Defects that span across time can be visually represented as spacetime diagrams, where X-type defects are represented as 2D surfaces, Z- type defects are represented as 2D surfaces, H-type defects are represented as 2D surfaces, and Y-type defects are represented as ID paths. These paths are referred to as “braids” or a “braiding of Y-type defects.” Example spacetime diagrams are described below with reference to FIGS. 6A-C.

The system 100 is configured to perform quantum computing operations in the surface code, e.g., perform logical operations on logical qubits that are stabilized using surface code error detection cycles. An example quantum computing operation is Y-basis measurement (also referred to herein as measurement of a Y observable of a logical qubit). A Y basis measurement can be decomposed into an S gate followed by an X basis measurement. The topology of the S gate is to exchange two twists at the ends of an X-type boundary of the surface code patch. The topology of the X basis measurement is to pair twists that share a Z type boundary, and then within each pair annihilate the twists by fusing them. The topological result of composing these two operations also fuses twist defects, but it pairs the twist defects across the diagonals of the patch. Therefore, the topology of the Y basis measurement is to fuse twists diagonally.

To perform a Y-basis measurement on a logical qubit, the control electronics 104 can be programmed to apply a quantum circuit to physical qubits included in the logical qubit, where the quantum circuit implements this twist movement, i.e., moves the twist diagonally across the logical qubit. In some implementations the control electronics can be configured to receive data specifying a quantum circuit construction for performing a Y-basis measurement on a logical qubit, e.g., data 124. In other implementations the system 100 can include components, e.g., classical processors, that are configured to construct a quantum circuit for performing a Y-basis measurement on a logical qubit. An example process for generating a quantum circuit that implements a target quantum computing operation in the surface code, e.g., a Y basis measurement, is described below with reference to FIGS. 5 and 6A-C.

When applied to the logical qubit, the quantum circuit implements a four coupler surface code cycle on a first subset of physical qubits included in the logical qubit to measure surface code stabilizers of the first subset of physical qubits. The quantum circuit also implements a three coupler surface code cycle on a second subset of physical qubits included in the logical qubit to measure surface code stabilizers of the second subset of physical qubits. The first subset of physical qubits and the second subset of physical qubits intersect along a diagonal line of physical qubits included in the logical qubit. For example, the quantum circuit can implement a four coupler surface code cycle on a lower left portion of the logical qubit and implement a three coupler surface code cycle on an upper right portion of the logical qubit, where the two portions join at a diagonal line that reaches from a top left comer of the logical qubit to a lower right comer of the logical qubit.

By constmction, the three coupler surface code cycle has a “walking effect” and moves information encoded in the physical qubits on which it operates in a same direction in the qubit array. For example, X stabilizers can move to neighboring physical qubits that are below the original physical qubits and Z stabilizers can move to neighboring physical qubits that are to the left of the original qubits. This walking effect implements the domain wall defect that is attached to the crossing twist. Single qubit and two-qubit quantum gates are applied to physical qubits on the diagonal line to mesh the four coupler surface code cycle and the three coupler surface code cycle. A layer of Hadamard gates are applied to the second subset of physical qubits to implement the change in boundary types of the logical qubit, as required by the crossing twist. The movement of surface code stabilizers during the surface code cycle is illustrated in box 122 and described in more detail below with reference to FIG. 3.

After the four coupler surface code cycle and three coupler surface code cycle have been performed, all stabilizers of the physical qubits included in the logical qubit have been measured. Corresponding measurement results can be used to compute the Y observable of the logical qubit. In particular, the value of the Y observable can be computed by multiplying measured X basis surface code stabilizers together.

An example process and example quantum circuits for measuring a Y observable of a logical qubit that includes multiple physical qubits are described in more detail below with reference to FIGS. 2-4D. For brevity, the present disclosure focuses on operations performed to measure a Y observable of a logical qubit (Y basis measurement). Y basis initialization can be performed by time reversing the operations described for Y basis measurement.

FIG. 2 is a flowchart of an example process 200 for measuring a Y observable of a logical qubit that includes a multiple physical qubits. For convenience, the process 200 will be described as being performed by components of a quantum computing system. For example, a quantum computer, e.g., the system 100 of FIG. 1 or the quantum computer 700 of FIG. 7, appropriately programmed, can perform example process 200.

The system measures surface code stabilizers of the physical qubits included in the logical qubit (step 202). To measure the surface code stabilizers of the physical qubits included in the logical qubit, the system performs steps 202a-c described below. Steps 202a- c can be performed simultaneously (e.g., within limits of the quantum computing hardware performing the experimental implementation).

The system performs a four coupler surface code cycle on a first subset of physical qubits included in the logical qubit to measure surface code stabilizers of the first subset of physical qubits (step 202a). To perform the four coupler surface code cycle the system initializes measure qubits included in the first subset of physical qubits and then applies multiple layers of entangling operations to the first subset of physical qubits, as described above with reference to FIG. 1. The system then measures the measure qubits included in the first subset of physical qubits. An example four coupler surface code cycle is described in more detail below with reference to FIGS. 4A-D.

The system performs a three coupler surface code cycle on a second subset of physical qubits included in the logical qubit to measure surface code stabilizers of the second subset of physical qubits (step 202b). The second subset of physical qubits is different to the first subset of physical qubits. The first subset of physical qubits and the second subset of physical qubits intersect along a diagonal line of physical qubits included in the logical qubit. By the subsets intersecting in this manner, the diagonal line of physical qubits can separate the first and second subsets such that qubits on one side of the diagonal line belong to on set and qubits on another side belong to another subset. The physical qubits on the diagonal line may belong to neither subset, or alternatively may belong to one or both subsets. For example, the first subset of physical qubits can include physical qubits in a lower left diagonal half of the logical qubit and the second subset of physical qubits can include physical qubits in an upper right diagonal half of the logical qubit.

To perform a conventional three coupler surface code cycle, the system initializes measure qubits included in the second subset of physical qubits, applies multiple layers of entangling operations to the first subset of physical qubits, and measures the measure qubits included in the second subset of physical qubits. In the presently described process for measuring a Y observable, the system also applies a layer of Hadamard gates to the second subset of physical qubits prior to measuring the measure qubits. Application of the layer of Hadamard gates changes the boundary types of the logical qubit from XZXZ to XXZZ. An example three coupler surface code cycle is described in more detail below with reference to FIGS. 4A-D.

The system applies multiple layers of quantum gates to physical qubits on the diagonal line such that error tracking of the four coupler surface code cycle and the three coupler surface code cycle is preserved (step 202c). The quantum gates include single qubit gates, e.g., square root X gates, and two-qubit gates, e.g., X-controlled Y gates, where each X-controlled Y gate applies a Y gate to a target physical qubit when a control physical qubit is in a minus state.

The number and form of the multiple layers of quantum gates is dependent on the specific implementations of the four coupler surface code cycle and three coupler surface code cycle, e.g., the order in which the entangling operations are performed and the type of entangling operations performed, and can vary.

For example, in some implementations the system can apply one layer of single qubit gates to the physical qubits on the diagonal line at the same time (e.g., within limits of the quantum computing hardware performing the experimental implementation) in which the layer of Hadamard gates is applied to the second subset of physical qubits.

As another example, in some implementations the system can apply a first layer of two-qubit gates to the physical qubits on the diagonal line prior to application of the layer of Hadamard gates to the second subset of physical qubits.

As another example, in some implementations the system can apply a second layer of two-qubit gates to the physical qubits on the diagonal line and one of the layers of entangling operations to the first subset of physical qubits and the second subset of physical qubits simultaneously (e.g., within limits of the quantum computing hardware performing the experimental implementation). In this example, the direction of controls used in the entangling operations applied to the first subset of physical qubits are different to the direction of controls used in the entangling operations applied to the second subset of physical qubits. This is illustrated and described below with reference to FIGS. 4A-D.

The system multiplies measured X basis surface code stabilizers to compute the Y observable of the logical qubit (step 204). FIG. 7 described below shows example observable slice diagrams of the surface code cycle where the Y observable of the logical qubit is transformed into a product of X basis surface code stabilizers.

In some implementations the system can repeatedly perform steps 202 and 204 to compute the Y observable of the logical qubit to arbitrary accuracy, e.g., d/2 + 0(1) times where d represents the code distance. In some implementations the process for measuring the Y observable can be completed by measuring the data qubits included in the logical qubit. To maximize code distance, the system can measure each data qubit in the basis of a boundary of the logical qubit that is closest to the data qubit.

FIG. 3 illustrates an example flow of surface code stabilizers in a surface code patch (logical qubit) during a Y observable measurement surface code cycle 302 and after the Y observable measurement surface code cycle 304. In both surface code patches 302 and 304, lighter shaded shapes, e.g., square 306, represent X stabilizers and darker shaded shapes, e.g., square 308, represent Z stabilizers. In this example, physical qubits located below the diagonal line 314 correspond to the first set of physical qubits described above with reference to example process 200 of FIG. 2. Physical qubits located above the diagonal line 314 correspond to the second set of physical qubits described above with reference to example process 200 of FIG. 2.

During the Y observable measurement surface code cycle, the physical qubits located below the diagonal line 314 perform a four coupler surface code cycle. Therefore, the surface code stabilizers in this region of the surface code patch do not logically move or change. The physical qubits located above the diagonal line 314 perform a three coupler surface code cycle. Therefore, the X stabilizers in this region of the surface code patch are moved one step downwards (as indicated by the solid arrows, e.g., arrow 310) and the Z stabilizers in this region of the surface code patch are moved one step to the left (as indicated by the grey shaded arrows, e.g., arrow 312). Although not explicitly illustrated in FIG. 3, transversal Hadamard gates turn the shifted X stabilizers into Z stabilizers, and vice versa. At the boundaries of the surface code patch, new stabilizers are introduced to replace the ones that moved inward (as indicated by the circles, e.g., circle 316). At the center diagonal 314, the X stabilizers stepping down merge into the Z stabilizers sitting along the diagonal. The labels “A, B, C” and “1, 2, 3” illustrate the flow of the surface code stabilizers. As shown in example surface code patch 304, after the Y observable measurement surface code cycle, the boundary of the surface code patch has changed from a XZXZ boundary to a XXZZ boundary.

FIGS. 4A-D show steps of an example quantum circuit for measuring a Y observable of a logical qubit that includes a multiple physical qubits.

Referring to FIG. 4A, in step 400 of the example quantum circuit, multiple reset operations are performed on each measure qubit in the logical qubit to initialize the measure qubits. Reset operations labeled “R”, e.g., reset operation 402, are applied to the measure-Z qubits and reset operations labelled “R_x”, e.g., reset operation 404, are applied to the measure-X qubits.

In step 406, a layer of entangling operations is applied to physical qubits located below the dashed diagonal line as part of a four coupler surface code cycle. In this example the layer of entangling operations includes CNOT gates, e.g., CNOT gate 408, that are applied between neighboring measure qubits and data qubits. In each CNOT gate, the measure qubit acts as the target (crossed circle) and the data qubit acts as a control (solid circle). At the same time, a layer of entangling operations is applied to physical qubits located above the dashed diagonal line as part of a three coupler surface code cycle. In this example the layer of entangling operations includes CNOT gates that are applied between neighboring measure qubits and data qubits. In each CNOT gate, the measure qubit acts as the target (crossed circle) and the data qubit acts as a control (solid circle).

Referring to FIG. 4B, in step 420 a layer of entangling operations is applied to physical qubits located below the dashed diagonal line as part of a four coupler surface code cycle and a layer of entangling operations is applied to physical qubits located above the dashed diagonal line as part of a three coupler surface code cycle. Step 420 of the example quantum circuit is similar to step 406 shown in FIG. 4A, except that the entangling operations are performed between different pairs of measure qubits and neighboring data qubits.

In step 422, a layer of entangling operations is applied to physical qubits located below the dashed diagonal line as part of a four coupler surface code cycle and a layer of entangling operations is applied to physical qubits located above the dashed diagonal line as part of a three coupler surface code cycle. The entangling operations performed in step 422 are similar to step 406 shown in FIG. 4A and step 420 in FIG. 4B, except that the entangling operations are performed between different pairs of measure qubits and neighboring data qubits. In addition, in step 422, a layer of quantum gates are applied to physical qubits located at the diagonal dashed line as part of the operations performed to preserve error tracking. In this example, the quantum gates include X-controlled Y gates, e.g., gate 424, where each X-controlled Y gate applies a Y gate to a target physical qubit (represented by the crossed circle) when a control physical qubit (represented by the shaded triangle) is in a minus state.

Referring to FIG. 4C, in step 430 a last layer of entangling operations is applied to physical qubits located below the dashed diagonal line as part of a four coupler surface code cycle and a last layer of entangling operations is applied to physical qubits located above the dashed diagonal line as part of a three coupler surface code cycle. Step 430 of the example quantum circuit is similar to step 406 shown in FIG. 4A, except that the entangling operations performed as part of the four coupler surface code cycle are performed between different pairs of measure qubits and neighboring data qubits (so that after step 406, 420, 422, and 430 each measure qubit in the bulk has performed an entangling operation with each of its neighboring data qubits).

In step 432, a layer of quantum gates are applied to physical qubits located at the diagonal dashed line as part of the operations performed to preserve error tracking. In this example, the quantum gates include X-controlled Y gates that are applied across the diagonal line at which the first subset and second subset meet.

Referring to FIG. 4D, in step 440, a layer of Hadamard gates, e.g., Hadamard gate 442, are applied to the physical qubits located above the diagonal dashed line (which participated in the three coupler surface code cycle). In addition, a layer of quantum gates are applied to physical qubits located at the diagonal dashed line as part of the operations performed to preserve error tracking. In this example, the quantum gates include square root X gates, e.g., gate 446. No operations are performed to physical qubits below the diagonal dashed line.

In step 448, measurement operations are applied to all measure qubits included in the logical qubit. Measure X qubits are measured in the X basis, e.g., using operation 452, and measure Z qubits are measured in the Z basis, e.g., using operation 450. Obtained measurement results are provided for processing, e.g., error detection and computation of the Y observable.

FIG. 5 is a flowchart of an example process 500 for generating a quantum circuit that implements a target quantum computing operation in the surface code. For example, example process 500 can be used to generate a quantum circuit that implements the operations described above with reference to FIGS. 2 to 4. For convenience, the process 500 will be described as being performed by components of a classical computing system. For example, a classical processor, e.g., the classical processor 714 of FIG. 7, appropriately programmed, can perform example process 500.

The system receives input specifying a target quantum computing operation and identifies a braiding of Y-type surface code defects for the target quantum computing operation (step 502). For example, the system can store or access a set of predefined or known braidings for various quantum computing operations. In some implementations, the system can identify the braiding of Y-type surface code defects for the target quantum computing operation by decomposing the target operation into a sequence of operations for which a topology and braiding is known.

FIG. 6A shows an illustration 600 of a braiding of Y-type surface code defects in a surface code patch for a Y-basis measurement operation. A Y-basis measurement operation can be decomposed into an S gate and an X basis measurement. Therefore, combining a spacetime defect diagram for an X basis measurement 602 and a spacetime defect diagram for an S gate 606 produces a spacetime defect diagram for a Y-basis measurement 606. In each spacetime defect diagram, 2D surfaces labelled “Z”, e.g., surface 614, represent Z-type defects in time, 2D surfaces labelled “X”, e.g., surface 616, represent X-type defects in time, and ID paths, e.g., path 618, represent Y-type defects in time (or “braids”). Focusing on the Y-type defects only, combining a braiding of Y-type defects for an X-basis measurement 608 with a braiding of Y-type defects for an S gate 610 produces a braiding of Y-type defects for a Y-basis measurement 612. As illustrated, the Y-defects cross.

Returning to FIG. 5, the system determines an optimized braiding of the Y-type surface code defects (step 504). The system optimizes the braiding of the Y-type surface code defects reduce a computational duration of the target quantum computing operation subject to predefined or known logical error mechanisms for the target quantum computing operation. For example, the system can optimize the braiding of the Y-type surface code defects reduce a computational duration of the target quantum computing operation subject to a time-like Y error mechanism. The time-like Y error mechanism is an error mechanism that terminates on time boundaries at the end of the measurement process of the surface code cycle. The time-hke Y error mechanism determines how fast the target quantum computation can be performed, i.e., determines a minimum duration of the target quantum computing operation. FIG. 6B shows the example braiding of Y-type defects for a Y-basis measurement 612 shown in FIG. 6A and an example optimized braiding of Y-type defects for a Y-basis measurement 622. The braiding 612 has been optimized to reduce the length of the braiding (which represents computational time/duration) subject to a time-like Y error mechanism 624 for the Y-basis measurement.

Returning to FIG. 5. the system determines spacetime surface code defects for the optimized braiding of Y-type surface code defects using the logical error mechanisms for the target quantum computing operation (step 506). For example, the system can use a time-like XZ error mechanism to determine bases for data qubit measurements. The time-like XZ error mechanism is also an error mechanism that terminates on time boundaries at the end of the measurement process of the surface code cycle. The system can also use a space-like Y error mechanism and switch assisted error mechanism to determine the spacetime surface code defects for the optimized braiding of Y-type surface code defects. The space-like Y error mechanism incentivizes the number of physical qubits (the size of the logical qubit) and the orientation of two qubit operations during the 2nd and 3rd layers of entangling gates of the transition cycle and adjacent cycles. Making the patch smaller, or changing the orientations of those gates, can result in the logical error rate increasing due to this error mechanism. The switch assisted error mechanism incentivize certain orderings of operations over others, as well as minimizing operations during the transition cycle.

Generally, the listed error mechanisms are important considerations because they can be used to inform choices of size, layout, and duration. For example, the time-like errors are suppressed by extending the number of rounds that the logical Y measurement process lasts. Therefore, the number and strength of the time-like errors is useful for deciding how long the measurement should last. The error mechanisms are a key constraint that shape the design of the operation.

FIG. 6C shows an example spacetime surface code defect diagram 642 for the optimized braiding of Y-type defects for a Y-basis measurement 622 of FIG. 6B. In the spacetime surface code defect diagram 642 2D surfaces labelled “Z”, e.g., surface 644, represent Z-type defects in time, 2D surfaces labelled "X". e.g., surface 646, represent X-type defects in time, ID paths, e.g., path 648, represent Y-type defects in time (or "braids"), and opaque 2D surfaces, e.g., surface 650, represent H-type defects. The spacetime surface code defects included in the spacetime surface code defect diagram 642 have been determined using the time-hke XZ error mechanism 652, input error mechanism 654, space-like Y error mechanism 656, and switch assisted error mechanism 658 for the Y-basis measurement (where each error mechanism is illustrated in FIG. 6B and 6C by respective small cylinders).

Returning to FIG. 5, the system determines a configuration of surface code stabilizers for implementing the target quantum computing operation (step 508). The system uses the spacetime surface code defects determined at step 506 to determine the configuration of surface code stabilizers, e.g., identifies a configuration of surface code stabilizers that is consistent with the spacetime surface code defects. A configuration of surface code stabilizers for a logical qubit is consistent with a spacetime surface code defect diagram if the configuration of surface code stabilizers maintains boundary types of the logical qubit as specified by the spacetime surface code defects. For example, in implementations where the target quantum computing operation is a Y basis measurement, the system determines a configuration of surface code stabilizers that transforms boundary types of the logical qubit from XZXZ to XXZZ. The logical qubit with XXZZ boundary type stabilizes an arbitrary observable running along an XX portion of the XXZZ boundary, therefore the determined configuration of surface code stabilizers converts the observable into a Y observable. In other words, the Y observable of the logical qubit is transformed into a product of X basis surface code stabilizers.

Further, a configuration of surface code stabilizers for a logical qubit is consistent with a spacetime surface code defect diagram if the configuration of surface code stabilizers implements H-type defects specified by the spacetime surface code defects. One method to implement the H-type defects is to logically moving surface code stabilizers, e.g., inwards. Other methods can also be used, as long as spacetime is divided into two regions such that errors crossing the division link X detection events with Z detection events, instead of X with X and Z with Z with no mixing. The configuration of surface code stabilizers should also measure all surface code stabilizers of the input logical qubit (so that the configuration can reliably perform error detection) and prepare stabilizers of an output of the logical qubit (so that when the round of error correction finishes, all the stabilizers of the output of the logical qubit are actually stabilizers of the current state of the system.)

The system determines a quantum circuit that implements the configuration of surface code stabilizers (step 510). The system can then cause a quantum computer to implement the quantum circuit to perform the target quantum computing operation, e.g., by sending instructions to control electronics included in the quantum computer. Example quantum circuits determined by the system at step 510 are described above with reference to FIGS. 1 to 4. FIG. 7 shows example observable slice diagrams of the surface code cycle where the Y observable of the logical qubit is transformed into a product of X basis surface code stabilizers. Observable slice diagrams are diagrams that show the locations of terms of the observable being measured at a given time. In each observable slice diagram, shaded circles represent terms of the observable after the operations form the respective step of the surface code cycle have been executed. Unfilled circles represent terms of the observable from before the operations from that step of the surface code were executed.

In step 1 of the surface code cycle, the observable slice diagram shows that terms of the observable form a typical Y basis observable. Shaded circles above the diagonal dashed line 702, e.g., shaded circle 706, represent Z terms of the observable. The dashed shaded circle 704 represents a Y term of the observable. The remaining shaded circles under the diagonal dashed line 702, e.g., shaded circle 708, represent X terms of the observable.

In step 2 of the surface code cycle, single qubit terms prepared by reset gates are added into the Y basis observable. Again, shaded circles above the diagonal dashed line represent Z terms of the observable. The dashed shaded circle represents the Y term of the observable. The remaining shaded circles under the diagonal dashed line represent X terms of the observable.

In steps 3-8 of the surface code cycle, the Y basis observable is deformed through application of Clifford operations (as described, e.g., above with reference to example process 200 of FIG. 2). Again, in steps 3-7 of the surface code cycle, shaded circles above the diagonal dashed line represent Z terms of the observable. The dashed shaded circle represents the Y term of the observable. The remaining shaded circles under the diagonal dashed line represent X terms of the observable. In step 8 of the surface code cycle, the dashed shaded circle represents the Y term of the observable and all remaining shaded circles represent X terms of the observable.

In step 9 of the surface code cycle, all terms of the Y basis observable disappear into measurements and the Y basis observable has been measured. The dashed unfilled circle represents the Y term of the observable before the measurements are performed. The remaining unfilled circles all represent X terms of the observable before the measurements are performed. Although the Y basis observable is physically measured at step 9 of the surface code cycle, additional rounds of stabilizer measurements can be implemented in order to correct errors during its removal and complete the logical measurement. FIG. 8A shows layers of an example quantum circuit for performing a Y basis memory experiment (where the layers begin at the top and are ordered left to right). In a memory experiment, a known logical state is initialized, protected against noise for some number of rounds of the surface code cycle, and then measured. The experiment succeeds if the measured state agrees with the prepared state, after error correction has been performed. Access to a Y basis measurement (and, by time reversal, aY basis initialization), allows a Y basis memory experiment to be defined.

To perform a Y basis memory experiment using the presently described techniques for Y-basis measurement, a surface code cycle that implements Y basis initialization is performed on a logical qubit, e.g., by running the example process for Y basis measurement described above with reference to FIGS. 2-4D in reverse. The logical qubit then idles for a number of rounds. Then, a surface code cycle that implements Y basis measurement is performed on the logical qubit, e.g., according to e example process for Y basis measurement described above with reference to FIGS. 2-4D. The measured value of the Y basis measurement can then be compared to a prepared input value to determine how well prepare- and-idle-and-measure operations can be performed (which provides an indication of the performance of the quantum computing hardware that implements the Y basis memory experiment).

In FIG. 8A, layers 1-12 of the example quantum circuit correspond to two idling rounds, where in each idling round a conventional four coupler surface code cycle is performed. Layers 13-20 of the example quantum circuit correspond to a Y basis initialization operation. Layers 21-32 of the example quantum circuit correspond to two idling rounds, where in each idling round a conventional four coupler surface code cycle is performed. Layers 33-40 of the example quantum circuit correspond to a Y basis measurement operation. Layers 41-52 of the example quantum circuit correspond to two idling rounds, where in each idling round a conventional four coupler surface code cycle is performed.

The Y basis memory experiment can be used to experimentally determine the optimal number of padding rounds to use for Y basis initialization and Y basis measurement. If not enough padding rounds are used, time-like error mechanisms become dominant and limit the fidelity. However, the benefit of adding padding rounds saturates once these time-like error mechanisms have been suppressed below a noise floor set by space-like error mechanisms. FIG. 8B shows a graph 850 that plots number of padding rounds versus logical error rate (per shot) for various code distances in the Y basis memory experiment. When the number of padding rounds is too small, the error rate is limited by time-like errors. As shown, when the number of padding rounds is increased, the effect of time-like errors is exponentially suppressed until they become negligible relative to space-like error mechanisms. The benefits of adding padding rounds saturates at around d/2 padding rounds, where d represents the code distance.

FIG. 9 depicts an example quantum computer 900 for performing the quantum operations described in this specification. The example quantum computer 900 includes an example quantum computing device 902. The quantum computing device 902 is intended to represent various forms of quantum computing devices. The components shown here, their connections and relationships, and their functions, are exemplary only, and do not limit implementations of the inventions described and/or claimed in this document.

The example quantum computing device 902 includes a qubit assembly 952 and a control and measurement system 904. The qubit assembly includes multiple physical qubits, e.g., qubit 906, that are used to perform algorithmic operations or quantum computations. While the qubits shown in FIG. 9 are arranged in a rectangular array, this is a schematic depiction and is not intended to be limiting. The qubit assembly 952 also includes adjustable coupling elements, e.g., coupler 908, that allow for interactions between coupled qubits. In the schematic depiction of FIG. 9, each qubit is adjustably coupled to each of its four adjacent qubits by means of respective coupling elements. However, this is an example arrangement of qubits and couplers and other arrangements are possible, including arrangements that are non-rectangular, e.g., hexagonal, arrangements that allow for coupling between non-adjacent qubits, and arrangements that include adjustable coupling between more than two qubits.

Each qubit can be a physical two-level quantum system or device having levels representing logical values of 0 and 1. The specific physical realization of the multiple qubits and how they interact with one another is dependent on a variety of factors including the type of the quantum computing device 902 included in the example computer 900 or the type of quantum computations that the quantum computing device is performing. For example, in an atomic quantum computer the qubits may be realized via atomic, molecular or solid-state quantum systems, e.g., hyperfine atomic states. As another example, in a superconducting quantum computer the qubits may be realized via superconducting qubits or semi-conducting qubits, e.g., superconducting transmon states. As another example, in aNMR quantum computer the qubits may be realized via nuclear spin states. In some implementations a quantum computation can proceed by loading qubits, e.g., from a quantum memory, and applying a sequence of unitary operators to the qubits. Applying a unitary operator to the qubits can include applying a corresponding sequence of quantum logic gates to the qubits, e.g., to implement the surface code circuits described in this specification. Example quantum logic gates include single-qubit gates, e.g., Pauli-X, Pauli-Y, Pauli-Z (also referred to as X, Y, Z), Hadamard gates, S gates, rotations, two-qubit gates, e.g., controlled-X, controlled-Y, controlled-Z (also referred to as CX, CY, CZ), controlled NOT gates (also referred to as CNOT), iSWAP gates, and gates involving three or more qubits, e.g., Toffoli gates. The quantum logic gates can be implemented by applying control signals 910 generated by the control and measurement system 904 to the qubits and to the couplers.

For example, in some implementations the qubits in the qubit assembly 952 can be frequency tunable. In these examples, each qubit can have associated operating frequencies that can be adjusted through application of voltage pulses via one or more drive-lines coupled to the qubit. Example operating frequencies include qubit idling frequencies, qubit interaction frequencies, and qubit readout frequencies. Different frequencies correspond to different operations that the qubit can perform. For example, setting the operating frequency to a corresponding idling frequency may put the qubit into a state where it does not strongly interact with other qubits, and where it may be used to perform single-qubit gates. As another example, in cases where qubits interact via couplers with fixed coupling, qubits can be configured to interact with one another by setting their respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. In other cases, e.g., when the qubits interact via tunable couplers, qubits can be configured to interact with one another by setting the parameters of their respective couplers to enable interactions between the qubits and then by setting the qubit’s respective operating frequencies at some gate-dependent frequency detuning from their common interaction frequency. Such interactions may be performed in order to perform multi-qubit gates.

The type of control signals 910 used depends on the physical realizations of the qubits. For example, the control signals may include RF or microwave pulses in an NMR or superconducting quantum computer system, or optical pulses in an atomic quantum computer system.

A quantum computation can be completed by measuring the states of the qubits, e.g., using a quantum observable such as X, Y, or Z, using respective control signals 910. The measurements cause readout signals 912 representing measurement results to be communicated back to the measurement and control system 904. The readout signals 912 may include RF, microwave, or optical signals depending on the physical scheme for the quantum computing device and/or the qubits. For convenience, the control signals 910 and readout signals 912 shown in FIG. 9 are depicted as addressing only selected elements of the qubit assembly (i.e. the top and bottom rows), but during operation the control signals 910 and readout signals 912 can address each element in the qubit assembly 952.

The control and measurement system 904 is an example of a classical computer system that can be used to perform various operations on the qubit assembly 952, as described above, as well as other classical subroutines or computations. The control and measurement system 904 includes one or more classical processors, e.g., classical processor 914, one or more memories, e.g., memory 916, and one or more I/O units, e g., I/O unit 918, connected by one or more data buses. The control and measurement system 904 can be programmed to send sequences of control signals 910 to the qubit assembly, e.g. to carry out a selected series of quantum gate operations, and to receive sequences of readout signals 912 from the qubit assembly, e.g. as part of performing measurement operations and post processing measurement results.

The processor 914 is configured to process instructions for execution within the control and measurement system 904. In some implementations, the processor 914 is a single-threaded processor. In other implementations, the processor 914 is a multi-threaded processor. The processor 914 is capable of processing instructions stored in the memory 916.

The memory 916 stores information within the control and measurement system 904. In some implementations, the memory 916 includes a computer-readable medium, a volatile memory unit, and/or a non-volatile memory unit. In some cases, the memory 916 can include storage devices capable of providing mass storage for the system 904, e.g. a hard disk device, an optical disk device, a storage device that is shared over a network by multiple computing devices (e.g., a cloud storage device), and/or some other large capacity storage device.

The input/output device 918 provides input/output operations for the control and measurement system 904. The input/output device 918 can include D/A converters, A/D converters, and RF/microwave/optical signal generators, transmitters, and receivers, whereby to send control signals 910 to and receive readout signals 912 from the qubit assembly, as appropriate for the physical scheme for the quantum computer. In some implementations, the input/output device 918 can also include one or more network interface devices, e.g., an Ethernet card, a serial communication device, e.g., an RS-232 port, and/or a wireless interface device, e.g., an 802.8 card. In some implementations, the input/output device 918 can include driver devices configured to receive input data and send output data to other external devices, e.g., keyboard, printer and display devices.

Although an example control and measurement system 904 has been depicted in FIG. 9, implementations of the subject matter and the functional operations described in this specification can be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

Implementations of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, analog electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-embodied software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computational systems” may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

Implementations of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially- generated propagated signal that is capable of encoding digital and/or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and/or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term “qubit” encompasses all quantum systems that may be suitably approximated as a two- level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible.

The term “data processing apparatus” refers to digital and/or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and/or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and/or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A digital computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, e.g., QCL or Quipper.

A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a digital and/or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

The processes and logic flows described in this specification can be performed by one or more programmable computers, operating with one or more processors, as appropriate, executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and/or quantum computers.

For a system of one or more computers to be “configured to” perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. For example, a quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

Computers suitable for the execution of a computer program can be based on general or special purpose processors, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory, a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof .

The elements of a computer include a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital, analog, and/or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information. However, a computer need not have such devices. Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, the quantum circuit elements are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.

In certain cases, some or all of the quantum and/or classical circuit elements may be implemented using, e.g., superconducting quantum and/or classical circuit elements. Fabrication of the superconducting circuit elements can entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating circuit elements described herein can entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process can include, e.g., wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of 1.2 kelvin) and niobium (superconducting critical temperature of 9.3 kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.

In certain implementations, control signals for the quantum circuit elements (e.g., qubits and qubit couplers) may be provided using classical circuit elements that are electrically and/or electromagnetically coupled to the quantum circuit elements. The control signals may be provided in digital and/or analog form.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magnetooptical disks; CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Control of the various systems described in this specification, or portions of them, can be implemented in a computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or system that may include one or more processing devices and memory to store executable instructions to perform the operations described in this specification.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

What is claimed is:

Claims

1. A method implemented by a quantum computer for measuring a Y observable of a logical qubit comprising a plurality of physical qubits, the method comprising: measuring surface code stabilizers of the physical qubits included in the logical qubit, comprising: performing a four coupler surface code cycle on a first subset of physical qubits included in the logical qubit to measure surface code stabilizers of the first subset of physical qubits; performing a three coupler surface code cycle on a second subset of physical qubits included in the logical qubit to measure surface code stabilizers of the second subset of physical qubits, wherein: the first subset of physical qubits and the second subset of physical qubits intersect along a diagonal line of physical qubits included in the logical qubit, the first subset of physical qubits is different from the second subset of physical qubits, and performing the three coupler surface code cycle comprises applying a layer of Hadamard gates to the second subset of physical qubits prior to measuring the surface code stabilizers of the second subset of physical qubits; and applying a plurality of quantum gates to physical qubits on the diagonal line such that error tracking of the four coupler surface code cycle and the three coupler surface code cycle is preserved; and multiplying measured X basis surface code stabilizers to compute the Y observable of the logical qubit.

2. The method of claim 1, wherein the four coupler surface code cycle and the three coupler surface code cycle are performed simultaneously.

3. The method of claim 1 or claim 2, wherein the plurality of quantum gates comprise a plurality of X-controlled Y gates, wherein each X-controlled Y gate applies a Y gate to a target physical qubit when a control physical qubit is in a minus state.

4. The method of any one of the preceding claims, wherein the plurality of quantum gates comprise a plurality of square root X gates.

5. The method of any one of the preceding claims, wherein: the plurality of quantum gates comprise single qubit gates, and applying the plurality of quantum gates to physical qubits on the diagonal line comprises applying a layer of the single qubit gates to the physical qubits on the diagonal line and applying the layer of Hadamard gates to the second subset of physical qubits simultaneously.

6. The method of any one of the preceding claims, wherein: the plurality of quantum gates comprise two-qubit gates, performing the four coupler surface code cycle and the three coupler surface code cycle comprises applying multiple layers of entangling operations to the first subset of physical qubits and the second subset of physical qubits, and applying the plurality of quantum gates to physical qubits on the diagonal line comprises applying a first layer of the two-qubit gates to the physical qubits on the diagonal line and applying one of the multiple layers of entangling operations to the first subset of physical qubits and the second subset of physical qubits simultaneously.

7. The method of claim 6, wherein: the one of the multiple layers of entangling operations comprise a first set of entangling operations that are applied to the first subset of physical qubits and a second set of entangling operations that are applied to the second subset of physical qubits, and a direction of controls of the first set of entangling operations are different to a direction of controls of the second set of entangling operations.

8. The method of claim 6 or claim 7, further comprising applying a second layer of the two-qubit gates to the physical qubits on the diagonal line prior to applying the layer of Hadamard gates to the second subset of physical qubits.

9. The method of any one of the preceding claims, wherein applying the layer of Hadamard gates to the second subset of physical qubits changes boundary types of the logical qubit from XZXZ to XXZZ.

10. The method of any one of the preceding claims, further comprising repeatedly measuring surface code stabilizers of the physical qubits included in the logical qubit to compute the Y observable of the logical qubit to arbitrary accuracy.

11. The method of any one of the preceding claims, wherein the plurality of physical qubits comprise data qubits and wherein the method further comprises measuring the data qubits, comprising measuring each data qubit in a basis of a boundary of the logical qubit that is closest to the data qubit.

12. The method of any one of the preceding claims, wherein: performing the three coupler surface code cycle on the second subset of physical qubits included in the logical qubit comprises measuring measure qubits included in the second subset of physical qubits, and performing the four coupler surface code cycle on the first subset of physical qubits included in the logical qubit comprises measuring measure qubits included in the first subset of physical qubits.

13. The method of any one of the preceding claims, wherein: performing the four coupler surface code cycle on the first subset of physical qubits included in the logical qubit comprises initializing measure qubits included in the first subset of physical qubits, and performing the three coupler surface code cycle on the second subset of physical qubits included in the logical qubit comprises initializing measure qubits included in the second subset of physical qubits.

14. A quantum computing apparatus comprising: quantum computing hardware comprising: a plurality of physical qubits arranged on a grid; qubit couplers defining nearest neighbor interactions between the plurality of qubits; and control electronics configured to operate the plurality of qubits and qubit couplers; and a classical processor configured to receive and process data received from the quantum computing hardware; wherein the quantum computing apparatus is configured to perform operations according to the method of any one of claims 1 to 13.

15. A computer implemented method comprising: identifying a braiding of Y-type surface code defects for a target quantum computing operation; determining an optimized braiding of the Y-type surface code defects, wherein the optimized braiding of the Y-type surface code reduces a computational duration of the target quantum computing operation subject to logical error mechanisms for the target quantum computing operation; determining spacetime surface code defects for the optimized braiding of Y-type surface code defects based on the logical error mechanisms for the target quantum computing operation; determining a configuration of surface code stabilizers for implementing the target quantum computing operation using the spacetime surface code defects; and determining a quantum circuit that implements the determined configuration of surface code stabilizers.

16. The method of claim 15, wherein the logical error mechanisms comprise a time-like Y error mechanism and a time-like XZ error mechanism, wherein the time-like Y error mechanism and the time-like XZ error mechanism determine a minimum duration of the target quantum computing operation and bases for data qubit measurements.

17. The method of claim 15 or claim 16, wherein the logical error mechanisms comprise a space-like Y error mechanism, wherein the space-like Y error mechanism incentivizes the size of the logical qubit and orientation of two qubit operations in the quantum circuit.

18. The method of any one of claims 15 to 17, wherein the logical error mechanisms comprise a switch assisted error mechanism, wherein the switch assisted error mechanism incentivizes orderings of operations included in the quantum circuit.

19. The method of any one of claims 15 to 18, wherein determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that: measures stabilizers of an input logical qubit that comprises a plurality of physical qubits; maintains boundary ty pes of the logical qubit as specified by the spacetime surface code defects; and prepares stabilizers of an output of the logical qubit.

20. The method of any one of claims 15 to 19, wherein the target quantum computing operation is a Y observable measurement.

21. The method of claim 20, wherein the braiding of Y-type surface code defects for the target quantum computing operation is equivalent to a braiding of Y-type surface code defects for an S gate and a X basis measurement operation.

22. The method of claim 20 or claim 21, wherein determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that transforms boundary' types of the logical qubit from XZXZ to XXZZ.

23. The method of claim 22, wherein the logical qubit with XXZZ boundary type stabilizes an observable running along an XX portion of the XXZZ boundary and the determined configuration of surface code stabilizers converts the observable into a Y observable.

24. The method of any one of claims 20 to 23, wherein determining the configuration of surface code stabilizers for implementing the target quantum computing operation comprises determining a configuration of surface code stabilizers that: transforms a Y observable of a logical qubit that comprises a plurality of physical qubits into a product of X basis surface code stabilizers whilst measuring the surface code stabilizers.

25. The method of any one of claims 20 to 24, wherein the quantum circuit comprises a quantum circuit that, when implemented by a quantum computer, performs operations according to the method of any one of claims 1 to 13.

26. The method of any one of claims 15 to 25, wherein the spacetime surface code defects comprise X-type defects, Y-type defects, H-type defects, and I-type defects.

27. The method of any one of claims 15 to 26, further comprising implementing, by a quantum computer, the quantum circuit to perform the target quantum computing operation.

28. A system comprising: a data processing apparatus; and a non-transitory computer readable storage medium in data communication with the data processing apparatus and storing instructions executable by the data processing apparatus and upon such execution cause the data processing apparatus to perform operations according to the method of any one of claims 15 to 27.

29. A computer-readable storage medium comprising instructions stored thereon that are executable by a processing device and upon such execution cause the processing device to perform operations according to the method of any one of claims 15 to 27.