EP4619824A2

EP4619824A2 - Optical proximity correction device and method of performing optical proximity correction

Info

Publication number: EP4619824A2
Application number: EP23895339.2A
Authority: EP
Inventors: Erik R. Hosler; Nicholas V. Licausi
Original assignee: Psiquantum Corp
Current assignee: Psiquantum Corp
Priority date: 2022-11-22
Filing date: 2023-11-20
Publication date: 2025-09-24
Also published as: WO2024112680A3; AU2023385602A1; WO2024112680A2

Abstract

An optical proximity correction (OPC) device may include a decomposition data generator that generates structural decomposition data from incoming design data, a mapping data generator that generates mapping data from the structure decomposition data, and a predictive correction unit that performs interleaved lithography-aware OPC based on the mapping data and correction adjustment data.

Description

OPTICAL PROXIMITY CORRECTION DEVICE AND METHOD OF PERFORMING OPTICAL PROXIMITY CORRECTION

FIELD

[0001] The present invention relates to an optical proximity correction device, and a method of performing optical proximity correction.

BACKGROUND

[0002] Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. In particular, OPC may be used in photomask design to account for resulting placement errors (e.g., from diffraction) in transferring an original design into an etched image on a semiconductor wafer.

SUMMARY

[0003] According to an aspect of the present disclosure, an optical proximity correction (OPC) device may include a decomposition data generator that generates structural decomposition data from incoming design data, a mapping data generator that generates mapping data from the structure decomposition data, and a predictive correction unit that performs interleaved lithography-aware OPC based on the mapping data and correction adjustment data.

[0004] According to another aspect of the present disclosure, a method of performing optical proximity correction (OPC) may include generating structural decomposition data from incoming design data, generating mapping data from the structure decomposition data, and performing interleaved lithography-aware OPC based on the mapping data and correction adjustment data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the Figures.

[0006] FIG. 1 is a schematic view of a lithographic scanner including an OPC device according to one or more embodiments. [0007] FIG. 2 is a schematic view of lithographic scanner including an OPC device according to one or more embodiments.

[0008] FIG. 3 is a detailed schematic view of the correction adjustment unit according to one or more embodiments.

[0009] FIG. 4 is a flow chart illustrating a lithographic scanning method according to one or more embodiments.

[0010] FIG. 5 is a plan view (e.g., top-down view) of a patterning layout according to one or more embodiments.

[0011] FIG. 6A is a plan view of example patterning layouts (e.g., exposure mask layouts) for interleaved, overlapping features, according to one or more embodiments.

[0012] FIG. 6B is a plan view of a sub-resolution assist feature (SRAF) layout (e.g., example SRAF placements) for interleaved, overlapping features, according to one or more embodiments. [0013] FIG. 7 is a plan view of example patterning layouts (e.g., exposure mask layouts) for interleaved, overlapping features, according to one or more embodiments.

[0014] FIG. 8 is a flow chart for a co-optimized interleaved source-mask optimization (SMO) method for the pattern layout, according to one or more embodiments.

DETAILED DESCRIPTION

[0015] As discussed above, the embodiments of the present disclosure are directed an optical proximity correction device and method of performing optical proximity correction, the various aspects of which are discussed herein in detail. The drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a “layer” refers to a continuous portion of at least one material including a region having a thickness. A layer may consist of a single material portion having a homogeneous composition, or may include multiple material portions having different compositions.

[0016] As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0 x 10⁵ S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10’⁵ S/cm. As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0 x IO^-5 S/cm to 1.0 x 10⁵ S/cm. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

[0017] For multiple patterning, either a litho-etch-litho-etch process, a litho-freeze-litho-etch process or a self-aligned process may typically be used. The standard data flow may isolate OPC/mask processing to a single reticle level, even with a freeze step. This may lead to critical dimension (CD) errors, such as bulges or gaps.

[0018] Since a second exposure may occur after development of the first exposure photoresist, there may be minimal impact to the first exposed features. When reticle fields are stitched together, a single reticle field may still be utilized. Therefore, it may be possible to pass OPC corrections from opposite ends of the frame where stitching occurs via custom coding. However, this may be non-standard and may be bypassed due to the size of features stitched. Stitching may typically occur either in the back end of line (BEOL) or for repeating features that can be separated, at the stitching interface (e.g., charge-coupled device (CCD) arrays).

[0019] In complex photonics circuits with high demands on CD uniformity, line edge roughness (LER) and shape fidelity, it may be desirable to specifically tune the lithography exposure (illumination, dose, focus, OPC) for each critical component on a single layer. However, the standard methods (e.g., litho-etch-litho-etch) may require a hardmask which can prevent overlapping of the structures.

[0020] In some example embodiments, as part of an interleaved L_nE exposure technique, without any freeze step, it may be desirable for the OPC of independent reticles to be “aware” of previous/concurrent exposures (e.g., for the OPC of one reticle to take into account an exposure using another reticle, where the reticles may not be near each other in the mask, and where the image features are in different reticles on the final design). One or more embodiments of the present disclosure may include an optical proximity correction (OPC) device and method of performing OPC. In at least one embodiment, the OPC device may perform interleaved lithography-aware OPC.

[0021] In one or more embodiments, the OPC device may perform interleaved lithography- aware OPC for adjacent but not overlapping features in a given design (e.g., stitched together PICs), and/or for interleaved and overlapping features. The OPC device may also perform individual exposure tuning based on critical structure content, and may perform OPC decomposition of critical components into features for stitching reticles together for rule-based updates or model-updates in a interleaved OPC approach.

[0022] FIG. 1 is a schematic view of a lithographic scanner 100 according to one or more embodiments. As illustrated in FIG. 1, the lithographic scanner 100 may include an exposure unit 110. The exposure unit 110 may include, for example, a radiation source such as an ultraviolet emitting lamp (e.g., LED or mercury lamp) or laser, or an X-ray emitter for X-ray lithography, for exposing a structure 10, such as a semiconductor device or a photonic structure (e.g., silicon photonic die) in a lithographic process. The structure 10 typically includes a substrate, such as a wafer (e.g., silicon wafer, etc.).

[0023] The lithographic scanner 100 may also include a metrology tool 130 coupled to the exposure unit 110. The metrology tool 130 may generate wafer correction data that may typically be used to make adjustments to the exposure unit 110. The generated wafer correction data may include, for example, interwafer correction data and/or intrawafer correction data.

[0024] The lithographic scanner 100 may also include a correction adjustment unit 140 coupled to the metrology tool 130. The correction adjustment unit 140 may map optical performance to the generated wafer correction data. Based on the mapping, the correction adjustment unit 140 may generate correction adjustment data.

[0025] The lithographic scanner 100 may also include an OPC device 120 for making optical proximity corrections. The optical proximity corrections may include, for example, corrections regarding design (e.g., design of the photomask). The optical proximity corrections may also include corrections to an operation of the exposure unit 110, such as dose corrections and focus corrections. [0026] As shown in FIG. 2, the OPC device 120 may include, for example, a decomposition data generator 120a that generates structural decomposition data from incoming design data.

The decomposition data generator 120a may decompose a patterning layout into structures that would benefit from a specific illumination source, such as a dipole source (e.g., two sources illuminate mask) for lines, and a quadrupole source (e.g., four sources illuminate mask) for curves and circles. In this way, pattern fidelity can be independently tuned via different sources and overall device performance is improved. The OPC device 120 may also include a mapping data generator 120b that generates mapping data from the structural decomposition data. The OPC device 120 may also include a predictive correction unit 120c that performs interleaved lithography-aware OPC based on the mapping data and based on the correction adjustment data from the correction adjustment unit 140. That is, the correction adjustment data from the correction adjustment unit 140 may be used to adjust the predictive correction unit 120c.

[0027] The correction adjustment data may include, for example, dose adjustment data for making an in-die dose correction and/or focus adjustment data for making in-die focus correction. The correction adjustment data may also include, for example, critical dimension correction data for the structure 10. In at least one embodiment, the predictive correction unit 120c may apply the in-die dose correction based on a type of the structure 10 (e.g., source, waveguide, block, etc. for a photonic die) is being formed. In at least one embodiment, the predictive correction unit 120c may apply the in-die focus correction based on the type of the structure 10.

[0028] In at least one embodiment, the OPC device 120 may be implemented by a computer, server, etc. including a processing device such as a central processing unit (CPU), microprocessor, etc., and a memory device (e.g., random access memory (RAM), read-only memory (ROM), etc.). The memory device may store data and programs including instructions for performing operations in the OPC device 120. The processing device may access the data and programs in the memory device, and execute the program instructions in order to perform various methods including a method of performing optical proximity correction.

[0029] As illustrated in FIG. 2, the predictive correction unit 120c may receive incoming design data, structural decomposition data and structural component requirement mapping data as input. The exposure unit 110 may perform, for example, wafer exposure at level "x". The metrology tool 130 may perform metrology of the level "x" (e.g., critical dimension, line edge roughness, etc.) and generate correlation data. The correction adjustment unit 140 may generate correction adjustment data based on the wafer correction data from the metrology tool 130, and feed the correction adjustment data forward to the predictive correction unit 120c for adjusting the predictive correction unit 120c. The correction adjustment unit 140 may also generate feedback data that is combined with the correlation data from the metrology tool 130, and fed back to the exposure unit 110.

[0030] FIG. 3 is a detailed schematic view of the correction adjustment unit 140 according to one or more embodiments. As illustrated in FIG. 3, the correction adjustment unit 140 may include a scanning electron microscope-based (SEM-based) fast correction loop and optically- based slow correction loop. In particular, the correction adjustment unit 140 may include an optical testing section 141 that may map optical performance to the generated wafer correction data from the metrology tool 130. The optical testing section may also continually update the mapping of the optical performance to the generated wafer correction data. The optical testing section 141 may perform, for example, full processing and then optical testing on the results of the full processing. In addition or alternatively, the optical testing section 141 may include a possible decorrelative data stream in which short loop processing is performed and then optical testing is performed on the results of the short loop processing.

[0031] The correction adjustment unit 140 may also include a combined data analysis and deconvolution section 142 that receives an output (e.g., optical testing output) from the optical testing section 141. The combined data analysis and deconvolution section 142 may perform data analysis and deconvolution on the output and generate the correction adjustment data to be fed forward to the predictive correction unit 120c. The combined data analysis and deconvolution section 142 may also generate feedback data to be fed back to the exposure unit 110.

[0032] In at least one embodiment, the correction adjustment data may include, for example, in-die correction data, across-wafer correction data, between-lot correction data and/or by-level correction data for improving optical performance utilizing dose and focus tuning. The correction adjustment data may further include optically aware, optical proximity correction (OPC) data and design correction data based on critical component design. The correction adjustment data may further include a diagnostic short loop data thread to disentangle integration versus patterning performance. [0033] In at least one embodiment, in the lithographic scanner 100, optical testing may be correlated (c.g., in the correction adjustment unit 140) to the traditional output of interwafer and/or intrawafer corrections to provide feedforward for critical dimension (CD) correction of critical optical components. Further, in-die dose/focus corrections may be applied based on the type of structure to be controlled (e.g., source vs. waveguide vs. block).

[0034] Further, the lithographic scanner 100 may provide an optically calibrated APC thread. The APC thread may be created to control CD, line edge roughness (LER), line width roughness (LWR) and/or CDU based on critical structure and in-die/wafer position. Optical performance may be mapped (e.g., in the correction adjustment unit 140) to inline CD/LER/LWR/CDU performance. Optical performance data may be deconvolved (e.g., in the combined data analysis and deconvolution section 142) by critical component and OPC/design corrections may be made prior to mask fabrication. Since critical structures (sources vs. delay lines) may typically be segregated on a photonic integrated circuit (e.g., photonic IC die or PIC die), localized dose/focus adjustments can be used to independently tune each.

[0035] The APC thread may be controlled, for example, via the optical measurements (master correction, slow loop). An inline scanning electron microscope (SEM) may be used as the fast correction loop based on SEM-optical matching. SEM-optical performance mapping may be continually updated. The SEM may be used to drive APC corrections based on critical component type, and maintain current, in-fab process control flow. A short loop (e.g., in the optical testing section 141) may contain only the critical optical structures and may be invoked to deconvolve the complexity of the APC thread.

[0036] Thus, the lithographic scanner 100 may, therefore, provide a process control loop with SEM-based fast correction loop and optically-based slow correction loop. The lithographic scanner 100 may further provide a within-die, across-wafer, between-lot, and by-level correction for improving optical performance utilizing dose and focus tuning. The lithographic scanner 100 may further provide optically aware, OPC and design correction based on critical component design. The lithographic scanner 100 may also provide a diagnostic short loop data thread to disentangle integration versus patterning performance.

[0037] The predictive correction unit 120c may include, for example, an interleaving unit for performing lithography-aware OPC. This may allow for improved stitched pattern fidelity and targeting. The predictive correction unit 120c may further include a transfer unit for passing layout knowledge from one OPC sub-level to another. This may allow for flare correction on the final common level exposure for adjacent features, and may allow for flare correction on the final common level exposure for overlapping features.

[0038] The predictive correction unit 120c may further include an optimization unit for performing OPC optimization across lithography sub-levels. This may allow for co-optimization of the design, dose and focus based on potentially different illumination sources. The predictive correction unit 120c may further include an OPC tuning unit for tuning the OPC between sublevels. Tuning the OPC between sub-levels may be critical to meet design targets. The predictive correction unit 120c may also include a positioning unit for uniquely positioning the silicon photonic structure 10 for interleaving lithography and consequently aware-OPC, because interacting components do not necessarily need to be in contact.

[0039] FIG. 4 is a flow chart illustrating a method of performing optical proximity correction (OPC) according to one or more embodiments. The method may be performed, for example, using the lithographic scanner 100 described above. In particular, the method may be performed by the OPC device 120 as part of the lithographic scanner 100. Step 410 includes generating structural decomposition data from incoming design data. Step 420 includes generating mapping data from the structural decomposition data. Step 430 includes performing interleaved lithography-aware OPC based on the mapping data and correction adjustment data.

[0040] FIG. 5 is a plan view (e.g., top-down view) of a patterning layout 500 according to one or more embodiments. For interleaved lithography, the predictive correction unit 120c may perform OPC by taking into account the varied sources, optimized for each exposure level, as well as the interaction between structures exposed on different exposure levels. Co-optimization of the source, OPC and assist placement for adjoined or overlapping structures may be critical. In at least one embodiment, the predictive correction unit 120c may perform an iterative OPC optimization process.

[0041] As illustrated in FIG. 5, the patterning layout 500 may include a first mask 510 (e.g., first prime mask) including a first pattern 501. The first mask 510 (e.g., first exposure field) may include various control structures for effecting optical proximity correction. The control structures may include first alignment structures 510a, first overlay structures 510b and first flare structures 510c. [0042] The patterning layout 500 may also include a second mask 520 (e.g., second prime mask) including a second pattern 502. The second mask 520 (e.g., second exposure field) may also include various control structures for effecting optical proximity correction. The control structures may include second alignment structures 520a, second overlay structures 520b and second flare structures 520c. The patterning layout 500 may also include a boundary 530 between the first mask 510 and the second mask 520. In the boundary 530, the first mask 510 may overlap the second mask 520, and vice versa.

[0043] FIG. 6A is a plan view of example patterning layouts 600 (e.g., exposure mask layouts) for interleaved, overlapping features, according to one or more embodiments. As illustrated in FIG. 6A, in a first patterning layout 601, a first structure 600a and a second structure 600b may be located close to but outside a boundary 630 between a first mask 610 and a second mask 620. In a second patterning layout 602, the first structure 600a and the second structure 600b may be located within the boundary 630 between the first mask 610 and the second mask 620.

[0044] In a third patterning layout 603, the first structure 600a and the second structure 600b may again be located within the boundary 630 between the first mask 610 and the second mask 620. In addition, in the third patterning layout 603, the second mask 620 is entirely within the first mask 610, so that the boundary 630 is coextensive with the second mask 620.

[0045] FIG. 6B is a plan view of a sub-resolution assist feature (SRAF) layout 650 (e.g., example SRAF placements) for interleaved, overlapping features, according to one or more embodiments. As illustrated in FIG. 6B, the SRAF layout 650 may include, for example, a first SRAF arrangement 651 including first SRAFs 650a and second SRAFs 650b. The SRAF layout 650 may also second SRAF arrangement 652, third SRAF arrangement 653 or fourth SRAF arrangement 654, each of which may include a different arrangement of the first SRAFs 650a and the second SRAFs 650b.

[0046] As illustrated in FIGS. 6A and 6B, in the case of interleaved, non-overlapping features, interacting features (e.g., first structure 600a and second structure 600b) may be placed inside or outside the boundary 630 between the first mask 610 and the second mask 620. Depending on the proximity of the features, the OPC device 120 may perform OPC independently for each exposure masking level. Further, the OPC device 120 may iteratively solve OPC for features that are close enough in proximity for flare to be a concern. Sub- resolution assist features (SRAFs) such as first SRAFs 650a and second SRAFs 650b may be interlaced or alternating, based on the requirements of each critical component near or in the boundary 630.

[0047] FIG. 7 is a plan view of example patterning layouts 700 (e.g., exposure mask layouts) for interleaved, overlapping features, according to one or more embodiments. In particular, the example patterning layouts 700 may include those with SRAFs and without SRAFs. As illustrated in FIG. 7, in a first patterning layout 701, the first structure 700a and the second structure 700b may be partially located within the boundary 730 between the first mask 710 and the second mask 720. In addition, the second structure 700b may overlap the first structure 700a in the boundary 730.

[0048] In a second patterning layout 702, the first structure 700a and the second structure 700b may again be located within the boundary 730 between the first mask 710 and the second mask 720, and again, the second structure 700b may overlap the first structure 700a in the boundary 730. In addition, first SRAFs 700c may be located adjacent the first structure 700a, and second SRAFs 700d may be located adjacent the second structure 700b.

[0049] In a third patterning layout 703, the second mask 720 is entirely within the first mask 710, so that the boundary 730 is coextensive with the second mask 720. The first structure 700a and the second structure 700b may be located entirely within the boundary 730, and the second structure 700b may overlap the first structure 700a.

[0050] In a fourth patterning layout 704, the second mask 720 is again entirely within the first mask 710, so that the boundary 730 is coextensive with the second mask 720. The first structure 700a and the second structure 700b may be located entirely within the boundary 730, and the second structure 700b may overlap the first structure 700a. In addition, first SRAFs 700c may be located adjacent the first structure 700a, and second SRAFs 700d may be located adjacent the second structure 700b.

[0051] In the case of interleaved, overlapping features, the OPC device 120 may be aware of both the content of lithography sub-levels as well as the targeted lithography conditions (source, dose, focus, OPC-type). Further, the OPC device 120 may iteratively optimize the shape and assist features around the overlapping content.

[0052] FIG. 8 is a flow chart for a co-optimized interleaved source-mask optimization (SMO) method for the pattern layout 500 shown in FIG. 5, according to one or more embodiments. In some example embodiments, source-mask optimization involves solving an optimization function (c.g., integral transfer function) to determine connections between optical intensity between the mask plane of the mask and the intensity at the image plane. An example optimization function can include the following equation, where I is the intensity and H is the transfer matrix:

[0053] As noted above, the patterning layout 500 may include a first mask 510 including a first pattern 501, and a second mask 520 including a second pattern 502, and boundary 530.

[0054] As illustrated in FIG. 8, in the co-optimized interleaved source-mask optimization (SMO) method, Step 810 may include optimizing the first mask 510 in prime area 1 of mask (e.g., mask 510) for the source that is preferred for prime area 1 (based on design feature(s) to be included in the prime area 1, such as feature 501). The illumination source implemented for the first prime area may be preset via rules or generated by a model of OPC software, such as off- the-shelf layout software with OPC tools, OPC plugins or via custom coding that performs SMO (e.g., solving the equation above) for a given design and mask.

[0055] Step 820 may include optimizing the second mask 520 in prime area 2 of mask 2 (e.g. mask 520) for a second source for that prime area 2 (c.g., based on design fcaturc(s) to be included in prime area 2, such as feature 502). In some example embodiments, the sources implemented in step 810 and 820 may be the same type of source (e.g., both prime area 1 and prime area 2 are illuminated with an annular source); while in other example embodiments, the sources used in step 810 and step 820 are different sources based on the different features to be included in the different prime areas (e.g., at step 810, an annular source is implemented and at step 820, a dipole source is implemented).

[0056] Step 830 may include examining a solution in the boundary 530 with a mixed source (e.g., dipole source, quadrupole source, other mixes or geometric configurations of sources) that best corresponds or mimics in the boundary area the collective illumination of the first source in step 810 and the second source in step 820.

[0057] Step 840 may include optimizing the boundary 530 with a mixed source. For example, a dipole source is implemented at step 840 to generate an output results (e.g., simulation data, etched data) where the dipole source more accurately represents the light for the boundary area (e.g., mimics light in the boundary area, taking into account the different sources of the two stitched together prime areas).

[0058] In some example embodiments, step 850 may include an iteration step in which the method returns to Step 810, while potentially adjusting a first source and a second source as a feedback so that in a later iteration the mixed source of step 840 can better approximate the updated sources and masks from respective areas and masks.

[0059] In some example embodiments, the co-optimized interleaved SMO approach of FIG. 8 includes an iterative flow between a custom illumination source and mask layout/design (including SRAFs). In these example embodiments, the OPC device 120 may perform SMO independently for the different exposure sub-levels, but perform a combined optimization (mixed source) in the boundary area 530. In particular, the OPC device may optimize main and assist features in the boundary 530 using the mixed source. The iteration step (Step 850) may invoke a co-optimized source for the lithography sub-levels if boundary structures can be improved without degrading the prime area features to within a specified control limit, in accordance with some example embodiments.

[0060] In some example embodiments, the above method is performed for each of a variety of test structures (FIG. 5) as a model simulations after which rules or models-updates are performed such that at fabrication time, the improved OPC device 120 outputs an accurate OPC interleaved mask for accurate fabrication of multiple stitched together reticles on a wafer. In some example embodiments, as part of the method of FIG. 8, etching is performed such that the feedback loop for which mixed source will be implemented in a given iteration is based on final etched results from a previous iteration (e.g., after-etch image (AEI) correction data based on metrology data of the physical etched output, FIG. 1).

[0061] In one or more embodiments, the OPC device 120 may perform OPC decomposition of photonic critical features. For photonic structures, it may be beneficial to decompose the layout into similar- shaped designs (e.g., lines, curves, resonators, blocks) to allow for independent tuning of those structures via source and mask shapes. For example, a ring resonator/curved structures (e.g., the first pattern 501) may be optimally patterned by a quadrupole light source or annular light source. Furthermore, a delay line/linear waveguide may prefer a dipole source. Lastly, a ring resonator may be optimized using a conventional source. More complex structures may require customized illuminations. Depending on designs, the OPC device 120 may decompose components into areas of the final device design or simply placed on separate exposure levels with a common reticle size.

[0062] The system may provide several advantages over other OPC devices. In particular, the OPC device 120 may provide improved pattern fidelity for adjacent, overlapping and stitched features by iterative OPC modeling and source optimization, where the masks features and designs . One or more embodiments may be especially helpful in case where interleaving lithography is adopted for critical levels. In that case, the OPC device 120 (e.g., data flow) may be important to maximize benefits, particularly in the adjacent/overlapping/interacting areas.

The OPC device 120 may also provide a patterning process having advantages for silicon photonics die used in augmented or virtual reality devices.

[0063] The following are examples:

[0064] Example 1 : An optical proximity correction (OPC) device, comprising: a decomposition data generator that generates structural decomposition data from incoming design data, the incoming design data comprising layout data and initial mask data; a mapping data generator that generates mapping data from the structure decomposition data; and a predictive correction unit that performs, using one or more hardware processors, interleaved lithography- aware OPC based on the mapping data and correction adjustment data, the predictive correction unit to output updated mask data based on the interleaved lithography-aware OPC.

[0065] Example 2: The OPC device as example 1 describes, wherein the initial mask data comprises a lithography mask to fabricate an initial semiconductor device according to the layout data, and wherein the updated mask data comprises OPC features to fabricate an improved semiconductor device that more closely resembles the layout data of the incoming design data. [0066] Example 3: The OPC device as either of examples 1 or 2 describe, wherein the interleaved lithography-aware OPC comprises at least one of an interleaved OPC for adjacent but not overlapping features, an interleaved OPC for overlapping features, individual exposure tuning based on critical structure content, or OPC decomposition of critical components.

[0067] Example 4: The OPC device as any of examples 1-3 describe, wherein the interleaved lithography-aware OPC implements a model based on a plurality of test structures and a plurality of sources.

[0068] Example 5: The OPC device as any of examples 1-4 describe, wherein the model is based on implementing the plurality of sources at different exposure levels according to the incoming design data, and further based on interactions between structures of the different exposure levels.

[0069] Example 6: The OPC device as any of examples 1-5 describe, wherein the incoming design data comprises mask data, and wherein the mask data comprises a plurality of areas including at least two stitched-together areas having features to optically couple the at least two stitched-together areas.

[0070] Example 7: The OPC device as any of examples 1-6 describe, wherein the interleaved lithography-aware OPC comprises an iterative interleaved lithography-aware OPC.

[0071] Example 8: The OPC device as any of examples 1-7 describe, wherein the decomposition data generator decomposes the incoming design data into test structures that function well with one or more specific sources to generate OPC data.

[0072] Example 9: The OPC device as any of examples 1-8 describe, wherein the test structures comprises lines that are stored as functioning well with dipole sources.

[0073] Example 10: The OPC device as any of examples 1-9 describe, wherein the test structures comprises bent shapes, the bent shapes comprises at least one or more of curves or circles; and wherein the bent shapes are stored as functioning well with quadrupole sources.

[0074] Example 11: The OPC device as any of examples 1-10 describe, wherein the predictive correction unit passes layout knowledge from one OPC sub-level to another.

[0075] Example 12: The OPC device as any of examples 1-11 describe, wherein the predictive correction unit performs OPC across lithography sub-levels, allowing for cooptimization of design, dose and focus based on potentially different illumination sources.

[0076] Example 13: The OPC device as any of examples 1-12 describe, wherein the predictive correction unit performs tuning of OPC between sub-levels for meeting design targets. [0077] Example 14: The OPC device as any of examples 1-13 describe, wherein the predictive correction unit uniquely positions a photonic structure for the interleaved lithography- aware OPC.

[0078] Example 15: The OPC device as any of examples 1-14 describe, wherein the interleaved lithography-aware OPC comprises OPC for interleaved, non-overlapping features, in which interacting features are placed inside or outside a boundary between exposure fields.

[0079] Example 16: The OPC device as any of examples 1-15 describe, wherein the interleaved lithography-aware OPC comprises an OPC scheme for interleaved, overlapping features, in which OPC scheme is aware of both a content of lithography sub-levels and targeted lithography conditions, and the OPC scheme iteratively optimizes shape and assist features around overlapping content.

[0080] Example 17: The OPC device as any of examples 1-16 describe, wherein the interleaved lithography-aware OPC comprises co-optimized interleaved source-mask optimization (SMO) that includes an iterative flow between a custom illumination source and mask layout and design, and performs SMO independently for different exposure sub-levels, and performs a combined optimization in a boundary area.

[0081] Example 18: The OPC device as any of examples 1-17 describe, wherein the correction adjustment data is based on a metrology data from metrology of one or more semiconductor devices formed using the updated mask data.

[0082] Example 19: A method of performing optical proximity correction (OPC), comprising: generating structural decomposition data from incoming design data, the incoming design data comprising layout data and initial mask data; generating mapping data from the structure decomposition data; and generating OPC data, the generating OPC data comprising performing interleaved lithography-aware OPC based on the mapping data and correction adjustment data, the OPC data comprising updated mask data.

[0083] Example 20: The method as example 19 describes, wherein the initial mask data comprises a lithography mask to fabricate an initial semiconductor device according to the layout data, and wherein the updated mask data comprises OPC features to fabricate an improved semiconductor device that more closely resembles the layout data of the incoming design data. [0084] Example 21: The method as either of examples 19 or 20 describe, wherein the interleaved lithography-aware OPC comprises at least one of an interleaved OPC for adjacent but not overlapping features, an interleaved OPC for overlapping features, individual exposure tuning based on critical structure content, or OPC decomposition of critical components.

[0085] Example 22: The method as any of examples 19-21 describe, wherein the interleaved lithography-aware OPC implements a model based on a plurality of test structures and a plurality of sources.

[0086] Example 23: The method as any of examples 19-22 describe, wherein the model is based on implementing the plurality of sources at different exposure levels according to the incoming design data, and further based on interactions between structures of the different exposure levels.

[0087] Example 24: The method as any of examples 19-23 describe, wherein the incoming design data comprises mask data, and wherein the mask data comprises a plurality of areas including at least two stitched-together areas having features to optically couple the at least two stitched-together areas.

[0088] Example 25: The method as any of examples 19-24 describe, wherein the interleaved lithography-aware OPC comprises an iterative interleaved lithography-aware OPC

[0089] Example 26: The method as any of examples 19-25 describe, further comprising decomposing the incoming design data into test structures that function well with one or more specific sources to generate OPC data.

[0090] Example 27: The method as any of examples 19-26 describe, wherein the test structures comprises lines that are stored as functioning well with dipole sources.

[0091] Example 28: The method as any of examples 19-27 describe, wherein the test structures comprises bent shapes, the bent shapes comprises at least one or more of curves or circles; and wherein the bent shapes are stored as functioning well with quadrupole sources. [0092] Example 29: The method as any of examples 19-28 describe, further comprising storing layout data from one OPC sub-level for use in processing another OPC sub-level.

[0093] Example 30: The method as any of examples 19-29 describe, further performing OPC across lithography sub-levels while allowing for co -optimization of design, dose, and focus based on potentially different illumination sources.

[0094] Example 31: The method as any of examples 19-30 describe, further comprising tuning of OPC between sub-levels for meeting design targets.

[0095] Example 32: The method as any of examples 19-31 describe, further comprising uniquely positioning a photonic structure for the interleaved lithography-aware OPC.

[0096] Example 33: The method as any of examples 19-32 describe, wherein the interleaved lithography-aware OPC comprises OPC for interleaved, non-overlapping features, in which interacting features are placed inside or outside a boundary between exposure fields.

[0097] Example 34: The method as any of examples 19-33 describe, wherein the interleaved lithography-aware OPC comprises OPC for interleaved, overlapping features, in which OPC is aware of both a content of lithography sub-levels and targeted lithography conditions. [0098] Example 35: The method as any of examples 19-34 describe, wherein the interleaved lithography-aware OPC comprises co-optimizcd interleaved source-mask optimization (SMO) that includes an iterative flow between a custom illumination source and mask layout and design, and performs SMO independently for different exposure sub-levels, and performs a combined optimization in a boundary area.

[0099] Example 36: The method as any of examples 19-35 describe, wherein the correction adjustment data is based on a metrology data from metrology of one or more semiconductor devices formed using the updated mask data.

[00100] Example 37: A method comprising: receiving, using one or more processors, incoming design data, the incoming design data comprising a plurality of PIC areas for fabrication on a wafer, the plurality of photonic integrated circuits comprising a first PIC area and a second PIC area, the first PIC area having features for optically coupling the first PIC area to the second PIC area on the wafer; generating, using the or more processors, first PIC optical proximity correction (OPC) data based on a first optical source; generating, using the one or more processors, second PIC OPC data based on a second optical source; generating, using the one or more processors, boundary OPC data for an overlapping area of the first PIC area and second PIC area, the overlapping area comprising a first feature in the first PIC area and a second feature in the second PIC area, the first feature and the second feature configured to couple light between the first feature and the second feature in the wafer, the boundary OPC data generated based on a mixed optical source; and storing the first PIC OPC data, the second PIC OPC data, and the boundary OPC data as OPC mask data for fabrication of the wafer.

[00101] Example 38: The method as example 37 describes, wherein generating the boundary OPC data comprises: generating initial boundary OPC data for an initial mixed optical source; determining adjustment data to correct errors due to one or more of the first optical source, the second optical source, or the initial mixed optical source; and selecting the mixed optical source based on the adjustment data for use in generating the boundary OPC data.

[00102] Example 39: The method as either of examples 37 or 38 describe, wherein each of the first optical source, the second optical source, and the mixed optical source comprise one or more of: an annular source, a dipole source, a quadrupole source.

[00103] Example 40: The method as any of examples 37-39 describe, further comprising: fabricating a wafer by implementing optical lithography based on the OPC data. [00104] The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. An optical proximity correction (OPC) device, comprising: a decomposition data generator that generates structural decomposition data from incoming design data, the incoming design data comprising layout data and initial mask data; a mapping data generator that generates mapping data from the structure decomposition data; and a predictive correction unit that performs, using one or more hardware processors, interleaved lithography-aware OPC based on the mapping data and correction adjustment data, the predictive correction unit to output updated mask data based on the interleaved lithography- aware OPC.

2. The OPC device of claim 1, wherein the initial mask data comprises a lithography mask to fabricate an initial semiconductor device according to the layout data, and wherein the updated mask data comprises OPC features to fabricate an improved semiconductor device that more closely resembles the layout data of the incoming design data.

3. The OPC device of claim 1, wherein the interleaved lithography-aware OPC comprises at least one of an interleaved OPC for adjacent but not overlapping features, an interleaved OPC for overlapping features, individual exposure tuning based on critical structure content, or OPC decomposition of critical components.

4. The OPC device of claim 1, wherein the interleaved lithography-aware OPC implements a model based on a plurality of test structures and a plurality of sources.

5. The OPC device of claim 4, wherein the model is based on implementing the plurality of sources at different exposure levels according to the incoming design data, and further based on interactions between structures of the different exposure levels.

6. The OPC device of claim 4, wherein the incoming design data comprises mask data, and wherein the mask data comprises a plurality of areas including at least two stitchcd-togcthcr areas having features to optically couple the at least two stitched-together areas.

7. The OPC device of claim 1, wherein the interleaved lithography-aware OPC comprises an iterative interleaved lithography-aware OPC.

8. The OPC device of claim 1, wherein the decomposition data generator decomposes the incoming design data into test structures that function well with one or more specific sources to generate OPC data.

9. The OPC device of claim 8, wherein the test structures comprises lines that are stored as functioning well with dipole sources.

10. The OPC device of claim 9, wherein the test structures comprises bent shapes, the bent shapes comprises at least one or more of curves or circles; and wherein the bent shapes are stored as functioning well with quadrupole sources.

11. The OPC device of claim 1, wherein the predictive correction unit passes layout knowledge from one OPC sub-level to another.

12. The OPC device of claim 1, wherein the predictive correction unit performs OPC across lithography sub-levels, allowing for co-optimization of design, dose and focus based on potentially different illumination sources.

13. The OPC device of claim 1, wherein the predictive correction unit performs tuning of OPC between sub-levels for meeting design targets.

14. The OPC device of claim 1, wherein the predictive correction unit uniquely positions a photonic structure for the interleaved lithography -aw are OPC.

15. The OPC device of claim 1 , wherein the interleaved lithography-aware OPC comprises OPC for interleaved, non-overlapping features, in which interacting features arc placed inside or outside a boundary between exposure fields.

16. The OPC device of claim 1, wherein the interleaved lithography-aware OPC comprises an OPC scheme for interleaved, overlapping features, in which OPC scheme is aware of both a content of lithography sub-levels and targeted lithography conditions, and the OPC scheme iteratively optimizes shape and assist features around overlapping content.

17. The OPC device of claim 1, wherein the interleaved lithography-aware OPC comprises co-optimized interleaved source-mask optimization (SMO) that includes an iterative flow between a custom illumination source and mask layout and design, and performs SMO independently for different exposure sub-levels, and performs a combined optimization in a boundary area.

18. The OPC device of claim 1, wherein the correction adjustment data is based on a metrology data from metrology of one or more semiconductor devices formed using the updated mask data.

19. A method of performing optical proximity correction (OPC), comprising: generating structural decomposition data from incoming design data, the incoming design data comprising layout data and initial mask data; generating mapping data from the structure decomposition data; and generating OPC data, the generating OPC data comprising performing interleaved lithography-aware OPC based on the mapping data and correction adjustment data, the OPC data comprising updated mask data.

20. The method of claim 19, wherein the initial mask data comprises a lithography mask to fabricate an initial semiconductor device according to the layout data, and wherein the updated mask data comprises OPC features to fabricate an improved semiconductor device that more closely resembles the layout data of the incoming design data.

21 . The method of claim 19, wherein the interleaved lithography-aware OPC comprises at least one of an interleaved OPC for adjacent but not overlapping features, an interleaved OPC for overlapping features, individual exposure tuning based on critical structure content, or OPC decomposition of critical components.

22. The method of claim 19, wherein the interleaved lithography-aware OPC implements a model based on a plurality of test structures and a plurality of sources.

23. The method of claim 22, wherein the model is based on implementing the plurality of sources at different exposure levels according to the incoming design data, and further based on interactions between structures of the different exposure levels.

24. The method of claim 22, wherein the incoming design data comprises mask data, and wherein the mask data comprises a plurality of areas including at least two stitched-together areas having features to optically couple the at least two stitched-together areas.

25. The method of claim 19, wherein the interleaved lithography-aware OPC comprises an iterative interleaved lithography-aware OPC.

26. The method of claim 19, further comprising decomposing the incoming design data into test structures that function well with one or more specific sources to generate OPC data.

27. The method of claim 26, wherein the test structures comprises lines that are stored as functioning well with dipole sources.

28. The method of claim 27, wherein the test structures comprises bent shapes, the bent shapes comprises at least one or more of curves or circles; and wherein the bent shapes are stored as functioning well with quadrupole sources.

29. The method of claim 19, further comprising storing layout data from one OPC sub-level for use in processing another OPC sub-level.

30. The method of claim 19, further performing OPC across lithography sub-lcvcls while allowing for co-optimization of design, dose, and focus based on potentially different illumination sources.

31. The method of claim 19, further comprising tuning of OPC between sub-levels for meeting design targets.

32. The method of claim 19, further comprising uniquely positioning a photonic structure for the interleaved lithography-aware OPC.

33. The method of claim 19, wherein the interleaved lithography-aware OPC comprises OPC for interleaved, non-overlapping features, in which interacting features are placed inside or outside a boundary between exposure fields.

34. The method of claim 19, wherein the interleaved lithography-aware OPC comprises OPC for interleaved, overlapping features, in which OPC is aware of both a content of lithography sub-levels and targeted lithography conditions.

35. The method of claim 19, wherein the interleaved lithography-aware OPC comprises cooptimized interleaved source-mask optimization (SMO) that includes an iterative flow between a custom illumination source and mask layout and design, and performs SMO independently for different exposure sub-levels, and performs a combined optimization in a boundary area.

36. The method of claim 19, wherein the correction adjustment data is based on a metrology data from metrology of one or more semiconductor devices formed using the updated mask data.

37. A method comprising: receiving, using one or more processors, incoming design data, the incoming design data comprising a plurality of PIC areas for fabrication on a wafer, the plurality of photonic integrated circuits comprising a first PIC area and a second PIC area, the first PIC area having features for optically coupling the first PIC area to the second PIC area on the wafer; generating, using the or more processors, first PIC optical proximity correction (OPC) data based on a first optical source; generating, using the one or more processors, second PIC OPC data based on a second optical source; generating, using the one or more processors, boundary OPC data for an overlapping area of the first PIC area and second PIC area, the overlapping area comprising a first feature in the first PIC area and a second feature in the second PIC area, the first feature and the second feature configured to couple light between the first feature and the second feature in the wafer, the boundary OPC data generated based on a mixed optical source; and storing the first PIC OPC data, the second PIC OPC data, and the boundary OPC data as OPC mask data for fabrication of the wafer.

38. The method of claim 37, wherein generating the boundary OPC data comprises: generating initial boundary OPC data for an initial mixed optical source; determining adjustment data to correct errors due to one or more of the first optical source, the second optical source, or the initial mixed optical source; and selecting the mixed optical source based on the adjustment data for use in generating the boundary OPC data.

39. The method of claim 37, wherein each of the first optical source, the second optical source, and the mixed optical source comprise one or more of: an annular source, a dipole source, a quadrupole source.

40. The method of claim 37, further comprising: fabricating a wafer by implementing optical lithography based on the OPC data.