EP4581535A1

EP4581535A1 - Device for connecting qubits for a semiconductor spin qubit quantum computer

Info

Publication number: EP4581535A1
Application number: EP23708480.1A
Authority: EP
Inventors: Matthias KÜNNE; Lars Reiner SCHREIBER; Jörg Hendrik BLUHM; Alexander WILLMES; Harsh Bhardwaj; Eugen Kammerloher; Ran XUE
Original assignee: Forschungszentrum Juelich GmbH; Rheinisch Westlische Technische Hochschuke RWTH
Current assignee: Forschungszentrum Juelich GmbH; Rheinisch Westlische Technische Hochschuke RWTH
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2025-07-09
Also published as: CN120712573A; WO2024179674A1

Abstract

A T-junction for a quantum processor comprises a plurality of gate electrodes arranged on a semiconductor heterostructure. The plurality of gate electrodes comprises first conveyor gates arranged at at least one path and second conveyor gates arranged at a branch. The branch and the at least one path are arranged substantially perpendicular to one another and meet at a junction. The first conveyor gates and second conveyor gates are configured to be supplied with at least one voltage V. The first conveyor gates and second conveyor gates are configured to move at least one qubit, arranged in the semiconductor heterostructure, along the at least one path and/or along the branch, and to divert the at least one qubit from the at least one path into the branch or from the branch into the at least one path.

Description

Title: DEVICE FOR CONNECTING QUBITS FOR A SEMICONDUCTOR SPIN QUBIT QUANTUM COMPUTER

Field of the disclosure

[0001] The field of the present disclosure relates to the operation of quantum processors.

Background of the disclosure

[0002] Quantum processor architectures have to allow for scalability in order to achieve numbers of logical qubits sufficiently high to implement quantum computer chips that enable NISQ (noisy intermediate-scale quantum) era quantum computing or even universal quantum computing. In the case of spin qubit-based quantum computing, the qubits are arranged in a two-dimensional plane. A downside of this two-dimensional architecture is the so-called fan-out problem, i.e. , spatial requirements of the wiring for the control lines of the quantum processor between the quantum processor and a classical control circuit. These spatial requirements scale faster with the number of qubits than the size of the hitherto proposed spin qubitbased quantum processor architectures.

[0003] Recently, an architecture for spin-qubits based on direct electron shuttling in Si/SiGe semiconductor heterostructures was proposed. The architecture includes shuttling paths along which qubits are transportable across, in principle, arbitrary distances such as of up to about 50 pm. The shuttling paths allow to arrange components of the quantum processor, such as loading zones, readout zones, and manipulation zones, at a distance from each other, which lowers crosstalk. Providing shuttling paths also enables operations modes that require comparatively small operation frequencies and reduced local magnetic field gradients.

[0004] In these shuttling path-based architectures, high-fidelity shuttling is important for reliable computations. Such high-fidelity shuttling is compromised by, e.g., charge defects or low valley splitting along the shuttling path. The low valley splitting may lead to leakage out of the computational basis, e.g., two spin states, that is used for computation. [0005] There is a need for identifying spots in the quantum processor, e.g., in the shuttling path or other components of the quantum processor, where the reliability of qubit handling is reduced, which ultimately impacts on the performance of the quantum processor.

Summary of the disclosure

[0006] A T-junction for a quantum processor comprises a plurality of gate electrodes arranged on a semiconductor heterostructure, wherein the plurality of gate electrodes comprises first conveyor gates arranged at at least one path and second conveyor gates arranged at branch. The branch and the at least one path are arranged substantially perpendicular to one another and meet at a junction; the first conveyor gates and the second conveyor gates are configured to be supplied with at least one voltage V, to move at least one qubit, arranged in the semiconductor heterostructure, along the at least one path and/or along the branch, and to divert the at least one qubit from the at least one path into the branch or from the branch into the at least one path.

[0007] The first conveyor gates may be further configured to generate at least one travelling potential well to move the at least one qubit along the at least one path or to generate a stationary potential well at the junction; and/or the second conveyor gates may further be configured to generate the traveling potential well to move the at least one qubit along the branch or to generate a confinement potential at the junction.

[0008] The first conveyor gates may comprise electrode subsets electrically disconnected from each other, the first conveyor gates of any one of the electrode subsets being electrically connected with each other.

[0009] The T-junction may further comprise screening gates arranged along the at least one path, and/or screening gates arranged along the branch.

[0010] The screening gates arranged along the branch may be connected at the junction with the screening gate, which is arranged along the at least one path interrupted between the screening gates arranged along the branch.

[0011] At least one of the conveyor gates may overlap at the junction with the screening gate arranged along the at least one path. [0012] The conveyor gates may be arranged on a planarized dielectric or insulating layer.

[0013] The T-junction may further comprise a top gate arranged above the first conveyor gates and/or the second conveyor gates.

[0014] The T-junction may further comprise a back gate arranged on the semiconductor heterostructure opposite the first conveyor gates and the conveyor gates.

[0015] A system comprises a T-junction according to the disclosure and an external magnet for providing an external magnetic field Bo.

[0016] A method of moving at least one qubit at a junction of at least one path and a branch in a semiconductor heterostructure comprising a plurality of gate electrodes arranged thereon, is disclosed. The at least one path and the branch are perpendicular to one another and meet at the junction. The method comprises the steps of providing an external magnetic field Bo; and of providing at the junction a confinement to move the at least one qubit along the at least one path, or providing at the junction a quasi-stationary potential well to adiabatically transfer the at least one qubit being moved along the branch into the quasi-stationary potential well.

[0017] The providing of the confinement may comprise providing a stationary voltage to at least ones of second conveyor gates.

[0018] The providing of the quasi-stationary potential well may comprise providing a stationary voltage to at least ones of conveyor gates.

[0019]The method may further comprise moving the at least one qubit from the junction along the at least one path or the branch.

Brief description of the drawings

[0006] FIG. 1 shows a top view of a quantum processor.

[0020] FIG. 2 shown a top view of a unit cell of the quantum processor shown in FIG. 2.

[0021] FIG. 3A shows a top view of an aspect of a shuttling lane.

[0022] FIG. 3B shows a longitudinal cross-section of a further aspect of the shuttling lane. [0023] FIG. 3C shows a pair of path-defining gates arranged at a path for a qubit.

[0024] FIG. 3D shows a longitudinal cross-section of a further aspect of the shuttlinglane.

[0025] FIG. 4A shows a top view of an aspect of a shuttling lane with a segmented path-defining gate electrode.

[0026] FIG. 4B shows a longitudinal cross-section of a further aspect of the shuttling lane.

[0027] FIG. 4C shows a pair of segmented path-defining gates arranged at a path for one or more qubits.

[0028] FIG. 5 shows an example of a grayscale-coded valley-splitting landscape of a shuttling lane as well as possible trajectories for a qubit along the shuttling lane which circumvent a series of fidelity-reducing loci with reduced valley splitting.

[0029] FIG. 6A shows a top view of a T-junction.

[0030] FIG. 6B shows a top view of the path-defining gates of the T-junction shown in FIG. 6A.

[0031] FIG. 7 shows a simulation of the orbital splitting during movement past a junction during straight moving (left panel) and during diversion at the junction.

[0032] FIG. 8 shows a simulation of potential well at the T-junction during diverting at least one qubit the junction.

[0033] FIG. 9 shows another aspect of a segmented path-defining gate.

[0034] FIG. 10A shows a top view of a T-junction with a segmented path-defining gate.

[0035] FIG. 10B shows a top view of the segmented path-defining gates of the T- junction shown in FIG. 6A.

Detailed description

[0036] The present disclosure relates to a method of operating a quantum processor as well as to a method of manufacturing a quantum processor.

[0037] The quantum processor may operate based on spin qubits. A spin qubit is a two-level quantum system of a spin degree of freedom. An example of a spin qubit is the two-level quantum system of the spin of an electron confined in a quantum dot. Another example is a hole spin qubit. Furthermore, a group of electrons, for example two or three electrons, may be used to implement a spin qubit, such as an S-T0 singlet-triplet system of two electrons in a quantum double-dot. [0038] The method of the present disclosure is applicable to any type of electrically controllable spin qubit implemented in a semiconductor heterostructure 12. Using an electron-based spin qubit involves bringing the electron spin into a known state. To this end, the state of the electron is initialized. In one aspect, a selected qubit is associated with the same electron throughout the performing of a quantum algorithm. In another aspect, a qubit implemented by a first electron may be initialized and, subsequently to an operation on the qubit, the qubit may be implemented by means of a second electron. In a further aspect, there are situations in which it is impossible to tell whether the qubit is implemented by the first electron or by the second electron, without compromising the performing of quantum algorithms. Likewise, the method of the present disclosure may be applied on any type of hole spin qubit.

[0039] Using semiconductor materials to form the semiconductor heterostructure 12, for implementing the quantum processor facilitates manufacturing due to easy handling and low costs of the materials, such as in the case of silicon. There are established technologies for using silicon in computing hardware. A two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) is confinable within the semiconductor heterostructure 12, formed from the semiconductor materials, in a quantum well 69 (see below and FIG. 3D). The quantum well 69 is exemplarily shown in FIG. 3D. However, the quantum well 69 will also be present in the semiconductor heterostructure 12 shown in FIGS. 3A, 3B, 4A, 4B. The 2DEG or the 2DHG may further be confined based on electrical potentials. The electric potentials may be static electric potentials or non-static electric potentials. The electrical potentials may form at least one quantum dot, in which at least one electron or hole of the 2DEG or 2DHG is trappable or confinable. The spin of the trapped (confined) at least one electron or hole is usable to implement spin qubits. Moving the electrical potentials results in moving the at least one quantum dot. The moving of the at least one quantum dot enables moving the trapped (confined) at least one electron/hole as well as the qubits associated with the trapped (confined) at least one electrons/holes. Altering a strength of the electrical potentials alters the degree of confinement of the trapped (confined) at least one electron or hole.

[0040] The quantum processor may comprise a plurality of unit cells. A unit cell of the plurality of unit cells comprises components that perform at least one action or operation on one or more qubits located in the unit cell. The at least one action on the one or more qubits includes: loading of the one or more qubits into the unit cell; unloading of the one or more qubits from the unit cell; moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell (i.e. , to another one of the unit cell of the quantum processor); manipulating a quantum state of the one or more qubits; and readout of the quantum state of the one or more qubits. The manipulating of the one or more qubits may comprise manipulating a single qubit or manipulating two qubits. The manipulating of the single qubit comprises rotating the spins of the single qubit, e.g., for driving transitions between a plurality of spin states. The plurality of spin states may comprise, e.g., a spin-up state and a spin-down state. The manipulating of two qubits may serve to implement a CPHASE gate, a CNOT gate, and/or a SWAP gate. The manipulating of the two qubits may further serve to implement a SQRT(SWAP) gate. Implementing a CNOT gate and one or more single-qubit gates, such as rotations or phase shifts, are sufficient to implement a quantum computer. The CNOT gate may be realized as a CPHASE gate in spin- qubit-based quantum computers.

[0041] In one aspect, several actions performed on the one or more qubits by the components of the unit cell may be performed one after another as a sequence of actions. For example, two actions may be performed one after another. In another aspect, the several actions performed on the one or more qubits by the components of the unit cell may be performed in parallel. For example, the two actions may be performed in parallel.

[0042] In one aspect, the several actions on the one or more qubits may be performed within a single one of the plurality of the unit cells or across several ones of the plurality of unit cells.

[0043] In one aspect, the several actions may be performed as part of determining a gate fidelity (see below for more details). For example, the determining of the gate fidelity may comprise performing the sequence of actions on the one or more qubits.

[0044] In another aspect, the several actions may be performed as part of performing an algorithm. For example, the performing of the algorithm may comprise performing the sequence of actions on the one or more qubits.

[0045] The components are arranged within the unit cell. Some of the components are connected with each other. The components and the connections of the components thus form a layout or structure of the unit cell. Ones of the plurality of unit cells may have substantially the same structure, in which the same components are arranged and connected with each other in substantially the same way. Other ones of the plurality of unit cells may have differing structures, in which the components and/or the connections of the components differ.

[0046] An aspect of the quantum processor is disclosed in international patent application no. WO 2021/052541 A1 , the disclosure of which is incorporated herein by reference in its entirety. In this aspect, shown in FIGS. 1 and 2, the quantum processor 10 comprises the semiconductor heterostructure 12. The semiconductor heterostructure 12 comprises several layers of differing material composition. The semiconductor heterostructure 12 may be a Si/SiGe or GaAs/AIGaAs heterostructure, however, the use of other materials in which a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) can be formed, such as Si-MOS, is possible. The semiconductor heterostructure may be undoped and/or strained. The semiconductor heterostructure 12 may serve as a substrate of the quantum processor 10. The semiconductor heterostructure 12 may comprise the 2DEG. The 2DEG or the 2DHG may be arranged or located in the quantum well 69 (see FIG. 3D). The one or more qubits may be arranged in the quantum well 69. The one or more qubits may be arranged in the at least one quantum dot formed in the quantum well 69. The one or more qubits may be generated from the 2DEG.

[0047] In one aspect, the semiconductor heterostructure 12 may further comprise a silicon cap 64, on which a dielectric or insulating layer 66 is arranged (see FIG. 3D). The gate electrodes 50a, 50b may be arranged on top of the dielectric or insulating layer 66.

[0048] In a further aspect, the semiconductor heterostructure 12 may further comprise a layer of strained silicon 63 (see FIG. 3D). In yet a further aspect, the semiconductor heterostructure 12 may further comprise a layer of silicon dioxide 62 (see FIG. 3D).

[0049] In the aspect of the quantum processor 10 shown in FIGS. 1 and 2, the components 16, 18, 20, 22, 24 are provided on at least one surface 14 of the semiconductor heterostructure 12. As can be seen in FIG. 1 , the shown aspect of the quantum processor 10 comprises one or more of each of the components 16, 18, 20, 22, 24. In another aspect, the quantum processor 10 may comprise one or more of only some of the component 16, 18, 20, 22, 24.

[0050] The quantum processor 10 shown in FIGS. 1 and 2 is a substantially two- dimensional device, as defined by the at least one surface 14. A third dimension of the quantum processor 10 is defined by a thickness of the semiconductor structure 12 and a thickness of the components 16, 18, 20, 22, 24.

[0051] The plurality of unit cells of the quantum processor 10 comprises several of the unit cell 26 (shown in FIG. 2). In the aspect shown in FIG.2, the unit cell 26 comprises the components 16, 18, 20, 22, 24. In another aspect of the disclosure, the unit cell 26 comprises merely some of the components 16, 18, 20, 22, 24. In yet a further aspect, the unit cell 26 may comprise more than one of at least one of the components 16, 18, 20, 22, 24.

[0052] The components 16, 18, 20, 22, 24 comprise a plurality of gate electrodes 50 (see FIGS. 3A and 3B) arranged on at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged to define within the quantum well 69 of the associated one of the components 16, 18, 20, 22, 24 at least one path 45 (see FIGS. 1 , 2, 3A, 3C, 3D, 4A,, 4C,) along which the one or more qubits may be moved (shuttled).

[0053] In FIGS. 1 and 2, the at least one path 45 is shown to substantially be directed in two directions on the surface 14 that are substantially perpendicular to one another, resulting in structure of a plurality of paths 45 that is grid-like. The plurality of paths 45 connect the components 16, 18, 20, 22, 24.

[0054] The plurality of gate electrodes 50 may further be arranged to move (shuttle) the one or more qubits along the at least one path 45. The movement (shuttling) may occur in either one of the two directions (back and forth) along the at least one path 45. The plurality of gate electrodes 50 may further be arranged for performing the at least one action on the one or more qubits, performed by the components 16, 18, 20, 22, 24.

[0055] The plurality of gate electrodes 50 may be provided with voltages. The plurality of gate electrodes 50 may be made of metal. The plurality of gate electrodes 50 may be superconducting. The voltages may serve one or more purposes, such as defining the at least one path 45, moving (shuttling) the one or more qubits, and/or implementing the at least one action on the one or more qubits. The voltages may comprise DC (direct current) voltages and AC (alternating current) voltages. The voltages may comprise one or more stationary voltages and one or more non- stationary voltages. The voltages may be applied by means of DC lines, AC lines, and/or bias tees. [0056] One or more of the components 16, 18, 20, 22, 24 may further comprise a magnet, such as a micromagnet. The micromagnet may be placed on top of the component 16, 18, 20, 22, 24. The micromagnet provides a magnetic field. The magnetic field may have a zero gradient or a non-zero gradient.

[0057] An external magnetic field splits the plurality of spin states (e.g., spin-up and spin-down) used as a computational basis for the one or more qubits into separated energy levels (Zeeman splitting). The external magnetic field may be provided by an external magnet, e.g., an electromagnet (not shown), that is placed in the vicinity of the quantum processor 10. The quantum processor 10 may at least partially be placed in the external magnetic field provided by the external magnet.

[0058] The one or more components 16, 18, 20, 22, 24 may further comprise means for providing electromagnetic radiation, e.g., microwaves, for manipulating the quantum state of the one or more qubits, e.g., rotating the spins of the one or more qubits between the plurality of spin states. The spins of the one or more qubits may thus be switched between, e.g., the spin-up and the spin-down state, or vice versa, by means of the electromagnetic radiation based on electron spin resonance (ESR). The frequency of the electromagnetic radiation may equal the energy difference of the separated energy levels. ESR provides a further way of manipulating the quantum state of the one or more qubits. The microwaves may have a frequency in the range of several hundred MHz to several hundred GHz. In one aspect, the frequency lies in the range of 9-10 GHz, but is not limited thereto.

[0059] Providing an inhomogeneous magnetic field, e.g., by means of the at least one magnet 35, i.e. , having a non-zero gradient, enables driving transitions between the plurality of spin states by means of displacements of the one or more qubits in the inhomogeneous magnetic field based on, e.g., an AC electric field. The AC electric field may be provided by means of one or more of the gate electrodes 50b This effect is called electric dipole spin resonance (EDSR). The displacement makes the one or more qubits oscillate between the plurality of spin states (e.g., the spin states forming the computational basis such as the spin-up state and the spin-down state). For example, the one or more qubits may oscillate such that the spin-up state can be switched to the spin-down state, and vice versa.

[0060] Alternatively, the EDSR may be achieved in one of the semiconductor heterostructure 12 in which spin-orbit coupling is present. The semiconductor heterostructure 12 may be made from semiconductor materials that provide the spinorbit coupling.

[0061] The plurality of gate electrodes 50 may be provided as one or more of gate electrode assemblies 50a, 50b, 50c, 50d. The plurality of gate electrodes 50 may comprise one or more laterally positioning gate electrodes (also termed "screening gates”) 50a (see FIG. 3A) arranged to define and/or modify a lateral position of a trajectory 80 (see FIG. 5) in the quantum well 69 and/or at the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The trajectory 80 may be a trajectory of one or more potential wells (further described below), in which the one or more qubits are arrangeable. The one or more potential wells may thus be one or more travelling potential wells. The trajectory 80 of the one or more potential wells may thus correspond to a trajectory of the one or more qubits arranged at the least one path 45. Thus, the lateral position of the trajectory 80 may correspond to a lateral position of the one or more potential wells and/or of the one or more qubits. Arranging the one or more qubits at the least one path 45 is to be understood to mean that the one or more qubits are arranged within the quantum well 69.

[0062] The plurality of gate electrodes 50 may further comprise one or more shuttling gate electrodes (also termed “conveyor gates” or “finger gates”) 50b (see FIG. 3A) arranged to move (shuttle) the one or more qubits along the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell.

[0063] The plurality of gate electrodes 50 may further comprise at least one pitchenhancing gate electrode (also termed “top gate”) 50d arranged to enable enhancing a pitch or spacing of the conveyor gates 50b.

[0064] The plurality of gate electrodes 50 may further comprise at least one vertically positioning gate electrode (also termed “back gate”) 50c arranged to define and/or modify a vertical position of the trajectory 80 (see FIG. 3D) in the quantum well 69 and/or at the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The vertical position of the trajectory 80 may correspond to a vertical position of the one or more potential wells and/or of the one or more qubits.

[0065] The plurality of gate electrodes 50 may further comprise qubit-handling gate electrodes arranged for performing the at least one action on the one or more qubits. The qubit-handling electrodes include plunger gates and barrier gates. The plunger gates may be used to control the occupation of a quantum dot, to control a detuning in a double quantum dot, and/or to perform an exchange of two qubits. The barrier gates may be used to form a potential double-well and/or to control the tunnel barrier in a double quantum dot.

[0066] The plurality of gate electrodes 50 may be arranged on the at least one surface 14 of the semiconductor heterostructure 12. The plurality of gate electrodes 50 may be arranged in layers that are separated by an insulating or dielectric layer 60 and the insulating or dielectric layers 66 (see FIG. 3B and 3D). In one aspect, the layers may be arranged in a direction substantially perpendicular to the direction of the at least one path 45.

[0067] One or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and/or the insulating or dielectric layer 67 may be planarized. A method of manufacturing the shuttling element 16 may comprise the step of planarizing one or more of the insulating or dielectric layer 60, the insulating and dielectric layer 66, and/or the insulating or dielectric layer 67. The insulating or dielectric layer 60 may be planarized during manufacturing before arranging the conveyor gates 50b on the insulating or dielectric layer 60. The planarizing facilitates using processes such as electron ray epitaxy, Deep UV, and/or spacer lithography. The planarizing reduces the thickness of one or more of the dielectric or insulating layers 60, 66, 67. For instance, the insulating or dielectric layers 66 and/or 60 may be planarized before manufacturing of the conveyor gates 50b to reduce the thickness of the insulating or dielectric layer 66 and/or 60, respectively. After planarization, the insulating or dielectric layers 66 and/or 60 are tightly placed on the semiconductor heterostructure 12. Planarizing the insulating or dielectric layers 66 and/or 60 results in the thickness of the insulating or dielectric layers 66 and/or 60 being reduced between the at least one path 45 and the conveyor gates 50b. In one aspect, the thickness of the insulating or dielectric layer 60 is required to cover a top surface and sides of the screening gates 50a.

[0068] The component 16 serves to move (shuttle) the one or more quantum dots in the semiconductor heterostructure 12 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The component 16 is also termed “shuttling lane”. Aspects of the shuttling lane 16 is disclosed in international patent application no. WO 2021/052531 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0069] The component 18 provides a junction at which the one or more quantum dots may be diverted into at least one branch 45’ (at least one second one of the at least one path 45) that branches off of the at least one path 45 for moving (shuttling) the one or more qubits within the unit cell or beyond the unit cell. The component 18 is also termed “T-junction” . The at least one path 45 and the at least one branch 45’ of the T-junction 18 are arranged substantially perpendicular to one another. In one aspect, the at least one path 45 and the at least one branch 45’ of the T-junction 18 may substantially form a T-shape. Aspects of the T-junction 16 is disclosed in international patent application no. WO 2021/052539 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0070] The component 20 is provided for manipulating qubits in quantum dots. The component 20 is also termed “manipulation zone”. The manipulation zone 20 enables manipulating one or more current spin state of the one or more qubits. Any one qubit has a current spin state. In one aspect, the plurality of spin states may comprise the current spin state. In another aspect, the current spin state may be a linear combination of the plurality of spin states. During the manipulating, the one or more current spin states may be changed. Aspects of the manipulation zone 20 are disclosed in WO 2021/052537 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0071] The component 22 serves to initialize the one or more spin states of the one or more qubits. When the one or more spin states have been initialized, any one of the one or more current spin states is equal to one of the plurality of spin states. After initialization, the one or more current spin states may remain unchanged during a relaxation time. The relaxation time describes transitions between the spin-up state and the spin-down state due to interactions with the environment, such as the lattice of the semiconductor heterostructure 12. The component 22 is also termed “initialization zone”. Aspects of the initialization zone 22 are disclosed in WO 2021/052538 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0072] The component 24 serves to read out the one or more current spin states of the one or more qubits. When the one or more spin states have been read out, any one of the one or more current spin states prior to readout is known. The component 24 is also termed “readout zone”. Aspects of the readout zone 24 are disclosed in WO 2021/052536 A1 , the disclosure of which is incorporated herein by reference in its entirety.

[0073] The quantum processor 10 is operated to perform algorithms, such as quantum algorithms. The performing of the algorithms includes performing the sequence of actions on the one or more qubits, as explained above. The at least one action is performed by the components 16, 18, 20, 22, 24 of the unit cells 26.

[0074] The operating of the quantum processor 10 involves controlling the at least one action performed by the components 16, 18, 20, 22, 24. In one aspect of the disclosure, the at least one action is controlled by applying the voltages to the plurality of gate electrodes 50. The voltages may be set and/or adjusted to increase a fidelity F of the at least one action or of the sequence of actions. The fidelity F is a measure of how reliably the at least one action or the sequence of actions results in the outcome that is expected based on the design of the quantum processor 10 and on the voltages applied to the plurality of gate electrodes 50. To determine the fidelity F, the at least one action or the sequence of actions is repeated; subsequently the proportion of the repetitions is determined in which the actual outcome equals the expected outcome. The actual outcome includes the one or more current spin states that have been read out at the readout zone 24 after the at least one action or the sequence of actions. The expected outcome includes the one or more current spin states that are, based on known fidelities of the components 16, 18, 20, 22, 24 and/or the relaxation time of the one or more qubits, expected to be read out at the readout zone 24 after the at least one action or the sequence of actions.

[0075] For example, the at least one action may comprise the moving (shuttling) of the one or more qubits along the at least one path 45 of the shuttling lane 16. In this case, the fidelity F is a shuttling fidelity. The shuttling fidelity is understood to be a probability that the one or more current spin states of the one or more qubits are preserved during shuttling. The shuttling fidelity may be determined, for example, by repeatedly performing the sequence of actions: initialization of the one or more qubits, moving (shuttling) of the one or more qubits, and readout of the one or more qubits; followed by determining whether the initialized spin state of the one or more qubits are equal to the one or more current spin states after shuttling and prior to readout; and finally calculating the proportion of the repetitions in which the one or more current spin states were unaltered.

[0076] Another example is diverting the one or more qubits during the moving of the one or more qubits. When the one or more qubits are in proximity of the T-junction 18, the moving of the one or more qubits may include diverting the one or more qubits at the junction 28. The diverting means changing a direction along which the one or more qubits are moved. The T-junction 18 may be associated with a straightshuttling fidelity Fss. During straight shuttling, the one or more qubits do not change the direction along which the one or more qubits are moved (see description of FIG. 7 below). The straight shuttling fidelity similar to the above-described shuttling fidelity. However, the straight shuttling includes moving the one or more qubits past the junction 28. Furthermore, the T-junction 18 may be associated with a turning-off fidelity FTO. During turning off, the one or more qubits change the direction along which the one or more qubits are moved (see description of FIG. 7 below). The turning off includes changing the direction, along which the one or more qubits are moved, at the junction 28.

[0077] As explained above, determining the shuttling fidelity Fs involves an initialization step and a readout step. In a manner analogous to the determination of the manipulation fidelity FM, the shuttling fidelity Fs may be determined by determining a fidelity F that is a combination, i.e., a product, of an initialization fidelity, a shuttling fidelity, and a readout fidelity, and by subsequently dividing the fidelity F by the initialization fidelity and the readout fidelity. Similarly, the straight-shuttling fidelity Fss may be determined as a combined fidelity of the initialization fidelity, the straight-shuttling fidelity Fss, and the readout fidelity, and by subsequently dividing the combined fidelity F by the initialization fidelity and the readout fidelity. Similarly, the turning-off fidelity FTO may be determined as a combined fidelity of the initialization fidelity, the turning-off fidelity FTO, and the readout fidelity, and by subsequently dividing the combined fidelity F by the initialization fidelity and the readout fidelity.

[0078] The fidelity F may further be a gate fidelity. The gate fidelity F is a measure of how closely the outcome of a gate operation (i.e., the sequence of actions by means of the components 16, 18, 20, 22, 24 on the one or more qubits that are associated with a gate the quantum processor 10 is designed to implement) matches the expected, e.g., theoretical, outcome based on the design of the quantum processor 10 and the components 16, 18, 2022, 24. The gate fidelity F may be determined by randomized benchmarking.

[0079] As an example, increasing the shuttling fidelity F of a single qubit along a shuttling lane 16 will be described. FIG. 3A shows an aspect of the shuttling lane 16. The shuttling lane 16 comprises the screening gates 50a and the conveyor gates 50b arranged on the at least one surface 14 of the semiconductor heterostructure 12. In the aspect shown in FIG. 3A, the at least one surface 14 comprises a top surface 141 of the semiconductor heterostructure 12. In the aspect shown in FIG. 3B, the top surface 141 may be a top surface of the dielectric or insulating layer 66 (further described below).

[0080] The screening gates 50a are arranged to extend on either side of the at least one path 45 as screening gates 50a-1 and 50a-2 (see also FIG. 3C). In one aspect, as shown in FIGS. 3A-3C, the screening gates 50a-1 and 50a-2 may extend continuously along the at least one path 45. In another aspect, as shown in FIG. 6A- 6B, one of the screening gates 50a-1 and 50a-2 may be interrupted along the at least one path 45, e.g., where the branch 45’ branches off of the at least one path 45. The screening gates 50a-1 and 50a-2 may be spaced apart by approximately 200nm. The screening gates 50a may be made from metal and may be manufactured by embedding the metal in the semiconductor heterostructure 12 or by local implantation of the semiconductor heterostructure 12. The screening gates 50a may be embedded in the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60.

[0081] The dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60 may be structured in the lateral direction D3. In one aspect, the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60 may be provided as two separate portions (not shown), the separate portions enveloping the two screening gates 50a-1 and 50a-2, and the semiconductor heterostructure 12 extending into a space (not shown) between the two portions along the lateral (or transverse direction) D3. The semiconductor heterostructure 12 thus may form a ridge (not shown) in the space between the two portions of the dielectric or insulating layer 66 and/or in the dielectric or insulating layer 60. [0082] The conveyor gates 50b are arranged to extend transversely across the at least one path 45 (as shown in FIG. 3A). For example, the conveyor gates 50b may extend in a lateral direction D3. The conveyor gates or finger gates 50b may be arranged along the at least one path 45.

[0083] In the aspect shown in Fig. 3A, the conveyor gates 50b are provided in electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 (indicated in FIG. 3A by indices 1 , 2, 3, 4 above the conveyor gates of the corresponding electrode subset). The ones of the conveyor gates 50b that belong to one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 are marked with the same index at the top of FIGS. 3A, 3B, 4A, 4B, i.e. , the index 1 , 2, 3, or 4. The number of electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 shown in FIG. 3A is four. However, the number of the electrode subsets of the conveyor gates 50b may differ from this example and be, e.g., three or five. Any number of the electrode subsets of the conveyor gates 50b may be chosen, as long as the one or more travelling potential wells for moving (shuttling) the qubit or the one or more qubits (see below) can be generated.

[0084] The one or more travelling potential wells provide the confinement to trap an electron or hole, the strength of which is sufficiently strong to overcome disorder during moving (shuttling) in the quantum well 69, and the height of which provide barriers between adjacent potential well to suppress tunnelling. The trapped one or more electrons or holes adiabatically follow a sufficiently slow translation of the potential. The disorder is due to one or more of defects at boundaries of the layers of the semiconductor heterostructure 12, defects within the layers of the heterostructure 12, and/or defects within the dielectric layers 60, 66 and/or 67. The defects at the boundaries of the layers of the semiconductor heterostructure 12 include charge defects at interfaces between layers made from semiconductor materials and the dielectric or insulating layers 60 and/or 66. These charge defects are randomly distributed, e.g., at the interfaces. A density of the charge defects was set to 5E10/cm². Transitions to excited orbital states of the electron confined in the one or more travelling potential wells are caused by the disorder. In a moving frame of the one or more travelling potential wells, the disorder that quasi-statically fluctuates turns into dynamic noise that couples the orbital levels. Setting the shuttling speed is set to v = 10 m/s results in a reduced orbital excitation rate and a below-threshold phase error. [0085] In one aspect, the conveyor gates 50b may be arranged at the at least one path 45 in a manner, in which juxtaposed ones of the conveyor gates 50b extend differently far in the lateral (or transverse) direction D3 (as shown in FIG. 3A). In another aspect the conveyor gates 50b may extend equally far in the lateral (or transverse direction) D3.

[0086] The conveyor gates 50b may be arranged in a substantially equidistant manner with a substantially constant conveyor gate spacing between any two neighboring conveyor gates 50b. If a conveyor gate width, i.e. , an extension of the conveyor gates 50b in the longitudinal direction D3, of the conveyor gates 50b is substantially constant, a conveyor gate pitch, which is the sum of the conveyor gate spacing and the conveyor gate width, is substantially constant. In one aspect of the disclosure, the conveyor gate pitch may be approximately 80nm. The conveyor gates 50b may be arranged in a periodic manner. In one aspect, the conveyor gates 50b of any one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be arranged in a substantially equidistant manner from each other based on a spatial period of the periodically arranged conveyor gates. In another aspect, any two conveyor gates 50b belonging to any selected one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 have one conveyor gate of each of the other non-selected ones of the electrode subsets arranged therebetween. The periodical arrangement of the conveyor gates 50b facilitates industrial manufacturing of the shuttling path 16.

[0087] The conveyor gates 50b belonging to one of the four electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4, shown in FIG. 3A, are electrically connected to each other by an electrical connection (not shown). The element gates of any selected electrode subset from the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 are electrically disconnected from (or not electrically connected to) the element gates of the corresponding non-selected electrode subsets. The electrical connection may be provided by a metal strip arranged parallel to the screening gates 50a. The electrode subsets of the conveyor gates 50b with indices 1 and 3 may have the electrical connection on one side of the at least one path 45 (above the at least one path 45 as seen in FIG. 3A). The electrode subsets of the conveyor gates 50b with indices 2 and 4 may have the electrical connection on the other side of the at least one path 45 (below the at least one path 45 as seen in FIG. 3A). In one aspect of the disclosure, the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be arranged at different levels in the stacking direction D1 . For example, the metal strip connecting the conveyor gates of the electrode subset 50b-1 may be arranged on one side of the at least one path 45 at a higher level in the stacking direction D1 than the metal strip connecting the conveyor gates of the electrode subset 50b-3; and the metal strip connecting the conveyor gates of the electrode subset 50b-2 may be arranged on the other side of the at least one path 45 at a higher level in the stacking direction D1 than the metal strip connecting the conveyor gates of the electrode subset 50b-4. The electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may each be arranged at the level at which the corresponding metal strip is arranged. In another aspect, the metal strips may be all arranged on one side of the at least one path 45. In a further aspect, ones of the metal strips connecting the conveyor gates of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be electrically connected to the conveyor gates of the corresponding electrode subset by vias; and the conveyor gates of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 may be arranged at substantially one level in the stacking direction D1 .

[0088] The electrical connection of the element gates of any one of the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 enables providing a single voltage to the corresponding electrode subset. In other words, the number of voltage signals applied to the conveyor gates 50b is given by the number of electrode subsets chosen. As a result, the number voltage signals applied to screening gates 50a and the conveyor gates 50b is independent of a length of the shuttling element 16. In the example shown in FIGS. 3A and 3B, the number of electrode subsets is four. However, the number may be smaller or larger than four.

[0089] In a further aspect of the disclosure, the shuttling path 16 may comprise the top gate 50d (see FIG. 3D). The top gate 50d may extend in the lateral (transverse) direction D3. The top gate may extend in the shuttling direction (or longitudinal direction) D2. The top gate 50d may cover at least part of the first path 451 and/or the second path 452. In one aspect, at least in the lateral (transverse) direction D3, the top gate 50d completely covers the first path 451 and/or the second path 452.

[0090] In yet another aspect of the disclosure, the top gate electrode 50d may be arranged above of the conveyor gates 50b with a dielectric layer 67 arranged therebetween. The dielectric or insulating layer 67 may be partially arranged on the dielectric or insulating layer 60 (see FIGS 3D). Sections of the dielectric or insulating layer 67, which are arranged between the conveyor gates 50b, may be arranged on the dielectric or insulating layer 60. The dielectric or insulating layer 67 may be structured, e.g., segmented or profiled, in the shuttling direction D2 (see FIG. 3D). The dielectric or insulating layer 67 insulates the conveyor gates 50b that belong to different ones of the subsets 50b-1 , 50b-2, 50b-3, 50b-4 from each other. In one aspect of the disclosure, the dielectric or insulating layers 60 and 67 are a single dielectric or insulating layer 60, 67, in which the conveyor gates 50b are embedded.

[0091] The top gate 50d may be applied with a constant voltage. In a further aspect, the voltage applied to the top gate 50d may be modified on the one or more actions on the one or more qubits. For example, the voltage applied to the top gate 50d may be modified for shuttling the one or more qubits, for initializing the one or more qubits, for reading out of the one or more qubits, for manipulating the one or more qubits. In another example, the voltage applied to the top gate 50d may be modified according to sequence of actions on the one or more qubits, for instance as part of performing an algorithm. In yet a further aspect, the voltage applied to the top gate 50d may be modified periodically or non-periodically. The periodically modifying and/or the non- periodical ly modifying of the voltage applied to the top gate 50d may depend on the action performed on the one or more qubits. The periodically modifying of the voltage applied to the top gate 50d includes adding a square wave, a sawtooth wave, a superposition of sine waves. The periodically modifying of the voltage applied to the top gate 50d includes adding a stepwise increment to the voltage applied to the top gate 50d. The stepwise increment may depend on the one or more actions performed on the one or more qubits.

[0092] In one aspect, the top gate may have a planar top surface (not shown). In another aspect of the disclosure, the top gate 50d may be structured. An example of the structured top gate 50d is a segmented top gate 50d. Another example of the structured top gate 50d is a top gate with a surface profile (or profiled top gate), as shown in FIG. 3D. The structured top gate 50d may in one aspect be a segmented and profiled top gate. As shown in FIG. 3D, the top gate 50d may be structured, e.g., segmented and/or profiled, along the shuttling direction (or longitudinal direction) D2. Additionally or alternatively to the longitudinal structuring, the top gate 50d may be structured, e.g., segmented and/or profiled, along the lateral direction (or transvers direction) D3 [0093] The top gate 50d enables increasing the pitch between the conveyor gates 50b whilst maintaining the ability to shuttle the one or more qubits along the at least one path 45. Furthermore, the structured, e.g., segmented, top gate 50d shown in FIG. 3D enables tuning the Rabi frequency of the EDSR generated by the magnetic field of the at least one magnet 35 and the applied AC electric field.

[0094] In an aspect of the disclosure, the at least one surface 14 may further comprise a back surface 142. The at least one back gate 50c may be arranged on the back surface 142 of the semiconductor heterostructure 12 opposite the top surface 141 (see FIG. 3D). In the aspect shown in FIG. 3D, the back surface 142 is arranged at a bottom of the semiconductor heterostructure. The back surface 142 is arranged opposite the top surface 141 . The back surface 142 may be a surface of the layer of silicon dioxide 62 (describe above).

[0095] In the aspect shown in FIG. 3D, the at least one back gate 50c extends along a shuttling direction or longitudinal direction D2 of the shuttling lane 16. The at least one back gate 50c may further extend laterally (or transversely to the at least one path 45). For example, the at least one back gate 50c may further extend along the lateral (or transverse) direction D3 of the shuttling lane 16 transverse to the at least one path 45. The at least one back gate 50c may overlap or intersect the screening gates 50a in the lateral direction D3. The at least one back gate 50c may be arranged opposite the screening gates 50a. A voltage may be applied to the at least one back gate 50c to provide an electrical potential to modify the confinement at the quantum well 69.

[0096] In one aspect of the disclosure, the at least one back gate 50c may be structured, e.g., segmented and/or profiled, along the shuttling direction (or longitudinal direction) D2. In another aspect of the disclosure, the at least one back gate 50c may be structured, e.g., segmented and/or profiled, along the lateral direction D3, i.e. , transverse to the at least one path 45. In a yet a further aspect of the disclosure, the at least one back gate may be structured, e.g., segmented and/or profiled, along the shuttling direction (or longitudinal direction) D2 and the lateral direction D3.

[0097] As shown in FIG. 3B, the screening gates 50a and the conveyor gates 50b are separated by the insulating or dielectric layer 60. As explained above, the insulating or dielectric layer 60 may be planarized during manufacturing before arranging the conveyor gates 50b on the insulating or dielectric layer 60. The four electrode subsets of the conveyor gates 50b are separated by further insulating or dielectric layers or material (not shown). Furthermore, the dielectric or insulating layer 66 may be provided on the semiconductor heterostructure 12 (see FIG. 3B and 4B). The insulating or dielectric layer 66 separates the screening gates 50a and the semiconductor heterostructure 12. The screening gates 50a may be provided on the insulating layer 66.

[0098] The shuttling lane 16 is configured to move (shuttle) the one or more qubits along the at least one path 45. During the operation of the quantum processor 10, the shuttling lane 16 will be used to move the one or more qubits, e.g., from the initialization zone 22 to the manipulation zone 20 and thence to the readout zone 24. During this sequence of actions on the one or more qubits, the two screening gates (or “gates”) 50a-1 , 50a-2 (see FIGS. 3A and 3C) of the screening gates 50a of the shuttling lane 16 may in one aspect of the disclosure be provided with the same voltage of, e.g., 0V. The conveyor gates 50b are provided with AC voltages to provide the one or more travelling potential wells in which the one more qubits may be moved (shuttled). The AC voltages provided to the conveyor gates 50b may be sine-wave voltages. The AC voltages provided to the conveyor gates 50b may be phase-shifted between the electrode subsets of conveyor gates 50b-1 , 50b-2, 50b-3, 50b-4. The phase shifts of the conveyor gates 50b-2, 50b-3, 50b-4 with respect to the conveyor gates 50b-1 may be set to TT/2, IT, and 3TT/2, respectively. However, other settings for the phase shifts are conceivable. The phase shifts may deviate from being set to multiples of TT/2.

[0099] A lateral or transverse position in the lateral direction D3 of the trajectory 80 (see FIG. 5) of the one or more qubits along the at least one path 45 (extending along the x-axis of FIG. 5) is defined by the voltage applied to the two gates 50a-1 , 50a-2 (see, e.g., FIG. 3C) of the screening gates 50a. If the voltage applied to the gate 50a-1 and the voltage applied to the gate 50a-2 are substantially equal, one or more lateral positions of the generated one or more potential wells (i.e. , of one or more minima of the one or more potential wells) will be substantially in the middle of the two gates 50a-1 , 50a-2. If on the other hand the voltage applied to the gate 50a-1 and the voltage applied to the gate 50a-2 differ, the lateral position of the generated one or more potential wells (i.e., of the one or more minima of the one or more potential wells) will be off the middle of the two gates 50a-1 , 50a-2. The differing voltages on the gates 50a-1 , 50a-2 may be the result of changing either the voltage applied to the gate 50a-1 or the voltage applied to the gate 50a-2 by the addition of an adjustment voltage AV. In other words, the voltage applied to either the gate 50a- 1 or the gate 50a is changed to V+AV. For example, in the case of the heterostructure 12 being an undoped Si/SiGe heterostructure, if the voltage applied to the gate 50a-1 is decreased relative to the voltage applied to the other gate 50a-2, the one or more positions of the generated one or more potential wells (i.e. , of the one or more minima of the one or more potential wells) will be moved towards the other gate 50a-2. In case the heterostructure 12 is doped, such as when using GaAs/AIGaAs, increasing the voltage applied to the gate 50a-1 moves the one or more potential wells towards the other gate 50a-2. In this way, the trajectory 80 of the one or more qubits along the at least one path 45 may be shifted laterally (i.e., in the lateral or transverse direction D3 with respect to the at least one path 45).

[00100] In one aspect of the disclosure, the lateral shifting of the trajectory 80 of the of the one or more qubits may be transient (termed “local shift” in FIG. 5). The transient lateral shifting is the result of a time-varying adjustment voltage AV(t) being added to the voltage applied to the gate 50a-1 or the voltage applied to the gate 50a- 2. In other words, the trajectory 80 deviates only temporally from the lateral position that was initially set during a calibration (i.e., y-position of 0 nm in the example shown in FIG. 5). The temporal lateral shifting results for example in the trajectory 80-1 shown in FIG. 5.

[00101 ] In one aspect, the time-varying adjustment voltage AV(t) may be an AC voltage, such as a square pulse or a square wave. If several fidelity-reducing loci 70 are on average found to be distanced along the at least one path 45 (along the x-axis in FIG. 5) from one another by an average distance of 1000 nm (or 1 pm), and the shuttling speed at which the one or more qubits are shuttled along the at least one path 45 is 10 nm/ns (or 10 m/s), then on average the one or more qubits take a time of 100 ns to travel a distance equal to the average distance. The time-varying adjustment voltage AV(t) may thus last for the time of 100 ns. For instance, half the period of the square wave may be chosen to be equal to the time of 100ns. In other words the square wave may be chosen to have a frequency of 5 MHz.

[00102] In a further aspect of the disclosure, the adjustment voltage comprises a DC voltage that is added to the AC voltage applied to the conveyor gates 50b. The DC voltage may be applied to the conveyor gates 50b in addition to, or alternatively to the adjustment voltage AV(t) applied to the screening gates 50a. The further adjustment voltage may provide an alteration of the confinement provided by the conveyor gates 50b, e.g., enhance the confinement when the one or more qubits are in the vicinity of a fidelity-reducing locus 70 (see below).

[00103] The lateral shifting of the lateral position of the trajectory 80-1 enables circumventing a fidelity-reducing locus 70 in the shuttling lane 16. When the one or more qubits pass the fidelity-reducing locus 70 in the shuttling lane 16, the shuttling fidelity F may be reduced. The reduced shuttling fidelity F results in a less reliable shuttling of the one or more qubits along the shuttling lane 16. The fidelity-reducing locus 70 may be the result of, for example, a manufacturing impurity, a manufacturing defect, a charge defect, a crystal defect, and/or a locally reduced valley splitting. FIG. 5 shows a greyscale-coded valley-splitting landscape with valley-splitting energies between 0 peV and 300 peV (lighter shaded areas corresponds to higher valleysplitting energies; darker shaded areas correspond to lower valley-splitting energies). Fidelity-reducing loci 70 are located where the valley-splitting energy is between 0 peV and approximately 30-50 peV (shown by the paler shaded areas within dark shaded areas). In the example shown in FIG. 5, the trajectory 80-1 circumvents several fidelity-reducing loci 70 positioned at the y-position of 0 nm. The fidelityreducing loci 70-1 , 70-2, 70-3, ... , 70-10 are indicated by arrows and in some cases additionally by white dotted elliptical markings. In the example shown, the deviation Ay from the lateral position of the trajectory 80 initially set during a calibration (i.e. , the y-position of 0 nm set during a calibration step described below) peaks at approximately 20 nm in the lateral direction D3 along the positive y-axis in FIG. 5 and at approximately -20 nm in the lateral direction D3 along the negative y-axis in FIG. 5. In another case, the maximum values for the deviation Ay in the two lateral directions (along the positive and the negative y-axis, respectively) may differ from 20 nm and - 20nm, respectively.

[00104] The lateral shifting of the lateral position y of the trajectory 80-1 further enables continuous adjustment of the lateral position y of the trajectory 80-1 by means of a time-varying adjustment voltage AV(t). The time-varying adjustment voltage AV(t) results in a time-varying deviation Ay(t). The continuous adjustment may be required in the case of fluctuations in the voltages applied to the plurality of gate electrodes 50. [00105] In an aspect of the disclosure, similar to the lateral shifting described above, one or more vertical positions of the one or more potential wells may be shifted vertically, i.e. , in a stacking direction D1 (described below). Thereby, a vertical position of the trajectory 80-3 (a position along the stacking direction D1 ) may be altered. When the voltage applied to the at least one back gate 50c is changed, the confinement of the one or more potential wells is altered. The voltage applied to the at least one back gate 50c may be changed relative to the voltage applied to the screening gates 50a. Depending on the location of the at least one fidelity-reducing locus 70 (indicated by an asterisk in FIG. 3D), the vertical position of the trajectory 80 may be altered upwards or downwards in the stacking direction D1 . Thereby, the at least one fidelity-reducing locus 70 may be circumvented, and the reliability (i.e., the fidelity) of the shuttling lane 16 may be increased.

[00106] The determination of the shuttling fidelity F enables identifying positions of the fidelity-reducing loci 70 at the trajectory 80-1 or 80-3 (e.g., along and/or in the vicinity of the trajectory 80-1 or 80-3). During the identification of the positions of the fidelity-reducing loci 70, the applied voltages V are iteratively adjusted. Thereby, the lateral position of the trajectory 80-1 and/or the vertical position of the trajectory 80-3 is iteratively adjusted. The identification of the positions of the fidelity-reducing loci 70 results in a method of controlling the shuttling lane 16.

[00107] In one aspect of the disclosure, the lateral shifting and/or the vertical shifting of the trajectory 80 may be used at the manipulation zone 20 for moving the one or more qubits to a manipulation position that does not coincide with a fidelity reducing locus 70.

[00108] The T-junction 18 shown in FIG. 6A comprises the shuttling element 16 along the at least one path 45.

[00109] The T-junction 18 further comprises a second one 16’ of the shuttling element 16 (referred to as “second shuttling element”) along the branch 45’. As shown in FIG. 6A, the second shuttling element 16’ has two screening gates 50a’-1 and 50a’-2 extending along a second longitudinal (or shuttling) direction D2’. The second shuttling element 16’ further comprises shuttling gates (or finger gates) 50b’. The shuttling gates 50b’ extend in a second transverse (or lateral) direction D3’.

[00110] The at least one path 45 and the at least one branch 45’ are arranged substantially perpendicular to one another. The second longitudinal direction D2’ is perpendicular to the longitudinal direction D2. The second lateral direction D3’ is perpendicular to the lateral direction D3.

[00111] The shuttling element 16 (referred to as “first shuttling element”) and the second shuttling element 16’ join one another at a junction 28. The at least one path 45 and the branch 45’ meet one another at the junction 28. The two screening gates 50a’-1 and 50a’-2 end at the junction 28. The conveyor gates 50b’ end at the junction 28.

[00112] The screening gate 50a-1 of the first shuttling element 16 is interrupted along the longitudinal direction D2 at the junction 28. The screening gate 50a-1 is interrupted where the screening gates 50a’-1 and 50a’-2 of the second shuttling element 16’ end. The screening gate 50a-1 is interrupted where the first shuttling element 16 and the second shuttling element 16’ join one another at a junction 28. The interruption may extend along the lateral direction D3’ between at least the screening gates 50a’-1 and 50a’-2.

[00113] The screening gates 50a’-1 of the second shuttling element 16’ may be connected to one portion of screening gate 50a-1 of the first shuttling element 16. The screening gates 50a’-2 of the second shuttling element 16’ may be connected to another portion of screening gate 50a-1 of the first shuttling element 16. The screening gates 50a-1 and 50a'-1 (50a-1 and 50a'-2) may be joined electrically in such a way that the screening gates 50a-1 and 50a'-1 (50a-2 and 50a'-2) effectively form a single continuous screening gate. In another aspect, the screening gates 50a- 1 and 50a'-1 (50a-1 and 50a'-2) may be designed as a single continuous screening gate. In another aspect, the screening gates 50a-1 and 50a'-1 (50a-1 and 50a'-2) may be separated by a dielectric or insulating layeno

[00114] The conveyor gates 50b’ of the second shuttling element 16’ may be arranged at the junction 28 in the second longitudinal direction D2’ (or the lateral direction D3 of the first conveyor gate 16) such that at least one of the conveyor gates 50b’ touches or overlaps the screening gate 50a-1 of the first shuttling element 16 along the second longitudinal direction D2’ (or first lateral direction D3). Ones of the conveyor gates 50b’ may have curved or angled ends in the lateral direction D3’. The ones of the conveyor gates 50b’ may be arranged in proximity to the junction 28.

[00115] In the aspect shown in FIG. 6A, the conveyor gate of the electrode subset 50b’-1 of the second shuttling element 16’ closest to the junction 28 (the “last conveyor gate 50b’”) overlaps with the screening gate 50a-1. The last conveyor gate 50b’ extends in the lateral direction D3’ at least between the screening gates 50b’-1 and 50b’-2. The last conveyor gate 50b is arranged in proximity to a lower edge (as seen in FIG. 6A) of the screening gate 50a-1 along the lateral direction D3. By applying the last conveyor gate 50b’ with the voltage such that sufficient confinement is provided to the one or more qubits, this arrangement of the last conveyor gate 50b’ enables providing a screening potential. The voltage applied to provide the confinement may be stationary. The providing of the screening potential enables compensating for the interruption of the screening gate 50a-1 in the case of shuttling of the one or more qubits along the shuttling element 16 at the junction 28.

[00116] The conveyor gates 50b of the first shuttling element 16 are arranged at the junction 28 such that the conveyor gates 50b do not contact the conveyor gates 50b’ of the second shuttling element 16’. As shown in FIG. 6A, the conveyor gates 50b of the first shuttling element 50b at the junction are arranged below (as seen in FIG. 6A) the last conveyor gate 50b’ of the second conveyor element 16’ along the lateral direction D3 (or second longitudinal direction D2’).

[00117] When the one or more qubits are moved along the branch 45’ towards the junction 28, the conveyor gates 50b of first shuttling element 16 may be applied with the voltages to provide a quasi-stationary potential well, into the minimum of which the one or more qubits may be moved in an adiabatic manner by means of the travelling potential well moving along the second shuttling element 16’. The quasi- stationary potential well is generated by applying stationary ones of the voltages to the conveyor gates 50b of the first shuttling element 16. Once the one or more qubits have been moved to the minimum of quasi-stationary potential well provided by the conveyor gates 50b of the first shuttling element 16, the voltages applied to the conveyor gates 50b may be changed to AC voltages to move (shuttle) the one or more qubits along the at least one path 45 by means of the first shuttling element 16.

[00118] For reversing the afore-described movement, adjustments to the voltages applied conveyor gates 50b and 50b’ may be made. Thereby, differences in the confinement strengths between the first shuttling element 16 and the branch 16’ may be managed.

[00119] When the one or more qubits are located at the junction 28, the one or more qubits may be moved along the longitudinal direction D3 or along the second longitudinal direction D3’. The one or more qubits may be shuttled along the at least one path 45 without turning off into the branch 45’. The one or more qubits may be shuttled along the at least one path 45 and made to turn off along the branch 45’ (or vice versa). The T-junctions 18 thus enables moving the one or more qubits across the quantum chip 10.

[00120] FIG. 7 shows a simulation of the orbital splitting between a ground state and a first excited state of the one or more qubits during moving of the one or more qubits in a straight manner along the first shuttling element 16 (left panel). The simulation shows an orbital splitting above 1 meV for the entire simulated movement. For a shuttling speed of the order of 10 m/s, decoherence is preventable if the orbital splitting remains above roughly 1 meV, which is the case for the straight shuttling shown in the left panel of FIG. 7.

[00121] During the moving of the one or more qubits, in which the one or more qubits turn off from the second shuttling element 16’ into the first shuttling element 16 (see right panel of FIG. 7), the orbital splitting drops to below 1 meV. The orbital splitting may be improved by dynamically adjusting an offset between the conveyor gate 50b and 50b’to increase confinement at junction 28. Another option is to adjust the shuttling speed.

[00122] FIG. 8 shows the simulation of the quasi-stationary potential well located at the junction 28 and the travelling potential well moving along the second shuttling element 16’ (as described above). The results show that the one or more qubits trapped in the travelling potential well moving along the second shuttling element 16’ can be transferred adiabatically to the quasi-stationary potential well. Tunneling of the one or more qubits can be prevented.

[00123] The method according to the present disclosure of adjusting voltages applied to the plurality of gate electrodes 50 achieves a method of controlling the quantum processor 10.

[00124] Based on determining a density of the fidelity-reducing loci 70 in a portion of the quantum processor 10, such as along one of the shuttling lanes 16, at the T-junction 18, or in the entire quantum processor 10, the elevated density may point to a property of a manufacturing process of the quantum processor 10 or of the materials used in the manufacturing process. In this case, the quantum processor 10 may be manufactured such that the screening gates 50a-1 and 50a-2 (see FIGS. 3A and 3B) arranged thereon are segmented.

[00125] In one aspect, the screening gate 50a-1 and/or the screening gate 50a- 2 of the shuttling lane 16 may be segmented into electrically disconnected screening gate segments 50a-11 , 50a-12 and/or 50a-21 , 50a-22, respectively, as shown in FIGS. 4A and 4B.

[00126] In the aspect shown in FIGS. 4A and 4B, the dielectric or insulating layer 60 comprises a first dielectric or insulating layer 60a and a second dielectric or insulating layer 60b. The screening gates 50a-1 and 50a-2 and the conveyor gates 50b are separated by the first insulating or dielectric layer 60a and/or by the second insulating or dielectric layer 60b.

[00127] The dielectric or insulating layer 66 separates the screening gates 50a- 1 and 50a-2 and the semiconductor heterostructure 12. In the aspect shown in FIGS. 4A and 4B, the screening gate segments 50a-11 , 50a21 may be provided on the insulating layer 66. In the aspect shown in FIGS. 4A and 4B, a portion of the first dielectric and insulating layer 60a is arranged between the screening gate segments 50a-12, 50a-22 and the dielectric or insulating layer 66.

[00128] For instance, if on average two fidelity-reducing loci 70 are found per 1 pm along the at least one path 45 of the shuttling lane 16, the screening gate segments 50a-11 , 50a-12, 50a-21 , 50a-22 of the screening gates 50a may be designed to have lengths of no longer than approximately 500 nm. In one aspect, the screening gates 50a may be subdivided into four screening gate segments having lengths of approximately 250 nm.

[00129] The electrically disconnected screening gate segments 50a-11 , 50a-12, 50a-21 , 50a-22 are disconnected at a segmentation point (or disconnection point) 55. The screening gate segments 50a-11 , 50a-12, 50a-21 , 50a-22 of the screening gates 50a may be disconnected at the segmentation point 55 by the first dielectric or insulating layer 60a. At the segmentation point 55, the first dielectric or insulating layer 60a may be provided between the screening gate segments 50a-11 and 50a-12 and/or between the segments 50a-21 and 50a-22, respectively.

[00130] The screening gate 50a may be separated from the conveyor gates 50b by the dielectric or insulating layer 60. In one aspect, the first dielectric or insulating layer 60a may at least partially separate the screening gate 50a from the conveyor gates 50b. In this aspect, the second dielectric or insulating layer 60b may at least partially separate the screening gate 50a from the conveyor gates 50b. For example, in the aspect shown in FIG. 4B, the screening gate segments 50a-12, 50a- 22 of the screening gate 50a are separated from the conveyor gates 50b by the second dielectric or insulating layer 60b. In this aspect, the first dielectric or insulating layers 60a and the second dielectric or insulating layer 60b may be partially arranged on one another. A first portion 60a1 of first the dielectric or insulating layer 60a may be arranged on the screening gate segments 50a-11 , 50a-21 of the screening gate 50a. Furthermore, the screening gate segment 50a-12, 50a-22 of the screening gate 50a may be at least partially arranged on a second portion 60a2 of the first dielectric or insulating layer 60a. The screening gate segments 50a-12, 50a-22 of the screening gates 50a may thus be arranged at a higher level along a stacking direction D1 with respect to the segment 50a-11 , 50a-21 of the screening gates 50a (see FIG. 4B).

[00131 ] The first dielectric or insulating layer 60a may form a step 60as at the segmentation point 55. The step 60as may be part of the first dielectric or insulating layer 60a. The first portion 60a1 and second portion 60a2 may be connected by the step 60as. The step 60as may extend in the stacking direction D1 . Additionally, the step 60as may extend in the longitudinal direction D2.

[00132] In a further aspect, the shuttling lane 16 may comprise a protrusion 161. The protrusion may be located at the segmentation point 55. At the protrusion 161 , protruding ones conveyor gates 50bp of the conveyor gates 50b, a protruding section 60bp of the second dielectric or insulating layer 60b, a protruding section 50a-12p of the segment 50a-12 of the screening gates 50a, and/or a protruding section 50a-22p of the segment 50a-22 of the screening gates 50a may protrude along the stacking direction D1 relative to the at least one surface 14 (see FIG. 4B). The protruding ones of the conveyor gates 50bp of the conveyor gates 50b, the protruding section 60bp of the second dielectric or insulating layer 60b, the protruding section 50a-12p of the screening gate segment 50a-12 of the screening gates 50a, and/or the protruding section 50a-22p of the screening gate segment 50a-22 of the screening gates 50a may protrude relative to the conveyor gates 50b, the second dielectric or insulating layer 60b, the screening gate segment 50a-12 and/or the screening gate segment 50a-22, respectively. The conveyor gates 50bp, the section 60bp, the section 50a- 12p, and the section 50a-22p may thus be arranged at a higher level along the stacking direction D1 with respect to the conveyor gates 50b, the second dielectric or insulating layer 60b, the screening gate segment 50a-12, and the screening gate segment 50a-22, respectively. The protruding section 60bp of the second dielectric or insulating layer 60b may have portions that extend in the stacking direction D1 . The protruding section 60bp of the second dielectric or insulating layer may envelop the protruding section 50-12p of the screening gate segment 50a-12 and/or the protruding section 50-22p of the screening gate segment 50a-22. The protrusion 161 may extend in the lateral (transverse) direction D3 across the screening gate50a-1 and/or the screening gate 50a-2.

[00133] In another aspect, the protruding section 50a-12p of the screening gate segment 50a-12 and/or the protruding section 50a-22p of the screening gate segment 50a-22 of the screening gate 50a may be arranged to touch or intersect along the longitudinal direction D2 a line L extending along the stacking direction D1 (see FIG. 4B). The line L may also be touched along the longitudinal direction D2 by the screening gate segment 50a-11 and/or the screening gate segment 50a-21 of the screening gates 50a. In a further aspect, the screening gate segment 50a-12 and/or the screening gate segment 50a-22 may intersect the line L or overlap with the line L. In yet a further aspect, the screening gate segment 50a-11 and/or the screening gate segment 50a-21 may intersect the line L or overlap with the line L along the longitudinal direction D2. In other words, by means of the protruding section 50a-12p and/or 50a-22p, the screening gate segment 50a-11 and/or 50a-21 may overlap with the screening gate segment 50a-12 and/or 50a-22, respectively, in the shuttling direction (or longitudinal direction) D2 (see FIG. 4B)without contacting one another. . Arranging the screening gate segment 50a-11 and/or the screening gate segment 50a-21 to overlap in the shuttling direction (or longitudinal direction) D2 in contactless manner with the screening gate segment 50a-12 and/or 50a-22, respectively, enables providing a continuous potential by means of the voltage applied to the screening gate segment 50a-11 , 50a-12 of the screening gate 50a-1 and/or the voltage applied to the screening gate segment 50a-21 , 50a-22 of the screening gate 50a-2.

[00134] Alternatively, the shuttling lane 16 does not have the protrusion 161. In this case, the second dielectric or insulating layer 60b may have a planar surface. Furthermore, the conveyor gates 50b will in this case be arranged a the same level in the stacking direction D1 ; or the electrode subsets 50b-1 , 50b-2, 50b-3, 50b-4 will individually be arranged at the different levels (see above) in the stacking direction D1 , without any conveyor gates 50b protruding.

[00135] In yet another aspect, a gap in the screening gate 50a-1 and/or 50a-2 may be provided along the shuttling direction (or longitudinal direction) D2 at the segmentation point 55, where the screening gate 50a-1 and/or 50a-2 are separated into segments. The gap may be provided in the shuttling direction (or longitudinal direction) D2 between the screening gate segments 50a-11 , 50a-12 of the screening gate 50a-1 and/or between the screening gate segments 50a-21 , 50a-22 of the screening gate50a-2. The step 60as may be provided in the gap. In this aspect, none of the conveyor gates 50b may be arranged above the gap in the stacking direction D1 . Arranging the conveyor gates 50b, which provide the potential wells for moving (shuttling) the one or more qubits, without any overlap of the conveyor gates 50b with the gap avoids the conveyor gates 50b generating a potential that interferes with the potential defining the trajectory 80 provided by the screening gates (or path-defining gates) 50a-1 , 50a-2.

[00136] Segmenting the screening gates 50a into the screening gate segments 50a-11 , 50a-12 and/or 50a-21 , 50a-22 enables applying the voltages individually to the screening gate segments 50a-11 , 50a-12 and/or 50a-21 , 50a-22. The voltages that are individually applied to the screening gate segments 50a-11 , 50a-12 and/or 50a-21 , 50a-22 may be DC voltages, in which case, given a corresponding duration of the DC voltages, the trajectory 80-2 will be constant along the screening gate segments 50a-11 , 50a-12 and/or 50a-21 , 50a-22, as seen in the FIG. 5. In the example shown in FIG. 5, the screening gate 50a is segmented into three segments, to which individual DC voltages are applied, as can bee seen from the position of the trajectory 80-2 relative to the line with y = 0 nm.

[00137] The one or more segmentation points (or disconnection points) 55 may be arranged in the quantum processor 10 based on the determined density of fidelityreducing loci 70. Based on a distribution of the fidelity-reducing loci 70 that is derived from the positions of the identified fidelity-reducing loci 70, the segmentation points 55 may be arranged in the quantum processor 10. Assuming, for example, a Gaussian distribution of distances between the fidelity-reducing loci 70, with an average distance d and with a standard deviation of Od, the segmentation points 55 may be arranged in the quantum processor 10 with a distance of, for example, approximately d - 2xo_d between any two of the segmentation points 55.

[00138] In one aspect of the disclosure, the screening gate 50a-1 and the screening gate 50a-2 are segmented into the screening gate segments 50a-11 , 50a- 12 and 50a-21 , 50a-22, respectively. Alternatively, one of the screening gate 50a-1 and the screening gate 50a-2 is segmented. In this case, the screening gate 50a-1 is segmented into the screening gate segments 50a-11 , 50a-12, or the screening gate 50a-2 is segmented into the screening gate segments 50a-21 , 50a-22.

[00139] FIG. 9 shows an aspect of the disclosure, in which the shuttling lane 16 has two of the segmentation point 55. The screening gate 50a-1 is segmented into three segments 50a-11 , 50a-12, 50a-13, and/or the screening gate 50a-2 is segmented into three segments 50a-21 , 50a-22, 50a-23.

[00140] The shuttling lane 16 may contain two of the protrusion 161 , as described above. Likewise, the conveyor gates 50b may comprise two of the protruding ones conveyor gates 50bp, as described above. Likewise, the second dielectric or insulating layer 60b may comprise two of the protruding section 60bp, as described above. The two of the protruding section 60bp may belong to a single one of the dielectric or insulating layer 60b, as shown in FIG. 9. Likewise, the screening gate 50a-1 may comprise two of the protruding section 50a-12p, as described above; and/or the screening gate 50a-12 may comprise two of the protruding section 50a- 22p, as described above. The two of the protruding section 50a-12p may belong to a single one of the screening gate section 50a-12, as shown in FIG. 9. The two of the protruding section 50a-22p may belong to a single one of the screening gate section 50a-22, as shown in FIG. 9. The first dielectric or insulating layer 60a may comprise two of the step 60as. The two of the step 60as may belong to a single one of first dielectric or insulating layer 60a, as shown in FIG. 9.

[00141 ] FIGS. 10A and 10B show an application of the aspect of the disclosure shown in FIG. 9 to the T-junction 18 shown in FIG. 6A. The screening gate 50a-2 of the first shuttling element 16 of the screening gate 18 is segmented into three segments as described with reference to FIG.9 The segment 50a-22, as shown in FIG. 10A and 10B, may be arranged at the junction 28. This arrangement enables adjusting the voltage applied to the screening segment 50a-22 in the case of the presence of the fidelity-reducing locus 70 at the junction 70. The adjustment voltage AV may be added to the voltage applied to the screening gate segment 50a-22 in order to circumvent the fidelity-reducing Iocus70 located at the junction 28 by changing the trajectory 80, or to counteract the effect of the fidelity-reducing Iocus70 located at the junction 28 by increasing the confinement generated by the screening gate segment 50a-22, possibly in conjunction with the last conveyor gate 50b’ of the second shuttling element 16’. The screening gate segment 50a-22 has a contact 50a-22c for applying the adjustment voltage AV.

Claims

1 . A T-junction (18) for a quantum processor (10) comprising a plurality of gate electrodes (50) arranged on a semiconductor heterostructure (12), wherein

- the plurality of gate electrodes (50) comprises conveyor gates (50b) arranged at at least one path (45) and conveyor gates (50b’) arranged at branch (45’),

- the branch (45’) and the at least one path (45) are arranged substantially perpendicular to one another and meet at a junction (28);

- the conveyor gates (50b) and conveyor gates (50b’) are configured to be supplied with at least one voltage V, to move at least one qubit, arranged in the semiconductor heterostructure (12), along the at least one path (45) and/or along the branch (45’), and to divert the at least one qubit from the at least one path (45) into the branch (45’) or from the branch (45’) into the at least one path (45).

2. The T-junction (18) of claim 1 , wherein the conveyor gates (50b) are further configured to generate at least one travelling potential well to move the at least one qubit along the at least one path (45) or to generate a stationary potential well at the junction (28); and/or wherein the conveyor gates (50b’) are further configured to generate the traveling potential well to move the at least one qubit along the branch (45’) or to generate a confinement potential at the junction (28).

3. The T-junction (18) of claim 1 or 2, wherein the conveyor gates (50b) comprise electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) electrically disconnected from each other, the conveyor gates (50b) of any one of the electrode subsets (50b-1 , 50b-2, 50b-3, 50b-4) being electrically connected with each other.

4. The T-junction (18) of any one of claims 1 to 3, further comprising screening gates (50a-1 , 50a-2) arranged along the at least one path (45), and/or screening gates (50a’-1 , 50a’-2) arranged along the branch (45’).

5. The T-junction (18) of any one of claims 1 to 4, wherein screening gates (50a’-1 , 50a’-2) arranged along the branch (45’) are connected at the junction (28) with the screening gate (50a-1 ) arranged along the at least one path (45), and screening gate (50a-10) is interrupted between the screening gates (50a’-1 ) and (50a’-2).

6. The T-junction (18) of any one of claims 1 to 5, wherein at least one of the conveyor gates (50b’) overlaps at the junction (28) with screening gate (50a) arranged along the at least one path (45).

7. The T-junction (18) of any one of claims 1 to 6, wherein the conveyor gates (50b) are arranged on a planarized dielectric or insulating layer (60).

8. The T-junction (18) of any one of claims 1 to 7, further comprising a top gate (50d) arranged above the conveyor gates (50b) and/or the conveyor gates (50b’).

9. The T-junction (18) of any one of claims 1 to 8, further comprising a back gate (50c) arranged on the semiconductor heterostructure (12) and opposite the conveyor gates (50b) and the conveyor gates (50b’).

10. System comprising a T-junction (18) of any claims 1 to 9 and an external magnet for providing an external magnetic field Bo.

11 . Method of moving at least one qubit at a junction (28) of at least one path (45) and a branch (45’) in a semiconductor heterostructure (12) comprising a plurality of gate electrodes (50) arranged thereon, the at least one path 945) and the branch (45') being perpendicular to another and meeting at the junction (28), the method comprising

- providing an external magnetic field Bo;

- providing at the junction (28) a confinement to move the at least one qubit along the at least one path (45), or providing at the junction (28) a quasi- stationary potential well to adiabatically transfer the at least one qubit being moved along the branch (45) into the quasi-stationary potential well.

12. The method of claim 11 , where in the providing of the confinement comprises providing a stationary voltage to at least ones of conveyor gates (50b’).

13. The method of claim 11 or 12, where in the providing of the quasi-stationary potential well comprises providing a stationary voltage to at least ones of conveyor gates (50b).

14. The method of any one of claims 11 to 13, further comprising moving the at least one qubit from the junction (28) along the at least one path (45) or the branch (45’).