EP4540706A1

EP4540706A1 - Sliding-window load-replay queues

Info

Publication number: EP4540706A1
Application number: EP23782390.1A
Authority: EP
Inventors: Chanchal Kumar; Leigang KOU
Original assignee: Google LLC
Current assignee: Google LLC
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2025-04-23
Also published as: WO2025053855A1; TW202511948A; KR20250168330A; CN120936986A

Abstract

This document describes systems and techniques directed at sliding‑window load‑replay queues. In aspects, a computing device having a processor, a load replay queue, and an instruction pipeline manager is configured to receive a plurality of instructions including complete loads and incomplete loads. The instruction pipeline manager determines a sliding window that includes a portion of the incomplete loads and begins at an oldest incomplete load of the portion of the incomplete loads. The instruction pipeline manager assigns virtual identifiers to the portion of the incomplete loads, maps, based on the virtual identifiers, the portion of the incomplete loads to entry indexes of a load replay queue, and loads the portion of the incomplete loads into the load replay queue. The instruction pipeline manager replays the oldest incomplete load to produce a complete load and moves the sliding window to begin at a next oldest incomplete load.

Description

SLIDING-WINDOW LOAD-REPLAY QUEUES

BACKGROUND

[0001] Central processing units (CPUs) may execute instructions within an instruction execution window (e.g., instruction window, execution window). Some examples of the instructions CPUs may execute include loads, stores, adds, multiplies, and branches Each of these instructions may progress through various stages of an instruction pipeline, including fetches, decodes, dispatches, executes, and commits. To avoid data hazards (e.g., read-after-read (RAR) hazards, read-after-write (RAW) hazards), CPUs may include one or more load-store units (LSUs) that are configured to keep track of loads and stores within the execution window. The LSUs may further include structures (e.g., two-dimensional (2D) age matrixes) configured to keep track of relative ages of the loads and stores within the instruction window.

[0002] However, as CPUs become more capable, some of these structures may not scale efficiently as CPUs trend towards larger instruction windows. For example, a 2D age matrix may include an entry on an x-axis and on a y-axis for every instruction within an instruction window. That is, for an instruction window that includes N instructions, the 2D age matrix includes N² entries. As the instruction window increases at a rate proportional to N, the 2D age matrix increases at a rate proportional to N². This may result in CPUs that are less power efficient (e.g., 2D age matrixes may be difficult to clock gate) and physically larger.

SUMMARY

[0003] This document describes systems and techniques directed at sliding window load replay queues (SWLRQs). In aspects, a computing device having a processor, a load replay queue (LRQ), and an instruction pipeline manager (IPM) is configured to receive a plurality of instructions including at least complete loads and incomplete loads. The plurality of instructions may further include loads, stores, adds, multiplies, branches, and so forth. Receiving the plurality of instructions may include receiving a virtual window (e.g., a list) of all instructions from a dispatch stage of an instruction pipeline to a commit stage of the instruction pipeline.

[0004] The LRQ may be realized as an array of flip flops or latches that can store state information. The LRQ can be a part of the processor or a separate component that is operably (e.g., physically, electronically) coupled to the processor. The LRQ may include entry indexes (e.g., pointers, addresses) associated with positions within the array of the flip flops or latches. For example, the entry indexes may behave like a select input (e.g., select bits, select lines) of a multiplexer. [0005] The IPM determines a sliding window (e.g., list) that includes a portion of the incomplete loads. The portion of the incomplete loads may include N incomplete loads, where N is a positive integer greater than 1 (e.g., 100, 500, 678, 1,000, 2,000). Furthermore, the sliding window of the N incomplete loads may begin at an oldest incomplete load of the portion of the incomplete loads. Said differently, a head of the sliding window may point to the oldest incomplete load of the portion of the incomplete loads. Similarly, the sliding window of the N incomplete loads may end at a youngest incomplete load of the portion of the incomplete loads. Said differently, a tail of the sliding window may point to the youngest incomplete load of the portion of the incomplete loads.

[0006] The IPM may issue the incomplete loads from an issue queue (IQ) for a first attempt at execution. The incomplete loads may run into a delay condition (e.g., a cache miss) due to which the incomplete loads cannot be completed. The IPM assigns virtual identifiers to the portion of the incomplete loads, maps, based on the virtual identifiers, the portion of the incomplete loads to entry indexes of the LRQ, and sends the portion of the incomplete loads to the LRQ. The incomplete loads may sleep in the LRQ until the delay condition is resolved (e.g., cache miss resolves). The virtual identifiers may be assigned to the portion of the incomplete loads at a dispatch stage of an instruction pipeline. The virtual identifiers may be integers that are modulo results of positions in the virtual window of all instructions associated with the portion of the incomplete loads. For example, the oldest incomplete load may be a nineteenth instruction in the virtual window of all instructions and the sliding window of N incomplete instructions may include 16 incomplete instructions (e.g., N is equal to 16). Accordingly, a virtual identifier assigned by the IPM to the oldest incomplete load may be three (e.g., 19 modulo 16).

[0007] The IPM may map the portion of the incomplete loads to entry indexes of the LRQ by any one of a variety of mappings. A straightforward example includes directly mapping the portion of the incomplete loads to the LRQ by using the virtual identifiers as the entry indexes. Using the example described above, the oldest incomplete load having the virtual identifier of three may be mapped to a third position within the LRQ. Based on the mappings, the IPM loads the portion of the incomplete loads into the LRQ.

[0008] Once the delay condition is resolved, the IPM issues the oldest incomplete load from the LRQ to produce a complete load and moves the sliding window to begin at a next oldest incomplete load. For example, the oldest incomplete load may have been incomplete because it included a cache miss. Accordingly, the IPM may replay the oldest incomplete load by fetching information (e.g., data, addresses, operators) associated with the oldest incomplete load in a system memory of the computing device. Once complete, the IPM may produce the complete load based on the information in the system memory. Because the oldest incomplete load is now the complete load, the head of the sliding window may point to the next oldest incomplete load (e.g., a load one position younger than the oldest incomplete load). By so doing, the IPM maintains the LRQ as an implicitly ordered structure, negating any need for a 2D age matrix and conserving thermal design power (TDP) and physical space.

[0009] The details of one or more implementations are set forth in the accompanying Drawings and the following Detailed Description. Other features and advantages will be apparent from the Detailed Description, the Drawings, and the Claims. This Summary is provided to introduce subject matter that is further described in the Detailed Description. Accordingly, a reader should not consider the Summary to describe essential features or to threshold the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The details of one or more aspects of sliding-window load-replay queues are described in this document with reference to the following Drawings. The use of same numbers in different instances throughout the Drawings may indicate similar features or components.

Fig. 1 illustrates an example environment of a computing device having an implicitly ordered sliding-window LRQ;

Fig. 2 illustrates an example implementation of the computing device from Fig. 1, which is configured to provide the implicitly ordered sliding-window LRQ;

Fig. 3 illustrates an example implementation of an LSU having a sliding-window LRQ;

Fig. 4 illustrates an example implementation of the LSU from Fig. 3 further including a RAR queue;

Fig. 5 illustrates an example implementation of the LSU from Fig. 4 further including a store queue (SQ);

Fig. 6 illustrates an example implementation of the LSU from Fig. 5 further including a RAW queue; and

Fig. 7 depicts an example method that an IPM may implement to provide an implicitly ordered sliding-window LRQ.

DETAILED DESCRIPTION

Overview

[0011] Computing devices (e.g., smartphones, tablets, laptops) often include one or more CPUs that operate on instructions within an instruction pipeline. The CPUs may be any appropriate single-core or multi-core processor, some of which may include multi-threading capabilities. The instructions can be any one of a variety of instructions including loads, stores, adds, multiplies, branches, and the like. For loads and stores, it is important that CPUs keep track of which loads or stores are older than other loads and stores. If CPUs do not track relative ages of these instructions, various data hazards may occur, including read-after-read (RAR) hazards and read-after-write (RAW) hazards.

[0012] As an example, a first core of an out-of-order multi-core processor includes a first load and a second load in an instruction pipeline, and a second core of the multi-core processor includes a store in the instruction pipeline. The first load, the second load, and the store may access a memory location. The second load of the first core may be speculatively executed and fetch a first value from the memory' location. Then, the store of the second core may be executed and store a second value to the memory location. Lastly, the first load of the first core may be executed and fetch the second value from the memory location. If the multi-core processor in the present example does not include relative age tracking of the first load, the second load, and the store, then a RAR hazard occurs. The multi-core processor may include a 2D age matrix to avoid the RAR hazard.

[0013] As another example, a single-core processor may include a store followed by a load in an out-of-order instruction pipeline. Due to the out-of-order execution, the load, which is younger than the store, may execute before the store and acquire first data from a memory' address. Then, the single-core processor may complete the store, which is older than the load, and update the memory address to include second data. This can result in the load, which is younger than the store, having the first data rather than the second data. As in the multi-core processor example above, if the single-core processor does not track relative ages of the store and the load, then a RAW hazard occurs. The single-core processor may include a 2D age matrix for tracking the relative ages of stores and loads, and avoiding the RAW hazard.

[0014] Unfortunately, however, a 2D age matrix for tracking relative ages of instructions within an execution window of an instruction pipeline can be costly in terms of physical size, power, and scalability. The 2D age matrix may include an entry for each instruction within the execution window on an x-axis and a y-axis. The 2D age matrix may store a relative age of two instructions by including a value (e.g., a bit) at an intersection of two entries of the x-axis and the y-axis. The 2D age matrix may store the value by including a flip flop, a latch, or another appropriate circuit component. If the execution window includes N instructions (e.g., 100, 1,000, 3,000), for example, then the physical size of the 2D age matrix is N². Accordingly, the power consumed, especially during switching (e.g., of the flip-flops), by the 2D age matrix is proportional to N². Furthermore, scalability of a CPU associated with the 2D age matrix is inefficient as the 2D age matrix would need to scale by a factor of N² for a larger execution window.

[0015] Contrarily, sliding-window LRQs may include a single entry for each instruction within an execution window. In a sense, sliding-window LRQs may be thought of as one-dimensional age matrixes where relative ages of each instruction within the execution window are implicit. Accordingly, for sliding-window LRQs that include N instructions, a physical size and power consumption of the sliding-window LRQs are proportional to N, rather than N². Similarly, CPUs that include sliding-window LRQs may scale more efficiently (e.g., proportionally to N rather than N²) to include larger execution windows. In these ways, sliding-window LRQs address the fallbacks of physical size, power consumption, and seal abi 1 i ty associated with 2D age matrixes.

Example Operating Environment

[0016] Fig. 1 illustrates an example environment 100 of a computing device 102 having an implicitly ordered sliding- window LRQ 110 (SWLRQ 110). As illustrated, the computing device 102 includes computer-readable media 104 (CRM 104). The CRM 104 can include various storage devices, including volatile memory (e.g., dynamic random-access memory (DRAM)) and non-volatile memory (e.g., solid state storage, magnetic hard drive disks). The CRM 104 can be included in a housing of the computing device 102 or altogether one or more separate components that are operably coupled (e.g., wirelessly, physically) to the computing device 102.

[0017] The CRM 104 may further include computer-readable instructions configured to provide software features of the computing device 102. For example, the computer-readable instructions may include code for an operating system (OS), applications, software features, and so forth of the computing device 102. As illustrated, the computer-readable instructions of the CRM 104 may include an IPM 108. The IPM 108, described in further detail below, may be configured to manage instructions within an execution window of an instruction pipeline that are executed by a processor 106.

[0018] The processor 106 may be any appropriate single-core or multi-core processor, including a CPU, a graphics processing unit (GPU), a reduced instruction set computer (RISC), an advanced RISC machine (ARM) computer, a system-on-a-chip (SOC), and the like. The processor 106 can be realized as a single processor or multiple processors configured to work cooperatively. For example, two processors may be attached (e g., by solder, by pressure) to a motherboard, or other appropriate printed circuit board (PCB), of the computing device 102 and share a bus (e.g., data bus, memory bus, command and address bus, a combination thereof). [0019] Fig. 1 further illustrates that the processor 106 of the computing device 102 further includes the SWLRQ 110. The SWLRQ 110 of the processor 106 may be implemented as a sub-component or sub-circuit within the processor 106, a separate component on a same silicon die as the processor 106, or an altogether separate component that is operably coupled (e.g., by traces of a PCB) to the processor 106. The SWLRQ 110 may include a number of entry' indexes at which instructions of the execution window of the instruction pipeline may be stored. The number of entry' indexes may be a portion (e.g., one fifth) of instructions included in the execution window. For example, the execution window of the instruction pipeline may include 1,500 instructions and the SWLRQ 110 may include 300 entry indexes.

[0020] At each entry index, an instruction may be stored in a flip flop, latch, or other appropriate electrical component or circuit configured to store a number of bits that represent the instruction. For example, in a 16-bit system (e.g., 16-bit processor, 16-bit OS), an instruction may include 16 bits. A most significant bit (e.g., bit position 15) of the 16 bits may indicate an addressing mode (e.g., drrect mode, indirect mode). A next number (e.g., three) of most significant bits (e.g., bit positions 14 down to 12) may indicate an operation code (e.g., opcode) that describes an operation (e.g., load, store) to be performed (e.g., by the processor 106). A remaining number (e.g., 12) of least significant bits (e.g., bit positions 11 down to zero) may indicate an address (e.g., location in DRAM, location in cache) or operand. Therefore, in this example, the flip flops or latches at each entry index of the SWLRQ 110 may include 16 flip flops or latches configured to store one bit of the 16-bit instruction.

[0021] The computing device 102 also includes, as illustrated, a battery 112. The battery' 112 may be any one of a variety of batteries, including lithium batteries, lithium-ion batteries, alkaline batteries, carbon-zinc batteries, silver-oxide batteries, zinc-air batteries, and so forth. The CRM 104, the processor 106, and the SWLRQ 110 of the computing device 102 may be powered by the battery 112 via electrical connections (e.g., PCB routings, wires).

[0022] The IPM 108, as mentioned above, may be configured to manage a plurality of instructions within an execution window of an instruction pipeline. In an example, the plurality' of instructions within the execution window of the instruction pipeline include complete loads and incomplete loads. The IPM 108 may determine a sliding window (e.g., a virtual list) that includes a portion of the incomplete loads of the plurality of instructions. The portion of the incomplete loads may include N incomplete loads, where N is a positive integer (e.g., 1,500). The IPM 108 may configure the sliding window to begin at an oldest incomplete load (e.g., a head of the sliding window points to the oldest incomplete load) of the incomplete loads and include N incomplete loads. [0023] The IPM 108 may assign virtual identifiers to the N incomplete loads and map, based on the virtual identifiers, the N incomplete loads to N entry indexes of the SWLRQ 110. The IPM 108 may load, based on the mappings, the N incomplete loads into the SWLRQ 110. Because the SWLRQ 110 is implicitly ordered, no complementary or additional age-tracking structure (e.g., 2D age matrix) is necessary'.

[0024] The IPM 108 may replay a load of the N incomplete loads stored in the SWLRQ 110. For example, the IPM 108 may replay the oldest incomplete load of the N incomplete loads to produce a complete load. The IPM 108 may replay the oldest incomplete load by instructing the processor 106 to fetch information (e.g., data, opcode, operand, address) associated with the oldest incomplete load from a system memory, a cache, or another appropriate medium of the computing device 102. After producing the complete load, the IPM 108 may adjust the head of the sliding window to point at a next oldest incomplete load. Additionally, the IPM 108 may reassign a virtual identifier associated with the completed load to a next youngest incomplete load outside of the sliding window. The IPM 108 may map, based on the virtual identifier, the next youngest incomplete load to an entry index associated with the complete load. Based on the mapping, the IPM 108 may load the next youngest incomplete load into the SWLRQ 110 at a position associated with the entry index.

[0025] Thanks to an implicit ordering of incomplete loads within the SWLRQ 110, the IPM 108 may track relative ages of the incomplete loads in a power-efficient, space-conserving, and scalable way. As illustrated in Fig. 1, a user 114 of the computing device 102 having the IPM 108 and the SWLRQ 110 may enjoy various benefits associated with the IPM 108 and the SWLRQ 110. For example, the user 114 may enjoy a longer battery life 116 while consuming online digital content 118 (e.g., images, videos, articles) illustrated at 120. Further at 120, the user 114 may enjoy the longer battery life 116 while consuming the online content 118 with less fatigue, thanks to an overall smaller form factor of the computing device 102 (e.g., because of space conservation). Additionally, illustrated at 122, the user 114 may enjoy various benefits associated with a large execution window 124 (e.g., greater than 1,000 instructions), including improved multitasking, simulating, gaming, and so forth.

Example Devices

[0026] Fig. 2 illustrates an example implementation 200 of the computing device 102 from Fig. 1, which is configured to provide the implicitly ordered SWLRQ 110. The computing device 102 can be realized as various non-limiting example devices, including a smartphone 202a, a tablet 202b, a laptop 202c, a desktop 202d, a smartwatch 202e, a pair of smart glasses 202f, a game controller 202g, a smart home speaker 202h, or a microwave appliance 202i. Although not illustrated, the computing device 102 may also be realized as a health monitoring device, a personal media device, a drone, a home appliance, a security system or device thereof, a digital photo frame, and so forth. The computing device 102 can be wearable, non-wearable but mobile, or relatively immobile. Further, the computing device 102 can be used with or embedded within many computing devices or peripherals (e.g., vehicles, personal computers). The computing device 102 may also include additional interfaces or components omitted from Fig. 2.

[0027] Fig. 2 further illustrates that the computing device 102 can include various components described with reference to Fig. 1, including the CRM 104, the IPM 108, the processor 106, the SWLRQ 110, and the battery 112. In the example implementation 200 of the computing device 102, the CRM 104 may further include memory media 204 and storage media 206. The memory media 204 may include one or more non-transitory storage devices, including RAM or DRAM. The storage media 206 may include one or more transitory storage devices, including a solid-state drive (SSD), a magnetic spinning hard drive disk (HDD), a tape drive, and the like. Additionally, the CRM 104 may include an OS 208 and applications 210, which may be stored in the memory media 204 or the storage media 206 as computer-readable instructions like the IPM 108. The processor 106 may execute the computer-readable instructions of the IPM 108, the OS 208, and/or the application 210 to provide some or all the functionalities described herein.

[0028] The processor 106, again, can be any appropriate single-core or multi-core processor, which can include multi-threading capabilities. The processor 106 may be configured as an M-bit processor, where M is greater than or equal to one (e.g., 16, 32, 64). Accordingly, the processor may be configured to utilize an M-bit instruction set, where each instruction includes M bits and can be segmented into groups of bits to define an addressing mode, an opcode, an operand, a memory address, and so forth. The processor 106 may include one or more registers or one or more cache memories, including a level one (LI) cache memory or a level two (L2) cache memory, for storing instructions of the M-bit instruction set. The processor 106 may store and access data (e.g., instructions, operators, operands) in the cache memories for quicker processing. The processor 106 can include various components or circuits dedicated to specific functions. For example, the processor 106 may include a decode circuit dedicated to decoding instructions within an instruction pipeline, an arithmetic logic unit (ALU) dedicated to performing binary mathematics, a memory controller (MC) dedicated to accessing the CRM 104, and so forth. The processor 106 may further include the SWLRQ 110 realized as an array of logic gates, flip flops, latches, and so forth. [0029] Further illustrated in Fig. 2, the computing device 102 may include a display 212. The display 212 may be realized as a display panel or a display module that includes the display panel and a display driver integrated circuit (DDIC) configured to control a brightness, color, refresh rate, and so forth of the display panel. The display panel of the display 212 can include one of a variety of display panels , including a liquid crystal display (LCD) panel, a light-emitting diode (LED) panel, an organic LED (OLED) panel, an active-matrix OLED (AMOLED) panel, and the like. The display 212 may present content (e.g., images, video, a user interface (UI)) to a user (e.g., user 114 of Fig. 1) of the computing device 102. The display 212 may further include a digitizer or another form of a touch input device (e.g., a touchscreen) to receive user input from the user.

[0030] The computing device 102 can also include one or more input/output (I/O) ports 214. As an example, the I/O ports 214 can enable the computing device 102 to interact with other devices or users through peripheral devices, transmitting any combination of digital signals and/or analog signals via wired manners (e.g., ethemet) or wireless manners (e.g., radio). The I/O ports 214 may include any combination of internal or external ports, including universal serial bus (USB) ports, audio ports, video ports, peripheral component interconnect express (PCIe) ports, and so forth. Various peripheral devices (e.g., human input devices (HIDs), external CRM, speakers, displays) may be operably coupled to the computing device 102 with the I/O ports 214. Fig. 2 also illustrates that the computing device 102 may include one or more sensors 216. The sensors 216 can include image sensors (e.g., cameras), audio sensors (e.g., microphones), accelerometers, barometers, ambient light sensors, thermometers, and so forth. The sensors 216 may enable the computing device 102 to perform various functions (e.g., capturing images, captunng audio) that are useful to the user.

[0031] Although not illustrated, the computing device 102, or the IPM 108 or the SWLRQ 110 thereof, can include one or more integrated circuits (ICs) (e.g., a power management integrated circuit (PMIC)), an SOC, a secure key store, hardware embedded with firmware, a PCB with various hardware components (e.g., a motherboard, a daughterboard), or any combination thereof. Further, the computing device 102 may include one or more communication buses (e.g., data buses, address buses, command buses) for transferring information between components of the computing device 102 (e.g., between the processor 106 and the CRM 104) and/or peripheral components.

[0032] Fig. 3 illustrates an example implementation 300 of an LSU 302 having an SWLRQ 304. In the implementation 300, the SWLRQ 304 is included as part of the LSU 302, which may be a sub-circuit or component of a processor (e.g., processor 106) or other CPU. The LSU 302 may be responsible for making memory operation decisions, including loads from or stores to a system memory (e.g., DRAM, cache, SSD). The LSU 302 may include an issue queue 306 (IQ 306) in addition to the SWLRQ 304. The IQ 306 may help facilitate out-of-order instruction execution.

[0033] Fig. 3 further illustrates that the SWLRQ 304 includes a number of entry indexes 308. In the example implementation 300, the entry indexes 308 of the SWLRQ 304 include four entry indexes 308 and are labeled “pO” through “p3”. Similarly, Fig. 3 illustrates a virtual window 310, which also includes virtual identifiers 312. The virtual window 310 may include all loads from a dispatch stage of an instruction pipeline to a commit stage of the instruction pipeline. In this example, the virtual window 310 includes eight virtual identifiers 312 that are labeled “vO” through “v7”

[0034] As illustrated, the virtual window 310 includes a number of loads 314. Each load 314 is assigned a respective virtual identifier 312. An oldest complete load 314a and a second oldest complete load 314b may be stored at virtual identifiers 312 vO and vl, respectively. An oldest incomplete load 314c may be stored at a virtual identifier 312 v2 of the virtual window 310. Additionally, younger incomplete loads 314d, 314e, and 314f may be stored at virtual identifiers 312 v3, v4, and v5, respectively. A youngest dispatched load 314g and a next youngest dispatched load 314h may be stored at virtual identifiers 312 v6 and v7, respectively.

[0035] An IPM (e.g., IPM 108 of Figs. 1 and/or 2) may utilize the SWLRQ 304, the IQ 306, and the virtual window 310. For example, the IPM may determine a sliding window that includes a portion of the incomplete loads 314c through 314h. The portion of the incomplete loads 314c through 314h may include a same number of incomplete loads as a size of the SWLRQ 304. In this example 300, the sliding window may include the oldest incomplete load 314c and a next three incomplete loads 314d through 314f The IPM may map the incomplete loads 314c through 314f to the entry indexes 308 of the SWLRQ 304.

[0036] As an example, the IPM may take a modulo four result of a right-most digit of the virtual identifiers 312 as the mapping. Thus, the oldest incomplete load 314c at virtual identifier v2 is mapped to entry index 308 p2 (e.g., 2 % 4 = 2) of the SWLRQ 304. Similarly, the incomplete load 314d at virtual identifier v3 is mapped to entry index 308 p3 (e.g., 3 % 4 = 3) of the SWLRQ 304, the incomplete load 314e at virtual identifier v4 is mapped to entry index 308 pO (e.g., 4 % 4 = 0), and the incomplete load 314f at virtual identifier v5 is mapped to en Inin dex 308 pl (e.g., 5 % 4 = 1). By so doing, the IPM loads the incomplete loads 314c through 314f into the SWLRQ 304 in an implicitly ordered manner. Thus the IPM may replay the oldest incomplete load 314c at the entry index 308 p2 of the SWLRQ 304 to produce a complete load.

[0037] Although not shown, the IPM may reassign the entry index 308 p2 of the now complete load (e.g., previously the oldest incomplete load 314c) to a next youngest incomplete load 314g at virtual identifier 312 v6 of the virtual window 310. The IPM may load the incomplete load 314g into the SWLRQ 304 at the entry index 308 p2 (e.g., 6 % 4 = 2) of the SWLRQ 304. The IPM may repeat the process of producing complete loads from oldest incomplete loads within the implicitly ordered SWLRQ 304.

[0038] Fig. 4 illustrates an example implementation 400 of the LSU 302 from Fig. 3 further including a RAR queue 402 (RAR 402). The RAR 402 may be similar to the SWLRQ 304 or the IQ 306 in that it stores instructions of an instruction pipeline using an array of flip-flops or latches. The RAR 402 may store instructions that pose potential RAR hazards. For example, a RAR hazard may occur in a dual-core processor where a first core executes first and second loads (e.g., reads) and a second core executes a store. The dual-core processor may be configured to execute instructions in an out-of-order or speculative fashion. The first load of the first core may encounter a cache miss. Accordingly, the first core may execute the second load before the first load to an address in memory. The second core may then execute the store to a same address in memory, updating a data value stored at the same address. Finally, the first core may execute the first load to the same address in memory. This results in a RAR hazard where the first load includes data that is newer than data in the second load.

[0039] An IPM may utilize the LSU 302 having the RAR 402 to address such an issue. For example, if an instruction (e.g., a dispatched load 314g or 314h) is executed before an incomplete load within the SWLRQ 304, the IPM may allocate a position in the RAR 402 for the instruction, as illustrated. Further, the IPM may check the RAR 402 and/or the SWLRQ 304 for hazards associated with a currently executing load (e.g., incomplete load 314c as described above with reference to Fig. 3).

[0040] Additionally or alternatively, for a complete load within the SWLRQ 304 that may be a potential RAR hazard, the IPM may keep the complete load within the SWLRQ 304 rather than allocating a space for the complete load within the RAR 402. By so doing, the IPM enables the RAR 402 to be smaller, conserving space within the LSU 302. As an example, the oldest incomplete load 314c may encounter a delay (e.g., cache miss), so the IPM completes the next oldest incomplete load 314d instead. Because the next oldest incomplete load 314d may present a RAR hazard with respect to the oldest incomplete load 314c, the IPM may reserve the entry index 308 p3 rather than loading the next oldest incomplete load 314d into the RAR 402. Once the IPM completes the oldest incomplete load 314c, the IPM may check the SWLRQ 304 for a RAR hazard associated with the completed load (previously the incomplete load 314d).

[0041] Fig. 5 illustrates an example implementation 500 of the LSU 302 from Fig. 4 further including a store queue 502 (SQ 502). Fig. 5 further illustrates that an IPM (e.g., IPM unresolved store. In this example, the field 504 is represented by an asterisk (e.g., a pointer to the bypassed youngest unresolved store) and the bypassed youngest unresolved store may be associated with the completed load (previously the incomplete load 314d). The SQ 502 may include a number of stores 506, including a first unresolved store 506a and a second unresolved store 506b. The first unresolved store 506a may be older than the second unresolved store 506b, and the IPM may track the first unresolved store 506a as an oldest unresolved store.

[0042] Fig. 6 illustrates an example implementation 600 of the LSU from Fig. 5 further including a RAW queue 602 (RAW 602). The RAW 602 may be utilized by an IPM to store instructions with potential RAW hazards. As an example, a first instruction in an instruction pipeline may be a store (e.g., a write) and a second instruction in the instruction pipeline may be a load (e.g., a read), and both the first and second instructions may use a same address in memory. If the IPM executes the load before the store, then the load, which is younger than the store, will fetch old data at the same address in memory. This is a RAW hazard.

[0043] The IPM may complete the oldest incomplete load 314c and the next oldest incomplete load 314d, which includes the field 504 for tracking the youngest unresolved store. Accordingly, the IPM may move the sliding window past the now completed loads (previously the oldest incomplete load 314c and the next oldest incomplete load 314d). The IPM may compare, responsive to moving the sliding window past the completed loads, the bypassed youngest unresolved store tracked by the field 504 to the oldest unresolved store 506a to produce a comparison result.

[0044] The comparison result may indicate that the bypassed youngest unresolved store tracked by the field 504 is younger than the oldest unresolved store 506a within the SQ 502. Based on the comparison result, the IPM may allocate a space within the RAW 602 for the complete load (previously the incomplete load 314d) as illustrated. Additionally or alternatively, the IPM may complete (e.g., by instructing a processor to execute) an incomplete load outside of the sliding window (e.g., incomplete load 314h) to produce a complete load. The IPM may then allocate a space within the RAW 602 for storing the complete load with a potential for a RAW hazard, as illustrated. Further, the IPM may check the SWLRQ 304 and/or the RAW 602 for hazards associated with a currently executing store. The IPM may replay any one or more instructions related to the hazards associated with the currently executing store.

Example Method

[0045] Fig. 7 depicts an example method that an IPM may implement to provide an implicitly ordered SWLRQ (e.g., SWLRQ 304 of Figs. 3, 4, 5, and/or 6). At 702, an IPM (e.g., IPM 108 of Figs. 1 and/or 2) may receive a plurality of instructions (e.g., virtual window 310) of an instruction pipeline, the plurality of instructions comprising complete loads and incomplete loads. The plurality of instructions may include other instructions, including loads, stores, mathematical operations, branches, and so forth. The instruction pipeline may be an out-of-order or speculative instruction pipeline where a CPU (e.g., processor 106 of Figs. 1 and/or 2) executes the plurality of instructions in an out-of-order or speculative fashion.

[0046] At 704, the IPM determines a sliding window comprising a portion of the incomplete loads, beginning at an oldest incomplete load (e g., oldest incomplete load 314c of Figs. 3 through 6) and ending at a youngest incomplete load (e.g., incomplete load 314f). The sliding window may be a virtual list of the portion of the incomplete loads. A head of the sliding window may point to the oldest incomplete load, and a tail of the sliding window may point to the youngest incomplete load. The portion of the incomplete loads may include a positive integer of incomplete loads (e.g., four, 16, 32). However, in out-of-order execution, the IPM may complete the youngest incomplete load before the oldest incomplete load. This can result in the sliding window beginning at the oldest incomplete load while ending at a complete load (previously the youngest incomplete load). That is, the head of the sliding window always points to the oldest incomplete load while the remaining loads within the sliding window' may be complete and/or incomplete.

[0047] At 706, the IPM assigns a first virtual identifier (ID) (e.g., v2 of Fig. 3 through 6), a second virtual ID (e.g., v5 of Figs. 3 through 6), and additional virtual IDs (e.g., v3 and v4 of Figs. 3 through 6) to the oldest incomplete load, the youngest incomplete load, and remaining incomplete loads, respectively, of the portion of the incomplete loads. The virtual IDs may be tike the virtual IDs 312 of Figs. 3 through 6. The virtual IDs may be binary digits of any number of bits (e.g., four, eight, 16, 64) suitable to uniquely identify each incomplete load in the portion of the incomplete loads.

[0048] At 708, the IPM maps, based on the first virtual ID, the second virtual ID, and the additional virtual IDs, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads to a first entry index (e.g., p2 of Figs. 3 through 6), a second entry index (e.g., pl of Figs. 3 through 6), and remaining entry indexes (e.g., p3 and pO of Figs. 3 through 6) of a SWLRQ (e.g., SWLRQ 304 of Figs. 3 through 6). The IPM may issue the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads from an issue queue (e.g., IQ 306 of Figs. 3 through 6). The oldest incomplete load, the youngest incomplete load, and/or the remaining incomplete loads may experience a subsequent delay in execution (e.g., a cache miss). Thus, at 710, based on the first entry index, the second entry' index, and the remaining entry indexes, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads, respectively, are loaded into the SWLRQ. [0049] At 712, the IPM may replay the oldest incomplete load of the portion of the incomplete loads in the SWLRQ to produce a complete load. At 714, the IPM may reassign, responsive to producing the complete load, the first virtual ID to a next youngest incomplete load (e.g., incomplete load 314g of Figs. 3 through 6) younger than the youngest incomplete load and outside of the portion of the incomplete loads (e.g., outside of the sliding window).

[0050] At 716, the IPM may map, based on the reassigned first virtual ID, the next youngest incomplete load to the first entry index of the SWLRQ. As described with reference to Fig. 3, the oldest incomplete load 314c may be completed by the IPM 108 (e.g., by instructing a CPU to execute the oldest incomplete load 314c), at which point the oldest incomplete load 314c may not require its position within the SWLRQ 304 at the entry index 308 p2. Accordingly, the IPM 108 may map and load the next youngest incomplete load 314g to the entry index 308 p2 of the SWLRQ 304.

[0051] By performing the method 700 of Fig. 7, the IPM may conserve physical space and power of a processor (e.g., a CPU, processor 106 of Figs. 1 and/or 2). Further, when utilized in an intelligent manner, as described with reference to Figs. 4 through 6, space within the SWLRQ 304 for complete instructions younger than the oldest incomplete load within the SWLRQ 304 may be conserved rather than the complete instructions being assigned to spaces within the RAR 402 and/or the RAW 602. This enables the RAR 402 and/or the RAW 602 to be physically smaller and consume less power. Additionally, the implicit ordering of the SWLRQ 304 enabled by performing the method 700 lends to greater scalability of processors as execution windows increase (e.g., beyond 1,000 instructions).

Additional Examples

[0052] In the following section, additional examples are provided.

[0053] Example 1: A method comprising: receiving, by an instruction pipeline manager, a plurality of instructions of an instruction pipeline, the plurality of instructions comprising complete loads and incomplete loads; determining, by the instruction pipeline manager, a sliding window comprising a portion of the incomplete loads, the sliding window beginning at an oldest incomplete load of the portion of the incomplete loads, the sliding window ending at a youngest incomplete load of the portion of the incomplete loads; assigning, by the instruction pipeline manager, a first virtual identifier, a second virtual identifier, and additional virtual identifiers to the oldest incomplete load, the youngest incomplete load, and remaining incomplete loads, respectively, of the portion of the incomplete loads; mapping, by the instruction pipeline manager, based on the first virtual identifier, the second virtual identifier, and the additional virtual identifiers, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads of the portion of the incomplete loads to a first entry index, a second entry index, and remaining entry indexes, respectively, of a load replay queue; loading, by the instruction pipeline manager, based on the first entry index, the second entry index, and the remaining entry indexes, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads, respectively, into the load replay queue; replaying, by the instruction pipeline manager, the oldest incomplete load of the portion of the incomplete loads in the load replay queue to produce a complete load; reassigning, by the instruction pipeline manager and responsive to producing the complete load, the first virtual identifier to a next youngest incomplete load, the next youngest incomplete load younger than the youngest incomplete load of the portion of the incomplete loads, the next youngest incomplete load outside of the portion of the incomplete loads; and mapping, by the instruction pipeline manager and based on the reassigned first virtual identifier, the next youngest incomplete load outside of the portion of the incomplete loads to the first entry index of the load replay queue.

[0054] Example 2: The method of example 1, wherein: the portion of the incomplete loads of the plurality of instructions comprises N incomplete loads, where N is an integer greater than one; and the incomplete loads of the plurality of instructions comprise M incomplete loads, where M is an integer greater than N.

[0055] Example 3: The method of any one of the preceding examples, wherein: the first virtual identifier comprises a head of the sliding window; the second virtual identifier comprises a tail of the sliding window; and the additional virtual identifiers comprise virtual identifiers between the head and the tail of the sliding window.

[0056] Example 4: The method of any one of the preceding examples, wherein: the first virtual identifier is an integer greater than or equal to zero and the first entry index of the load replay queue is a modulo result of the first virtual identifier; the second virtual identifier is an integer greater than the first virtual identifier and the second entry' index is a modulo result of the second virtual identifier; and the additional virtual identifiers are integers greater than the first virtual identifier and less than the second virtual identifier, and the remaining entry indexes are modulo results of the additional virtual identifiers.

[0057] Example 5: The method of any one of the preceding examples, further comprising: replaying, by the instruction pipeline manager, an incomplete load of the remaining incomplete loads to produce a completed load, the completed load younger than the oldest incomplete load; and reusing, by the instruction pipeline manager, an entry index of the load replay queue associated with the completed load y ounger than the oldest incomplete load.

[0058] Example 6: The method of any one of the preceding examples, further comprising: reserving, by the instruction pipeline manager, an entry' index of the load replay queue associated with a complete load; and keeping, by the instruction pipeline manager, the complete load within the load replay queue at the entry index effective to conserve space of a read-after-read hazard queue.

[0059] Example 7: The method of any one of the preceding examples, further comprising: completing, by the instruction pipeline manager, an incomplete load outside of the sliding window to produce a completed load outside of the sliding window; and allocating, by the instruction pipeline manager, a space within a read after read hazard queue for the completed load outside of the sliding window.

[0060] Example 8: The method of example 7, further comprising at least one of: checking, by the instruction pipeline manager, the load replay queue for hazards associated with a currently executing load; or checking, by the instruction pipeline manager, the read after read hazard queue for hazards associated with the currently executing load.

[0061] Example 9: The method of any one of the preceding examples, further comprising: adding, by the instruction pipeline manager, a field to the load replay queue that tracks a bypassed youngest unresolved store; tracking, by the instruction pipeline manager, an oldest unresolved store within a store queue; and comparing, by the instruction pipeline manager and responsive to moving the sliding window past a completed load, the bypassed youngest unresolved store to the oldest unresolved store to produce a comparison result.

[0062] Example 10: The method of example 9, wherein the comparison result indicates that the bypassed youngest unresolved store is younger than the oldest unresolved store and the method further comprises reserving, by the instruction pipeline manager and based on the comparison result, an entry index within a read after write hazard queue for a completed load.

[0063] Example 11 : The method of any one of the preceding examples, further comprising: completing, by the instruction pipeline manager, an incomplete load outside of the sliding window to produce a completed load outside of the sliding window; and allocating, by the instruction pipeline manager, a space within the read after write hazard queue for the completed load outside of the sliding window.

[0064] Example 12: The method of example 11, further comprising at least one of: checking, by the instruction pipeline manager, the load replay queue for hazards associated with a currently executing store; or checking, by the instruction pipeline manager, the read after write hazard queue for hazards associated with the currently executing store.

[0065] Example 13: The method of any one of the preceding examples, wherein completing an incomplete load comprises instructing, by the instruction pipeline manager, at least one processor to execute the incomplete load. [0066] Example 14: A computing device comprising: at least one processor; at least one read after read hazard queue; at least one read after write hazard queue; at least one store queue; at least one load replay queue; and computer readable media storing instructions that, when executed by the at least one processor, cause the at least one processor to implement an instruction pipeline manager utilizing the at least one read after read hazard queue, the at least one read after write hazard queue, the at least one store queue, and the at least one load replay queue by performing the method of any one of examples 1-13.

[0067] Example 15: Computer readable media comprising instructions that, when executed by at least one processor, cause the at least one processor to perform the method of any one of examples 1-13.

Conclusion

[0068] Unless context dictates otherwise, use herein of the word “or” may be considered use of an “inclusive or,” or a term that permits inclusion or application of one or more items that are linked by the word “or” (e.g., a phrase “A or B” may be interpreted as permitting just “A,” as permitting just “B,” or as permitting both “A” and “B”). Also, as used herein, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. For instance, “at least one of a, b, or c” can cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Further, items represented in the accompanying Drawings and terms discussed herein may be indicative of one or more items or terms, and thus reference may be made interchangeably to single or plural forms of the items and terms in this wntten description.

[0069] Although implementations of systems and techniques of, and apparatuses enabling, sliding-window load-replay queues have been described in language specific to certain features and/or methods, the subject of the appended Claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of sliding-window load-replay queues.

Claims

CLAIMS What is claimed is:

1. A method comprising: receiving, by an instruction pipeline manager, a plurality of instructions of an instruction pipeline, the plurality of instructions comprising complete loads and incomplete loads; determining, by the instruction pipeline manager, a sliding window comprising a portion of the incomplete loads, the sliding window beginning at an oldest incomplete load of the portion of the incomplete loads, the sliding window ending at a youngest incomplete load of the portion of the incomplete loads; assigning, by the instruction pipeline manager, a first virtual identifier, a second virtual identifier, and additional virtual identifiers to the oldest incomplete load, the youngest incomplete load, and remaining incomplete loads, respectively, of the portion of the incomplete loads; mapping, by the instruction pipeline manager, based on the first virtual identifier, the second virtual identifier, and the additional virtual identifiers, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads of the portion of the incomplete loads to a first entry index, a second entry index, and remaining entry indexes, respectively, of a load replay queue; loading, by the instruction pipeline manager, based on the first entry index, the second entry index, and the remaining entry indexes, the oldest incomplete load, the youngest incomplete load, and the remaining incomplete loads, respectively, into the load replay queue; replaying, by the instruction pipeline manager, the oldest incomplete load of the portion of the incomplete loads in the load replay queue to produce a complete load; reassigning, by the instruction pipeline manager and responsive to producing the complete load, the first virtual identifier to a next youngest incomplete load, the next youngest incomplete load younger than the youngest incomplete load of the portion of the incomplete loads, the next youngest incomplete load outside of the portion of the incomplete loads; and mapping, by the instruction pipeline manager and based on the reassigned first virtual identifier, the next youngest incomplete load outside of the portion of the incomplete loads to the first entry index of the load replay queue.

2. The method of claim 1, wherein: the portion of the incomplete loads of the plurality of instructions comprises N incomplete loads, where N is an integer greater than one; and the incomplete loads of the plurality of instructions comprise M incomplete loads, where M is an integer greater than N.

3. The method of any one of the preceding claims, wherein: the first virtual identifier comprises a head of the sliding window; the second virtual identifier comprises a tail of the sliding window; and the additional virtual identifiers comprise virtual identifiers between the head and the tail of the sliding window.

4. The method of any one of the preceding claims, wherein: the first virtual identifier is an integer greater than or equal to zero and the first entry index of the load replay queue is a modulo result of the first virtual identifier; the second virtual identifier is an integer greater than the first virtual identifier and the second entry index is a modulo result of the second virtual identifier; and the additional virtual identifiers are integers greater than the first virtual identifier and less than the second virtual identifier, and the remaining entry indexes are modulo results of the additional virtual identifiers.

5. The method of any one of the preceding claims, further comprising: replaying, by the instruction pipeline manager, an incomplete load of the remaining incomplete loads to produce a completed load, the completed load younger than the oldest incomplete load; and reusing, by the instruction pipeline manager, an entry index of the load replay queue associated with the completed load younger than the oldest incomplete load.

6. The method of any one of the preceding claims, further comprising: reserving, by the instruction pipeline manager, an entry index of the load replay queue associated with a complete load; and keeping, by the instruction pipeline manager, the complete load within the load replay queue at the entry index effective to conserve space of a read-after-read hazard queue.

7. The method of any one of the preceding claims, further comprising: completing, by the instruction pipeline manager, an incomplete load outside of the sliding window to produce a completed load outside of the sliding window; and allocating, by the instruction pipeline manager, a space within a read-after-read hazard queue for the completed load outside of the sliding window.

8. The method of claim 7, further comprising at least one of: checking, by the instruction pipeline manager, the load replay queue for hazards associated with a currently executing load; or checking, by the instruction pipeline manager, the read-after-read hazard queue for hazards associated with the currently executing load.

9. The method of any one of the preceding claims, further comprising: adding, by the instruction pipeline manager, a field to the load replay queue that tracks a bypassed youngest unresolved store; tracking, by the instruction pipeline manager, an oldest unresolved store within a store queue; and comparing, by the instruction pipeline manager and responsive to moving the sliding window past a completed load, the bypassed youngest unresolved store to the oldest unresolved store to produce a comparison result.

10. The method of claim 9, wherein the comparison result indicates that the bypassed youngest unresolved store is younger than the oldest unresolved store and the method further comprises reserving, by the instruction pipeline manager and based on the comparison result, an entry index within a read after write hazard queue for a completed load.

11. The method of any one of the preceding claims, further comprising: completing, by the instruction pipeline manager, an incomplete load outside of the sliding window to produce a completed load outside of the sliding window; and allocating, by the instruction pipeline manager, a space within the read-after-write hazard queue for the completed load outside of the sliding window.

12. The method of claim 11, further comprising at least one of: checking, by the instruction pipeline manager, the load replay queue for hazards associated with a currently executing store; or checking, by the instruction pipeline manager, the read-after-write hazard queue for hazards associated with the currently executing store.

13. The method of any one of the preceding claims, wherein completing an incomplete load comprises instructing, by the instruction pipeline manager, at least one processor to execute the incomplete load.

14. A computing device comprising: at least one processor; at least one read-after-read hazard queue; at least one read-after-write hazard queue; at least one store queue; at least one load replay queue; and computer-readable media storing instructions that, when executed by the at least one processor, cause the at least one processor to implement an instruction pipeline manager utilizing the at least one read-after-read hazard queue, the at least one read-after-write hazard queue, the at least one store queue, and the at least one load replay queue by performing the method of any one of claims 1-13.

15. Computer-readable media compnsing instructions that, when executed by at least one processor, cause the at least one processor to perform the method of any one of claims 1-13.