EP4494357A1

EP4494357A1 - Image sensor array with ramp generator and comparing circuit

Info

Publication number: EP4494357A1
Application number: EP23705606.4A
Authority: EP
Inventors: Noam Zeev ESHEL; Golan Zeituni
Original assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Current assignee: Sony Europe BV; Sony Semiconductor Solutions Corp
Priority date: 2022-03-18
Filing date: 2023-02-22
Publication date: 2025-01-22
Also published as: WO2023174655A1

Abstract

A pixel circuit (100) of an image sensor array (10) includes an amplification transistor (103) and a selection transistor (109) electrically connected in series between a first positive voltage supply node (VDDP) and a data signal line (VSL). The pixel circuit (100) outputs a pixel output signal (Vout) on the data signal line (VSL). A constant current circuit (210) is electrically connected between the data signal line (VSL) and a first negative voltage supply node (VDDP). A ramp generator (220) generates a voltage ramp signal (Vrmp). A comparing circuit (230) includes a voltage-controlled switching element (231). The comparing circuit (230) generates an active comparator output signal (Vcout1) at a comparator output node (239) when a voltage difference between the voltage ramp signal (Vrmp) and the pixel output signal (Vout) exceeds a threshold voltage of the voltage-controlled switching element (231).

Description

IMAGE SENSOR ARRAY WITH RAMP GENERATOR AND COMPARING CIRCUIT

The present disclosure relates to an image sensor array of a solid-state imaging device. More particularly, the present disclosure relates to an image sensor array including a ramp generator circuit and a comparing circuit for intensity readout.

BACKGROUND

Image sensors in solid-state imaging devices include photoelectric conversion devices generating a photocurrent in proportion to the received radiation intensity. A pixel circuit transforms the small photocurrent generated by the photoelectric conversion device into a voltage signal (pixel output signal) and outputs the pixel output signal on a data line (vertical signal line). A downstream ADC (analog-to-digital converter) converts the analog pixel output signal into a digital pixel value. The ADC may be a ramp compare ADC that includes a ramp generator circuit, a comparator circuit and a counter. The comparator circuit compares the pixel output signal with a voltage ramp generated by the ramp generator circuit and outputs an active comparator signal when the voltage ramp exceeds or falls below the pixel output signal. The counter counts events that occur at regular intervals in a counting period between the start of the voltage ramp and the start of the active comparator signal. The count value at the end of the counting period gives the result of the analog-to-digital conversion and defines the digital pixel value.

The data signal line is shared by a plurality of pixel circuits assigned to the same pixel column and the pixel output signals of each pixel column are output individually in a time multiplex regime. A column signal processing unit including the ADC sequentially receives and processes the pixel output signals of the pixels assigned to the same pixel column.

SUMMARY

In a solid-state imaging device having a column signal processing unit for processing the pixel output signals transmitted on the data signal lines, each data signal line is terminated by a constant current source. The constant current source pre-charges the data signal line during periods, when none of the pixel circuits connected to the data signal line is selected. The comparator circuit on the other hand typically includes a specialized high-gain differential amplifier with two analog input terminals, wherein the differential amplifier compares the two voltages applied to the two analog input terminals and outputs a digital comparator output signal indicating which of the two voltages is greater. Differential amplifiers typically include a pair of source-coupled transistors sharing a common tail current source permanently drawing current.

The present disclosure mitigates shortcomings of column signal processing units used for intensity readout. In particular, power consumption can be reduced without compromising SNR (signal-to-noise ratio) and without requiring more chip area.

To this purpose, an image sensor array according to the present disclosure includes a pixel circuit that includes an amplification transistor and a selection transistor electrically connected in series between a first power supply node and a data signal line. The pixel circuit outputs a pixel output signal on the data signal line. A constant current circuit is electrically connected between the data signal line and a second power supply node. A ramp generator generates a voltage ramp signal. A comparing circuit includes a voltage-controlled switching element. The comparing circuit generates an active comparator output signal at a comparator output node when a voltage difference between the voltage ramp signal and the pixel output signal exceeds a threshold voltage of the voltage- controlled switching element.

Thereby the current supplied by the constant current circuit is divided between a first branch including the selected pixel circuit and a second branch including the controlled path of the voltage-controlled switching element. Since the voltage-controlled switching element is off at the beginning of the voltage ramp, the total current supplied by the constant current circuit at this time is used for settling the amplifier transistor in the selected pixel circuit. Further, the current consumption in an output stage of the comparing circuit can be kept low, because of its small effect on the overall noise in the column readout circuit. As a result, the total electric losses of the column readout circuit can be reduced without affecting the SNR and chip area.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a simplified block diagram showing an image sensor array of a solid-state imaging that includes column processing units with comparing circuits according to an embodiment of the present technology.

FIG. 2 is a simplified circuit diagram showing a basic configuration of a data signal line and a column processing unit with a comparing circuit according to an embodiment.

FIG. 3 A is a simplified circuit diagram showing a basic configuration of a comparing circuit with an auxiliary switch for autozeroing the comparing circuit according to an embodiment.

FIG. 3B is a simplified time diagram illustrating a pixel output signal and control signals applied to the pixel circuit and the comparing circuit of FIG. 3 A in combination with a voltage ramp signal including a voltage ramp with positive slope.

FIG. 4 is a simplified circuit diagram showing a basic configuration of a comparing circuit with a voltage level converting circuit as output stage according to an embodiment.

FIG. 5A to 5E are simplified time diagrams illustrating a pixel output signal and control signals applied to the pixel circuit and the comparing circuit of FIG. 5.

FIG. 6 is a simplified circuit diagram showing a basic configuration of a comparing circuit with a booster circuit for shifting up the voltage ramp signal according to an embodiment. FIG. 7 is a simplified circuit diagram showing a column readout circuit that includes a plurality of comparing circuits according to an embodiment.

FIG. 8 is a schematic circuit diagram of elements of an image sensor array formed on a second chip of a solid-state imaging device with laminated structure according to an embodiment.

FIG. 9 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

FIG. 10 is a diagram of assistance in explaining an example of installation positions of an outside -vehicle information detecting section and an imaging section of the vehicle control system of FIG. 9.

DETAILED DESCRIPTION

Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various numerical values and the like in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may be electrically connected or signal-connected through resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g. FETs (field effect transistors), transmission gates, and others. The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a FET controls by field effect the current flow in the load path between source and drain.

Though in the following a technology for reducing power consumption is described in the context of certain types of image sensors for intensity readout, the technology may also be used for other types of image sensors.

FIG. 1 illustrates a configuration example of a solid-state imaging device 90 including an image sensor assembly 10 and a signal processing unit 80 according to an embodiment of the present technology.

The image sensor assembly 10 may include a pixel array unit 11, a row decoder 12, a pixel driver unit 13, a column signal processing unit 14, and a sensor controller 15.

The pixel array unit 11 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensors for intensity readout. In the illustrated embodiment, each pixel circuit 100 includes one photoelectric conversion device PD and four FETs for controlling the output signal of the pixel circuit 100. Other embodiments may refer to pixel circuits 100 with more or with less FETs, and with pixel circuits 100 with two or more photoelectric conversion devices PD. The photoelectric conversion devices PD of the pixel array unit 11 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column of photoelectric conversion devices PD may form a pixel column 31-1, 31-N. A subset of pixel circuits 100 assigned to the same row of photoelectric conversion devices PD may form a pixel row 32-1, ..., 32-M.

The row decoder 12 and the pixel driver unit 13 control driving of each pixel circuit 100 or each pixel row 31-1, ... , 32-M disposed in the pixel array unit 11. In particular, the row decoder 12 may supply control signals for selecting the pixel circuits 100 of a selected pixel row 31-1, ... , 32-M to the pixel driver unit 13 according to an address latch signal from the sensor controller 15. The pixel driver unit 13 may control the FETs of the selected pixel row 32-1, 32-M according to driver timing signals supplied from the sensor controller 15 and the control signals supplied from the row decoder 12.

The output signals of the pixel circuits 100 of the same pixel column 31-1, ..., 31-N are successively supplied to a data signal line (vertical signal line) VSL. The data signal lines VSL pass the output signals of the pixel circuits 100 (pixel output signals) to the column signal processing unit 14.

In particular, the solid-state imaging device 90 includes pixel circuits 100 arranged in pixel columns 31-1, ... , 31-N, wherein each pixel column 31-1, ... , 31-N is assigned to one data signal line VSL and wherein the signal outputs of the pixel circuits 100 of the same pixel column 31-1, ..., 31-N are connected to the same data signal line VSL.

The column signal processing unit 14 may include one or more ADC (analog-to-digital converter) units 20. The column signal processing unit 14 may include as much ADC units 20 as the pixel array unit 11 includes data signal lines VSL. Alternatively, the number of ADC units 20 may be lower than the number of data signal lines VSL and each ADC unit 20 may be multiplexed between two or more of the data signal lines VSL. Each ADC unit 20 performs analog-to-digital conversion of the pixel output signals Vout successively passed from the pixel column 31-1, ..., 31-N into digital pixel values and passes digital column pixel data to a readout buffer 290. The readout buffer 290 passes the digital column pixel data received form the ADC units 20 to the signal processing unit 80.

The sensor controller 15 controls the components of the image sensor assembly 10. For example, the sensor controller 15 may generate address latch signals to control the row decoder 12, may generate driving timing signals to control the pixel driver unit 13, and may generate readout control signals to control the column signal processing unit 14.

In each pixel circuit 100, the photoelectric conversion device PD photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion device PD corresponds to the intensity of the incident electromagnetic radiation. For example, the photoelectric conversion device PD may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation. In addition to the photoelectric conversion device PD, the illustrated configuration example of the pixel circuit 100 includes a floating diffusion region FD for storing charge supplied from photoelectric conversion device PD, a transfer transistor 101, a reset transistor 102, an amplification transistor 103, and a selection transistor 109. Each of the transistors is or includes an FET.

A load path of the transfer transistor 101 is electrically connected between the cathode of the photoelectric conversion device PD and the floating diffusion region FD. The transfer transistor 101 serves as transfer element for transferring charge from the photoelectric conversion device PD to the floating diffusion region FD. The floating diffusion region FD serves as temporary local charge storage. A transfer signal TG is supplied to the gate (transfer gate) of the transfer transistor 101 through a transfer control line. The transfer signal TG has an active signal level and an inactive signal level. In response to an active transfer signal TG, the transfer transistor 101 may transfer electrons photoelectrically converted by the photoelectric conversion device PD to the floating diffusion region FD.

A load path of the reset transistor 102 is electrically connected between a first positive voltage supply line to which a positive pixel supply voltage VDDP is supplied and the floating diffusion region FD. A reset signal RES is supplied to the gate of the reset transistor 102 through a reset control line. The reset signal RES has an active signal level and an inactive signal level. The reset transistor 102 serves as a reset element that resets a floating diffusion potential Vfd of the floating diffusion region FD. In particular, an active reset signal RES sets the floating diffusion potential Vfd equal or approximately equal to the positive pixel supply voltage VDDP.

In the following, the abbreviation “VDDP” marks both the first positive voltage supply node (first positive voltage supply line) and the positive pixel supply voltage supplied on the first positive voltage supply node. The abbreviation “VSSP” marks both the first negative voltage supply node (first negative voltage supply line) and the negative pixel supply voltage supplied through the first negative voltage supply node.

The floating diffusion region FD is connected to the gate of the amplification transistor 103 serving as an amplification element. The floating diffusion region FD functions as the input node of the amplification transistor 103.

The amplification transistor 103 and the selection transistor 109 are connected in series between the first power supply line for the positive pixel supply voltage VDDP and the data signal line VSL. Thus, the amplification transistor 103 is connected to the data signal line VSL through the selection transistor 109. A select signal SEL is supplied to the gate of the selection transistor 109 through a select control line. The select signal SEL has an active signal level and an inactive signal level.

An active select signal SEL turns on the selection transistor 109. When the selection transistor 109 is turned on, the amplification transistor 103 amplifies the floating diffusion potential Vfd of the floating diffusion region FD and outputs a voltage corresponding to the floating diffusion potential Vfd to the data signal line VSL. The data signal line VSL passes the pixel output signal Vout from the pixel circuit 100 to the column signal processing unit 14. Since the respective gates of the transfer transistor 101, the reset transistor 102, and the selection transistor 109 are connected in units of pixel rows 32-1, ..., 32-M, these operations can be simultaneously performed for each of the pixel circuits 100 of one pixel row 32-1, ..., 32-M.

Each data signal line VSL is further connected to a constant current circuit 210, wherein the constant current circuit 210 is electrically connected between the data signal line VSL and a power supply line for the negative pixel supply voltage VSSP. The constant current circuit 210 may include a constant current source or a switched capacitor current source supplying at least temporarily a constant current to the data signal line VSL, by way of example.

The amplification transistor 103 of the pixel circuit 100 and the constant current circuit 210 complement to a source follower circuit passing the pixel output signal Vout derived from the floating diffusion potential Vfd to the column signal processing unit 14.

The column signal processing unit 14 includes one or more ramp generators 220 for generating a voltage ramp signal Vrmp. For example, each ADC unit 20 may include a ramp generator 220. Alternatively, each ramp generator 220 may be shared by two or more ADC units 20. In the illustrated embodiment, a single ramp generator 220 supplies the same voltage ramp signal Vrmp to each of the ADC units 20.

Each ADC unit 20 includes a comparing circuit 230 that generates an active comparator output signal Vcout at a comparator output node 239 when a voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout exceeds a predefined threshold voltage.

In particular, the comparing circuit 230 may include a voltage-controlled switching element 231 with a load path electrically connected in series between a first power supply line or node, which supplies the positive pixel supply voltage VDDP, and the data signal line VSL. A capacitive element 251 may pass the voltage ramp signal Vrmp to a gate of the voltage-controlled switching element 231. A constant current source 232 may be electrically connected between the first power supply line, which supplies the positive pixel supply voltage VDDP, and the load path of the voltage-controlled switching element 231. The comparing circuit 230 outputs the comparator output signal Vcout at a comparator output node 239 between the constant current source 232 and the voltage-controlled switching element 231. A first auxiliary switch 233 may connect the gate of the voltage-controlled switching element 231 and the comparator output node 239 when an autozero signal AZ is active. The comparing circuit 230 generates an active comparator output signal Vcout at the comparator output node 239 when a voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout exceeds the gate threshold voltage of the voltage-controlled switching element 231.

The image sensor array may further include a counter circuit 280 that counts clock pulses and that may be stopped by a signal derived from the active comparator output signal Vcout.

In particular, each ADC unit 20 may include a counter circuit 280. The counter circuit 280 counts clock pulses that occur at regular intervals in a counting period between the start of a voltage ramp in the voltage ramp signal Vrmp and the start of the active comparator signal. The count value at the end of the counting period gives the result of the analog-to-digital conversion performed by the ADC unit 20 and defines the digital pixel value for the pixel output signal Vout on the data signal line VSL.

The sensor controller 15 controls the ramp generator circuit 220 and the counter circuit 280. In particular, the sensor controller 15 may synchronize the counting in the counter circuit 280 with the voltage ramp of the voltage ramp signal Vrmp generated in the ramp generator circuit 220. In addition, the sensor controller 15 may generate the active autozero signal AZ in a predefined temporal relationship with the start of the voltage ramp.

In the solid-state imaging device 90 as illustrated in FIG. 1, a readout of one pixel circuit 100 typically includes two periods: In a first period, a first pixel output signal (data signal) is read out directly after illumination of the pixel and converted into a digital pixel value (pixel data value) by AD (analog-to-digital) conversion. In a second period, a second pixel output signal (noise signal) of the non-illuminated pixel is read out and converted into a digital pixel value (pixel noise value). The second period may directly precede or may directly follow the first period. The final pixel output value is obtained by subtracting the pixel noise value from the pixel data value, wherein noise effects on the final pixel output value can be reduced.

The noise signal corresponds to the voltage of the floating diffusion FD immediately after an active reset signal turns on the reset transistor and connects the floating diffusion FD to the positive pixel supply voltage VDDP.

For the AD conversion of the noise signal, the comparator of the AD converter compares the voltage ramp signal with the noise signal in a P (preset) phase. For the AD conversion of the data signal, the comparator compares the voltage ramp signal with the data signal in a D phase.

According to a CDS (correlated double sampling) readout method, the P phase precedes the D phase. In a DDS (double data sampling) readout method, the D phase precedes the P phase.

FIG 2 shows a pixel circuit 100 and a comparing circuit 230 of an image sensor array. The pixel circuit 100 includes an amplification transistor 103 and a selection transistor 109 electrically connected in series between a first positive voltage supply node VDDP and a data signal line VSL. The pixel circuit 100 outputs a pixel output signal Vout on the data signal line VSL. A constant current circuit 210 is electrically connected between the data signal line VSL and a first negative voltage supply node VSSP. A ramp generator 220 generates a voltage ramp signal Vrmp. The comparing circuit 230 includes a voltage-controlled switching element 231. The comparing circuit 230 generates an active comparator output signal Vcout at a comparator output node 239 when a voltage difference between the voltage ramp signal Vrmp and the pixel output signal exceeds a threshold voltage of the voltage-controlled switching element 231.

The pixel circuit 100 may be one of a plurality of identical pixel circuits 100 of a pixel column 31-1, ..., 31-N, wherein the selection transistors 109 of all pixel circuits 100 assigned to the same pixel column 31-1, ... , 31-N are connected to the same data signal line VSL as illustrated in FIG. 1. The threshold voltage is defined as the potential difference between a control input of the voltage-controlled switching element 231 and the pixel output voltage at which the voltage-controlled switching element turns on. The voltage ramp signal Vrmp may include linear positive voltage ramps for both the preset phase and the data phase.

The voltage-controlled switching element 231 may be an n channel FET (field effect transistor), wherein a source of the n channel field effect transistor and the data signal line VSL are electrically connected. In particular, the voltage- controlled switching element 231 may an nMOSFET (n-channel metal oxide semiconductor FET) of the enhancement type and the threshold voltage is the nMOSFET gate threshold voltage.

A capacitive element 251 may pass the voltage ramp signal Vrmp output from the ramp generator 220 to the control input of the voltage-controlled switching element 231.

A controlled path of the voltage controlled switching element 231 is electrically connected in a network path in parallel with the series connected amplification transistor 103 and selection transistor 109.

A voltage level converting circuit 240 may convert the comparator output signal Vcout into a binary output signal Vbout and may output the binary output signal Vbout at a converter output node 249.

The voltage level converting circuit 240 may include elements supplied by a second voltage supply connected between a second positive voltage supply node VDDL and a second negative voltage supply node VSSL. The potential difference between the second positive voltage supply node VDDL and the second negative voltage supply node VSSL may be lower than between the first positive voltage supply node VDDP and the first negative voltage supply node VSSP.

In the following, the abbreviation “VDDL” marks both the second positive voltage supply node (second positive voltage supply line) and the positive logic supply voltage supplied on the second positive voltage supply node. The abbreviation “VSSL” marks both the second negative voltage supply node (second negative voltage supply line) and the negative logic supply voltage supplied through the second negative voltage supply node.

In particular, an input of the voltage level converting circuit 240 is connected to the comparator output node 239. The voltage level converting circuit 240 receives the comparator output signal Vcout and transforms the received comparator output signal Vcout into a binary output Vbout with a lower voltage swing than the comparator output signal Vcout.

As a result, the current supplied from the constant current circuit 210 is divided between a first branch that includes a network path through a selected one of the pixel circuits 100 and a second branch that includes the controlled path of the voltage-controlled switching element 231. Since the voltage-controlled switching element 231 is off at the beginning of the counting period, the total current supplied by the constant current circuit 210 can contribute to the settling of the amplifier transistor 103 in the selected pixel circuit 100 such that settling is maximized. On the other hand, the current consumption in an output stage of the comparing circuit 230, e.g. in the voltage level converting circuit 240, can be kept low, because of its small effect on the overall noise of the column signal processing unit 14 (column readout circuit). In this way, the total electric losses of the column signal processing unit 14 can be reduced without affecting the SNR. FIG. 3A shows an embodiment of the pixel circuit 100 with a floating diffusion region FD for storing charge supplied from a photoelectric conversion device PD, a transfer transistor 101, a reset transistor 102, an amplification transistor 103, and a selection transistor 109 as described above with reference to FIG. 1. In principle, the pixel circuit 100 may be any type of pixel circuit 100 for intensity readout, such as a high dynamic range pixel circuit including two photoelectric conversion devices PD, wherein radiation receiving areas of the two photoelectric conversion devices PD differ in size.

The comparing circuit 230 further includes a first auxiliary switch 233 that temporarily short-circuits a control input of the voltage-controlled switching element 231 and the comparator output node 239. In particular, the first auxiliary switch 233 may electrically connect the gate of an nMOSFET used as voltage-controlled switching element 231 and the comparator output node 239 through a low-resistive path in response to an active autozero signal AZ. The autozero signal AZ resets the voltage at the control input of the voltage-controlled switching element 231 and on the data signal line VSL to a predefined level.

FIG. 3B shows a pixel output signal Vout and control signals of the image sensor array of FIG. 3 A when the image sensor array is controlled for CDS correlated double sampling.

In or prior to an autozero phase Tl, an active reset signal RES may reset the pixel circuit 100, wherein the floating diffusion potential Vfd is set to a predefined potential that approximates the positive pixel supply voltage VDDP. Since the voltage gain of a source follower is approximately +1, the comparatively high floating diffusion potential Vfd results in a pixel output signal Vout with comparatively high preset voltage level Vpreset. A short active autozero signal AZ resets both the potential at the control input of the voltage-controlled switching device 231 and the comparator output signal Vcout to a reset potential.

In a preset-off phase T2, the voltage ramp signal Vrmp changes to a first initial voltage level VS1. For the comparatively high preset voltage level Vpreset on the data signal line VSL and the comparatively low first initial voltage level VS1, the voltage difference between the voltage ramp signal Vrmp and the preset voltage level is lower than the threshold voltage of the voltage-controlled switching element 231 and the voltage-controlled switching element 231 is off. The start of a voltage ramp with positive slope in the voltage ramp signal Vrmp starts the preset phase T3 and, simultaneously the counting period. At a certain point in time in the preset phase T3, the voltage difference between the voltage ramp signal Vrmp and the preset voltage level Vpreset exceeds the threshold voltage of the voltage-controlled switching element 231 and the voltage-controlled switching element 231 turns on resulting in a voltage drop in the comparator output signal Vcout.

In a data-off phase T4 the voltage ramp signal Vrmp changes to a second initial voltage level VS2, which is lower than the first initial voltage level VS1, wherein a voltage difference between the first initial voltage level VS1 and the second initial voltage level VS2 is greater than the maximum voltage span of the data signal. The voltage- controlled switching element 231 turns off. An active transfer signal TG turns on the transfer transistor 101 such that the photocurrent discharges the pre-charged floating diffusion FD to a degree given by the received illumination intensity. The lower floating diffusion potential Vfd results in a data voltage level Vdata of the pixel output signal Vout, wherein the data voltage level Vdata is the lower, the lower the floating diffusion potential Vfd and the higher the illumination intensity are. The start of a voltage ramp with positive slope in the voltage ramp signal Vrmp starts the data phase T5 and, simultaneously the counting period. At a certain point in time in the data phase T5, the voltage difference between the voltage ramp signal Vrmp and the data voltage level Vdata exceeds the threshold voltage of the voltage-controlled switching element 231 and the voltage-controlled switching element 231 turns on resulting in a voltage drop in the comparator output signal Vcout.

FIG. 4 shows a constant current source 232 electrically connected between the first positive voltage supply node VDDP and the controlled current path of the voltage-controlled switching element 231.

The constant current source 232 supplies a constant current to the network path that includes the load path of the voltage-controlled switching element 231. The constant current source 232 may include a pull-up element such as a resistor or a pMOSFET (p-channel MOSFET) whose gate is biased with a constant bias voltage.

The comparator output node 239 is between the constant current source 232 and the voltage-controlled switching element 231. An auxiliary capacitive element 238 may be connected between the comparator output node 239 and the first negative voltage supply node VSSP.

The constant current source 232 may supply a comparatively low constant current determined by noise and settling requirements, wherein the lower the current the higher the noise.

For example, the constant current source 232 may supply a comparatively low constant current of at most 20% of a constant current supplied by the constant current circuit 210.

The voltage level converting circuit 240 includes a second voltage-controlled switching element 241 controllable by the comparator output signal Vcout. The second voltage-controlled switching element 241 may be in a common source configuration providing a comparatively large voltage gain, wherein a load path of the second voltage- controlled switching element 241 is electrically connected between a second positive voltage supply line VDDL and a load element 242 connected to a second negative voltage supply line VSSL. The the voltage level converting circuit 240 may include the second voltage-controlled switching element 241 in a configuration with the voltage- controlled switching element 241 realized as pMOSFET as illustrated or as nMOSFET.

The second voltage-controlled switching element 241 may be a p channel field effect transistor.

A capacitive element 244 may electrically couple the comparator output signal Vcout to a control input of the second voltage-controlled switching element 241.

A controlled path of the second voltage-controlled switching element 241 and a load element 242 may be electrically connected in series between a second positive voltage supply line VDDL and a second negative voltage supply line VSSL, wherein the level converter output node 249 is between the second voltage-controlled switching element 241 and the load element 242. The voltage level converting circuit 240 provides a binary output signal Vbout at the level converter output node 249. The load element 242 may be a further constant current source 242. The further constant current source 242 may supply a comparatively low constant current to reduce power consumption. For example, the constant current may be lower than 500nA, e.g. about lOOnA.

A second auxiliary switch 243 may temporarily short-circuit the control input of the second voltage-controlled switching element 241 and the level converter output node 249. In particular, the second auxiliary switch 243 may electrically connect the gate of the second voltage-controlled switching element 241 and the level converter output node 249 through a low-resistive path in response to the active autozero signal AZ. The autozero signal AZ resets the voltage at the control input of the second voltage-controlled switching element 241 to a predefined level.

A power supply part of the image sensor array may generate a first supply voltage between the first positive voltage supply node VDDP and the first negative voltage supply node VSSP, and a second supply voltage between the second positive voltage supply node VDDL and the second negative voltage supply node VSSL, wherein the second supply voltage is lower than the first supply voltage. The second supply voltage may provide the supply voltage for digital circuits of the image sensor assembly 10 shown in FIG. 1, e.g. the counter circuit 280.

FIG: 5A to FIG. 5E show various output signals of the pixel circuit 100, the comparing circuit 230, and the voltage level converting circuit shown in FIG. 4 as part of an image sensor array operated in a CDS mode that uses a voltage ramp with positive voltage slope for analog-to-digital conversion. For simplicity it is assumed that the select signal SEL for the pixel circuit 100 is permanently active in the illustrated time periods. The various output signals are shown for different illumination conditions, wherein the arrows indicate the direction of increasing illumination intensity. In the CDS mode, a preset pixel signal of the non-illuminated pixel circuit (i.e., the pixel circuit’s voltage after it is reset) is obtained in a preset phase and a pixel data signal of the same pixel circuit when illuminated is obtained in a data phase. Then the preset pixel signal is subtracted from the pixel data signal to cancel kTC noise, which is the thermal noise associated with the total capacitance connected to the gate of the amplification transistor 103 and the total capacitance connected to the gate of the voltage-controlled switching element 231.

The total capacitance connected to the gate of the amplification transistor 103 includes the floating diffusion FD. The total capacitance connected to the gate of the voltage-controlled switching element 231 includes the capacitive element 251.

FIG. 5 A shows the floating diffusion potential Vfd of the floating diffusion FD for different illumination conditions. An active reset signal prior to t=tO turns on the reset transistor and sets the voltage level of the floating diffusion potential Vfd to a reset level that approximates the positive pixel supply voltage VDDP, which may be about 1.8V in the illustrated example. Autozero phase, preset-off phase and preset phase for determining a preset voltage follow after t=tO. At t=t41 an active transfer signal turns on the transfer transistor that connects the cathode of the photoelectric conversion device PD with the floating diffusion FD. The photocurrent of the photoelectric conversion device PD discharges the floating diffusion FD and the floating diffusion potential Vfd decreases the more the higher the photocurrent and thus the received radiation intensity are. At t=t42 the floating diffusion potential Vfd reaches its final value for the current exposure. Since the voltage gain of a source follower is approximately +1, the lower the floating diffusion potential Vfd is, the lower the voltage level at the pixel output node 139.

FIG. 5B shows the pixel output signal Vout for different illumination conditions. The pixel output signal Vout reaches its final value at t=t43. A large parasitic capacitance of the data signal line VSL can cause t43 to depend on the voltage level of the pixel output signal Vout as illustrated. The voltage level of the pixel output signal Vout is lower the higher the illumination intensity.

FIG. 5C shows the voltage ramp signal Vrmp. The voltage level VA of the voltage ramp signal Vrmp immediately after t=0 may be set by the ramp generator 220 and may be higher than the sum of first initial voltage level VS1 and the maximum data signal level. To enable a voltage ramp with sufficiently wide voltage span, the voltage ramp signal Vrmp is lowered to a first initial voltage level VS1 at the beginning of the preset-off phase at t=tl. The voltage ramp for the preset phase starts at t=t2. Between t=t2 and t=t3, the voltage ramp signal Vrmp increases according to a linear ramp function and so does the voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout. At a certain point in time between t=t2 and t=t3, the voltage difference exceeds the threshold voltage of the voltage-controlled switching device 231 and the voltage-controlled switching device 231 turns on.

At t=t4 the voltage ramp signal Vrmp is lowered to a second initial voltage level VS2 at the start of the data-off phase prior to starting the voltage ramp for the data phase at t=t5. The second initial voltage level VS2 can be lower than the first initial voltage level VS 1 by at least the maximum data signal level. During the data-off phase between t=t4 and t=t5, the active transfer signal controls discharge of the floating diffusion FD by the photocurrent. The length of the data-off phase phase between t=t4 and t=t5 is given by the settling time of the pixel output signal Vout after the transfer signal becomes active. At the start of the data phase at t=t5 the voltage ramp starts increasing from the second initial voltage level VS2 and reaches the end value VE at the end of the data phase at t=t6. At a certain point in time between t=t5 and t=t6, the voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout exceeds the threshold voltage of the voltage-controlled switching device 231 and the voltage- controlled switching device 231 turns on.

FIG. 5D shows the comparator output signal Vcout, which is reset to a maximum on-voltage Vcon2 directly after the autozero period at t=t01, wherein the maximum on-voltage Vcon2 results from the voltage level on the data signal line VSL and the gate-to-source voltage VGS of the voltage-controlled switching element 231. With the start of the preset-off phase at t=tl, the voltage ramp signal Vrmp goes low and the voltage difference between the voltage at the control input (gate voltage) and the data signal line VSL is below the threshold voltage of the voltage- controlled switching element 231. The voltage-controlled switching element 231 turns off and the pulled-up comparator output signal Vcout on the comparator output node 239 reaches a high off-level close to the maximum on-voltage Vcon2. The comparator output signal Vcout returns to a level close to the maximum on-voltage Vcon2, when at t=t21 the voltage ramp signal Vrmp reaches a level sufficiently high such that the voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout exceeds the threshold voltage of the voltage- controlled switching device 231 and the voltage-controlled switching device 231 turns on.

With the start of the data-off phase at t=t4, the voltage ramp signal Vrmp again goes low such that the voltage difference between the voltage level at the control input (gate voltage) and the voltage level of the data signal line VSL falls below the threshold voltage of the voltage-controlled switching element 231. The voltage-controlled switching element 231 turns off again and the pulled-up comparator output signal Vcout on the comparator output node 239 reaches the off-level Vcoff. The comparator output signal Vcout changes again when after t=t5 the voltage ramp signal Vrmp reaches a level sufficiently high such that the voltage difference between the voltage ramp signal Vrmp and the pixel output signal Vout exceeds the threshold voltage of the voltage-controlled switching device 231 and the voltage-controlled switching device turns on. The time at which the voltage-controlled switching element 231 turns on depends on the voltage level of the pixel output signal Vout and is the earlier the lower the voltage level of the pixel output signal Vout.

For high illumination intensity, the voltage level of the pixel output signal Vout is comparatively low and the voltage-controlled switching element 231 switches comparatively early at t=t51. For low illumination intensity, the voltage level of the pixel output signal Vout is high and the voltage-controlled switching element 231 switches later at t=t55.

FIG. 5D shows further that the comparator output signal Vcout is no binary signal but that after the voltage- controlled switching element 231 has turned on in the data phase, the voltage level of the comparator output signal Vcout depends on the voltage level of the pixel output signal Vout, wherein the voltage level of the comparator output signal Vcout is the lower, the lower the voltage level of the pixel output signal Vout. More particularly, after the voltage-controlled switching element 231 has turned on in the data phase, the voltage level of the comparator output signal Vcout is in a rage from a minimum on-state voltage Vconl to a maximum on-state voltage Vcon2.

FIG. 5E shows the binary output signal Vbout of the voltage level converting circuit 240 in FIG. 4. The binary output signal Vbout follows the turn-ons and turn-offs of the voltage-controlled switching element 231. In particular, the voltage level of the binary output signal Vbout goes to a low level when at t=tl and t=t4 the voltage- controlled switching element 231 turns off, and the voltage level of the binary output signal Vbout goes to a high level when at t=t21 and t=t51, t=t55 the voltage-controlled switching element 231 turns on. The voltage swing of the binary output signal Vbout is equal to the voltage swing in the digital domain that includes, inter alia, the counter circuit 280 and may be significantly lower than the maximum voltage swing of the comparator output signal Vcout.

FIG. 6 shows a booster circuit 250 in the gate line of the first voltage-controlled switching element 231. The booster circuit 250 shifts up the voltage ramp signal Vrmp received from the ramp generator 200 and supplies an up-shifted voltage ramp signal Vrmp to a control input of the voltage-controlled switching element 231.

The booster circuit 250 may provide an additional degree of freedom in selecting the voltage levels used for the voltage ramp and the threshold voltage. For example, if the voltage level on the data signal line VSL is comparatively high during the reset phase, a resulting comparatively high binary output signal Vbout during the autozero phase may result in that the constant current source 232 saturates.

FIG. 7 shows an image sensor array that includes a plurality of pixel columns 31-1, ... , 31-N.

Each pixel column 31-1, ..., 31-N of the image sensor array includes a plurality of pixel circuits 100, wherein each pixel circuit 100 includes an amplification transistor 103 and a selection transistor 109 electrically connected in series between the first positive voltage supply node VDDP and the data signal line VSL.

A data signal line VSL electrically connects the selection transistors 109 of the pixel circuits 100 of one pixel column 31-1, ..., 31-N with a constant current circuit 210 and a comparing circuit 230. FIG. 8 is a perspective view showing an example of a laminated structure of a solid-state imaging device 23020 with a plurality of pixel circuits arranged matrix-like in array form. Each pixel circuit includes at least one photoelectric conversion element.

The solid-state imaging device 23020 has the laminated structure of a first chip (upper chip) 910 and a second chip (lower chip) 920. The laminated first and second chips 910, 920 may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip 910. The solid-state imaging device 23020 may be formed to have the laminated structure in such a manner that the first and second chips 910 and 920 are bonded together at wafer level and cut out by dicing.

In the laminated structure of the upper and lower two chips, the first chip 910 may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, e.g., the photoelectric conversion devices arranged in array form.

For example, the first chip 910 may include only the photoelectric conversion devices of the pixel circuits as described above with reference to the preceding figures. Alternatively, the first chip 910 may include further elements of each pixel circuit. For example, the first chip 910 may include, in addition to the photoelectric conversion elements, at least the transfer transistor, the reset transistor, the amplification transistor, and/or the selection transistor of the pixel circuits. Alternatively, the first chip 910 may include each element of the pixel circuit. In addition to the elements of the pixel circuits, the first chip 910 may include one, some or all elements of the column signal processing unit, e.g., some or all elements of the ramp generator, the constant current circuit and/or the comparing circuit as described above.

The second chip 920 may be mainly a logic chip (digital chip) that includes the elements complementing the elements on the first chip 910 to complete pixel circuits and/or the column signal processing unit. The second chip 920 may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip 910 through the TCVs. For example, the second chip 920 may include all or at least some of the components of the comparing circuit as described with reference to the preceding Figures.

The second chip 920 may have one or more bonding pads BPD and the first chip 910 may have openings OPN for use in wire-bonding to the second chip 920. The solid-state imaging device 23020 with the laminated structure of the two chips 910, 920 may have the following characteristic configuration:

The electrical connection between the first chip 910 and the second chip 920 is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four comers of the solid-state imaging device 23020, by which a signal wiring area of the first chip 910 can be reduced.

The technology according to the present disclosure may be realized in a light receiving device mounted in a mobile body of any type such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, or robot. FIG. 9 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 9, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound/image output section 12052, and a vehicle-mounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside -vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section 12031 may be or may include an image sensor that includes a column signal processing unit with a comparing circuit according to the embodiments of the present disclosure. The light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include a solid-state imaging device with a raw driver assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-state imaging device and that is focused on the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside -vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside -vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

The sound/image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 9, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display, wherein each of them may include a solid-state imaging device with a comparing circuit as described with reference to the preceding Figures.

FIG. 10 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12109, and 12105.

The imaging sections 12101, 12102, 12103, 12109, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12109 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, FIG. 10 depicts an example of photographing ranges of the imaging sections 12101 to 12109. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12109 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12109, for example.

At least one of the imaging sections 12101 to 12109 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12109 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including a high dynamic range image sensor that includes an ADC unit with a comparing circuit according to the present disclosure.

For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12109, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12109, extract the classified three-dimensional object data, and use the extracted three- dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision. At least one of the imaging sections 12101 to 12109 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12109. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12109 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12109, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor that includes an ADC unit with a comparing circuit according to the present disclosure, power consumption can be further reduced.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

A solid-state imaging device including an image sensor array that includes ADC units with a comparing circuit according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in- vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light. In the field of security, the solid-state imaging device can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, the solid-state imaging device can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, the solid-state imaging device can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

The present technology can also be configured as described below:

(1) An image sensor array, including: a pixel circuit including an amplification transistor and a selection transistor electrically connected in series between a first positive voltage supply node and a data signal line and configured to output a pixel output signal on the data signal line; a constant current circuit electrically connected between the data signal line and a first negative voltage supply node; a ramp generator configured to generate a voltage ramp signal; and a comparing circuit including a voltage-controlled switching element, the comparing circuit configured to generate an active comparator output signal at a comparator output node when a voltage difference between the voltage ramp signal and the pixel output signal exceeds a threshold voltage of the voltage-controlled switching element.

(2) The image sensor array according to (1), wherein the voltage-controlled switching element is an n channel field effect transistor, and wherein a source of the n channel field effect transistor and the data signal line are electrically connected.

(3) The image sensor array according to any of (1) and (2), wherein a controlled path of the voltage controlled switching element is in a network path electrically connected in parallel to the series connected amplification transistor and selection transistor.

(4)The image sensor array according to claim (3), further including a constant current source electrically connected between the first positive voltage supply node and the controlled current path of the voltage-controlled switching element, wherein the comparator output node is between the constant current source and the voltage-controlled switching element.

(5) The image sensor array according to (4), wherein the constant current source is configured to supply a constant current of at most 20% of a constant current supplied by the constant current circuit.

(6) The image sensor array according to any of (1) to (5), further including a first auxiliary switch configured to temporarily short-circuit a control input of the voltage-controlled switching element and the comparator output node.

(7) The image sensor array according to any of (1) to (6), further including a voltage level converting circuit configured to convert the comparator output signal into a binary output signal and to output the binary output signal at a converter output node. (8) The image sensor array according to (7), wherein the voltage level converting circuit includes a second voltage- controlled switching element controllable by the comparator output signal.

(9) The image sensor array according to (8), further including a second auxiliary switch configured to temporarily short-circuit a control input of the second voltage-controlled switching element and the level converter output node.

(10) The image sensor array according to any of (8) and (9), wherein the second voltage-controlled switching element is a p channel field effect transistor.

(11) The image sensor array according to any of (8) to (10), wherein a controlled path of the second voltage- controlled switching element and a load element are electrically connected in series between a second positive voltage supply node and a second negative voltage supply node, and wherein the level converter output node is between the second voltage-controlled switching element and the load element.

(12) The image sensor array according to (11), further including a power supply part configured to generate a first supply voltage between the first positive voltage supply node and the first negative voltage supply node, and a second supply voltage between the second positive voltage supply node and the second negative voltage supply node, the second supply voltage being lower than the first supply voltage.

(13) The image sensor array according to any of (1) to (12), further including a booster circuit configured to shift up the voltage ramp signal and to supply a shifted high voltage ramp signal to a control input of the voltage-controlled switching element.

(14) The image sensor array according to any of (1) to (13), including a plurality of pixel circuits, wherein each pixel circuit includes an amplification transistor and a selection transistor electrically connected in series between the first positive voltage supply node and the data signal line.

(15) The image sensor array according to any of (1) to (14), further including a counter circuit configured to count clock pulses and to be stopped by a signal derived from the active comparator output signal.

Claims

CLAIMS An image sensor array, comprising: a pixel circuit (100) comprising an amplification transistor (103) and a selection transistor (104) electrically connected in series between a first positive voltage supply node (VDDP) and a data signal line (VSL) and configured to output a pixel output signal (VOUT) on the data signal line (VSL); a constant current circuit (210) electrically connected between the data signal line (VSL) and a first negative voltage supply node (VSSP); a ramp generator (220) configured to generate a voltage ramp signal (Vrmp); and a comparing circuit (230) comprising a voltage-controlled switching element (231), the comparing circuit (230) configured to generate an active comparator output signal (Vcout) at a comparator output node (239) when a voltage difference between the voltage ramp signal (Vrmp) and the pixel output signal (Vout) exceeds a threshold voltage of the voltage-controlled switching element (231). The image sensor array according to claim 1, wherein the voltage-controlled switching element (231) is an n channel field effect transistor, and wherein a source of the n channel field effect transistor and the data signal line (VSL) are electrically connected. The image sensor array according to claim 1, wherein a controlled path of the voltage controlled switching element (231) is in a network path electrically connected in parallel to the series connected amplification transistor (103) and selection transistor (104). The image sensor array according to claim 3, further comprising: a constant current source (232) electrically connected between the first positive voltage supply node (VDDP) and the controlled current path of the voltage-controlled switching element (231), wherein the comparator output node (239) is between the constant current source (232) and the voltage-controlled switching element (231). The image sensor array according to claim 4, wherein the constant current source (232) is configured to supply a constant current of at most 20% of a constant current supplied by the constant current circuit (210). The image sensor array according to claim 1, further comprising: a first auxiliary switch (233) configured to temporarily short-circuit a control input of the voltage-controlled switching element (231) and the comparator output node (239). The image sensor array according to claim 1, further comprising: a voltage level converting circuit (240) configured to convert the comparator output signal (Vcout) into a binary output signal (Vbout) and to output the binary output signal (Vbout) at a level converter output node (249). The image sensor array according to claim 7, wherein the voltage level converting circuit (240) comprises a second voltage-controlled switching element (241) controllable by the comparator output signal (Vcout). The image sensor array according to claim 8, further comprising: a second auxiliary switch (243) configured to temporarily short-circuit a control input of the second voltage- controlled switching element (241) and the level converter output node (249). The image sensor array according to claim 8, wherein the second voltage-controlled switching element (241) is a p channel field effect transistor. The image sensor array according to claim 8, wherein a controlled path of the second voltage-controlled switching element (241) and a load element (242) are electrically connected in series between a second positive voltage supply node (VDDL) and a second negative voltage supply node (VSSL), and wherein the level converter output node (249) is between the second voltage-controlled switching element (241) and the load element (242). The image sensor array according to claim 11, further comprising: a power supply part configured to generate a first supply voltage between the first positive voltage supply node (VDDP) and the first negative voltage supply node (VSSP), and a second supply voltage between the second positive voltage supply node (VDDL) and the second negative voltage supply node (VSSL), the second supply voltage being lower than the first supply voltage. The image sensor array according to claim 1, further comprising: a booster circuit (250) configured to shift up the voltage ramp signal (Vrmp) and to supply a shifted high voltage ramp signal to a control input of the voltage-controlled switching element (231). The image sensor array according to claim 1, comprising: a plurality of pixel circuits (100), wherein each pixel circuit (100) comprises an amplification transistor (103) and a selection transistor (109) electrically connected in series between the first positive voltage supply node (VDDP) and the data signal line (VSL). The image sensor array according to claim 1, further comprising: a counter circuit (280) configured to count clock pulses and to be stopped by a signal derived from the active comparator output signal (Vcout).