EP4427341A1

EP4427341A1 - Signal converter and arrangement with a signal converter

Info

Publication number: EP4427341A1
Application number: EP22812435.0A
Authority: EP
Inventors: Luc GONNET; Sebastien Ocquidant
Original assignee: Eaton Intelligent Power Ltd
Current assignee: Eaton Intelligent Power Ltd
Priority date: 2021-11-02
Filing date: 2022-11-02
Publication date: 2024-09-11
Also published as: WO2023078585A1

Abstract

A signal converter (11) comprises a converter input (12), a transformer (16) with a primary side (17) coupled to the converter input (12), a demodulator (20) comprising a filter (90), a comparator (86) and a demodulator output (21), and a converter output (25) coupled to the demodulator output (21). The filter (90) is coupled to a secondary side (18) of the transformer (16). An input side of the comparator (86) is coupled to the filter (90). A comparator output (100) of the comparator (86) is coupled to the demodulator output (21).

Description

DESCRIPTION

Signal converter and arrangement with a signal converter

The present disclosure is related to a signal converter and an arrangement with a signal converter .

The signal converter is configured to convert an input signal received at a converter input using a first protocol into an output signal at a converter output with a second protocol . A smart meter, such as the smart meter Linky often used in France , provides a data signal with a first protocol . Since the information gained by the smart meter is useful for at least another application in a building, the data signal provided by the smart meter has to be converted into an output signal or output signals which can be received by the other application in the building . The input signal of the signal converter may be disturbed by electromagnetic interference or noise received by a connection line that connects the smart meter to the signal converter .

It is an obj ect to provide a signal converter and an arrangement with a signal converter which reduces an influence of interferences while converting a signal .

These obj ects are achieved by the subj ect-matter of the independent claims . Further developments and embodiments are described in the dependent claims .

There is provided a signal converter, comprising a converter input , a trans former with a primary side coupled to the converter input , a demodulator with a demodulator output and a converter output coupled to the demodulator output . The demodulator comprises a filter and a comparator . The filter is coupled to a secondary side of the transformer. An input side of the comparator is coupled to the filter. A comparator output of the comparator is coupled to the demodulator output .

Advantageously, the transformer at the input side of the signal converter and the filter of the demodulator reduce an influence of electromagnetic interference or noise received at the converter input. Advantageously, there is no direct current coupling, abbreviated DC coupling, between the converter input and the demodulator, because the transformer is arranged between the converter input and the demodulator. Thus, a reference potential at a reference potential terminal of the signal converter can be different from a reference potential of a device or apparatus coupled to the converter input. Also the signal converter with the transformer at the converter input achieves a higher sensitivity than an optocoupler that requires e.g. at least 1V~1.2V minimal voltage to be functional. With transformer it can be achieved to use a supply voltage e.g. less than 0.8V, as required by a specification in this technical field.

In an embodiment, the signal converter is configured to receive an input signal at the converter input and to convert the input signal in a converter output signal that is provided at the converter output. The input signal is e.g. an amplitude modulated signal, an amplitude shift keying signal or an on-off-keying signal. The input signal is e.g. generated by digital amplitude modulation by a signal source that is not comprised by the signal converter. The signal source is e.g. a smart meter, such as the Linky smart meter.

In an embodiment of the signal converter, the transformer is realized as a current transformer. In an embodiment of the signal converter, a turn ratio R of the transformer is calculated according to the following equation :

NPRI Uprim Isec R NSEC Usee Iprim wherein NPRI is a number of turns of windings on the primary side of the transformer, NSEC is a number of turns of windings on the secondary side of the transformer; Uprim is a voltage on the primary side; Usee is a voltage on the secondary side; Iprim is a short circuit current on the primary side; and Isec is a short circuit current on the secondary side. In an example, the turn ratio R is less than 1.2. Alternatively, the turn ratio R is less than 1.1. Alternatively, the turn ratio R is less or equal than 1.0. In case of R>1, a transformer is implemented as step-up current transformer. In case of R<1, a transformer is implemented as step-down current transformer. In case of R=l, a transformer is implemented as isolation transformer. The transformer is designed such that e.g. its size is reduced to a minimum size and has an appropriate creepage distance, minimum magnetizing current and core characteristics. In an example, the number NPRI of turns on the primary side is zero; in this case the primary side is e.g. realized by a straight conducting line and the secondary side is realized by windings around the conducting line.

In an embodiment, the signal converter comprises an antiparallel circuit of diodes which are arranged between a first terminal of the secondary side of the transformer and a second terminal of the secondary side of the transformer.

In an embodiment of the signal converter, the anti-parallel circuit of diodes comprises a first and a second diode. The first and the second diode are implemented as Schottky diodes. Advantageously, the Schottky diodes have a very low voltage drop to have the smallest current transformer.

In an embodiment of the signal converter, the filter is implemented as a band-pass filter or high-pass filter.

In an embodiment of the signal converter, the demodulator comprises an edge detector which comprises an input side coupled to the comparator output and an output side coupled to the demodulator output. The input signal includes a signal carrier. The edge detector is implemented to detect a presence of the signal carrier.

In an example, more specifically, the input signal comprises a number of periods. In some periods of the number of periods, the input signal is realized by the signal carrier; the signal carrier is present in these periods; these periods represent a first logical value of the input signal. In the other periods of the number of periods, the input signal is free of the signal carrier; the signal carrier is absent; the input signal is approximately zero; these periods represent a second logical value of the input signal. The edge detector is configured to detect an edge of a period with a present signal carrier. A period can also be named cycle. The signal carrier is considered as present in the input signal if the peak amplitude is higher than a predetermined value, such as e.g. 0.8 V. The edge detector detects a presence of the signal carrier.

In an embodiment of the signal converter, the demodulator is configured to perform an envelope demodulation, e.g. an incoherent envelope demodulation. The demodulator is realized e.g. as an envelope detector. In an embodiment of the signal converter, the edge detector is configured to generate a demodulator output signal as a function of a comparator output signal of the comparator . A pulse duration of the demodulator output signal is longer than a pulse duration of the comparator output signal . The edge detector detects an edge of a pulse of the comparator output signal . The edge detector is configured to combine several pulses of the comparator output signal into one pulse of the demodulator output signal . Thus , the edge detector could also be called pulse former, pulse forming circuit , pulse combining circuit or envelope demodulator .

In an embodiment of the signal converter, the edge detector comprises at least one of a monostable multivibrator or a pulse generator . The edge detector is e . g . retriggerable .

In an embodiment , the signal converter comprises a microcontroller having an input coupled to the demodulator output and an output coupled to the converter output .

In an embodiment , the signal converter comprises a transceiver having an input coupled to the output of the microcontroller and an output coupled to the converter output . The transceiver is implemented e . g . as a RS485 transceiver .

In an embodiment , the signal converter includes a converter housing which is configured to be attached to a switchboard, for example to a rail of the switchboard .

There is provided an arrangement , comprising the signal converter and a smart meter coupled to the converter input . In an embodiment of the arrangement, the smart meter includes a housing. The signal converter is inserted into the housing of the smart meter.

In an example, the signal converter implements a demodulation circuit of an amplitude modulated signal (e.g. an on-off keying signal, abbreviated OOK) with high sensitivity at 9600 Bds to RS485 modbus protocol including a reinforced insulation. The application includes a demodulation of amplitude modulation "on off keying" (AM, 50 kHz, 50 %, 9600 Bds) signal with a very high sensitivity (0.8 V peak, abbreviated 0.8 P) . The signal converter provides a reinforced insulation. The signal converter transforms the previous signal to RS485 modbus protocol using a microcontroller or to modbus over RS485 using a microcontroller. The signal converter reaches a high sensitivity level to demodulate an OOK signal through a transformer galvanic insulation and demodulates a signal having 4.8 kHz (9600 Bds) .

In an example, the signal converter includes to design an electronic schematic connected to TIC protocol signal sink Linky counter. TIC is the abbreviation for telecommunication interface customer. The Linky smart meter or counter is distributed by Enedis, France. The TIC signal is of amplitude modulation type "on off key" (AM, 50 kHz, 50 % , 9600 Bds) . Reinforced insulation and high sensitivity are achieved by using a specific current transformer meeting the insulation distance and creepage distance in a very small volume. For demodulation, a comparator followed by a retriggerable monostable multivibrator with Schmitt-trigger inputs (e.g. the device 74 HC123 or the device SN 74LVC1G123) or a monostable pulse generator (one shot) is used (e.g. device TimerBlox: LTC 6993) . A microcontroller converts the previous signal into another protocol e . g . Modbus RS485 . The RS485 hardware interface is made using a transceiver dedicated ( e . g . the device LTC 2854 ) .

In an example , the signal converter is configured to interface an Xstorage residential product directly to a Linky counter and use the data from Linky smart electric meter customer tele-information . This interface avoids to add some current sensors outside Xstorage involved in wiring problems leading to customer issues .

In an example , the signal converter is configured as a gateway card .

The following description of figures of embodiments may further illustrate and explain aspects of the signal converter and the arrangement with the signal converter . Parts and devices with the same structure and the same ef fect , respectively, appear with equivalent reference symbols . In so far as parts or devices correspond to one another in terms of their function in di f ferent figures , the description thereof is not repeated for each of the following figures .

Figure 1 shows an example of an arrangement with a signal converter ;

Figures 2A to 2C show examples of details of a signal converter ;

Figure 3 shows an example of signals of a signal converter ; and Figures 4A and 4B show examples of an arrangement with a signal converter .

Figure 1 shows an example of an arrangement 10 with a signal converter 11 . In Figure 1 , a global view schematic is il lustrated . The signal converter 11 has a converter input 12 . The converter input 12 comprises a first and a second input terminal 13 , 14 . The signal converter 11 comprises a trans former 16 . A primary side 17 of the trans former 16 is coupled to the converter input 12 . Moreover, the signal converter 11 comprises a demodulator 20 . An input side of the demodulator 20 is coupled to a secondary side 18 of the trans former 16 . The signal converter 11 comprises a converter output 25 . A demodulator output 21 of the demodulator 20 is coupled to the converter output 25 .

Additionally, the signal converter 11 includes a microcontroller 22 having an input 23 coupled to the demodulator output 21 . An output 24 of the microcontroller 22 is coupled to the converter output 25 . The signal converter 11 comprises a transceiver 26 having an input coupled to the output 24 of the microcontroller 22 . An output of the transceiver 26 is coupled to the converter output 25 . Thus , the output 24 of the microcontroller 22 is coupled via the transceiver 26 to the converter output 25 . The transceiver 26 is e . g . implemented as RS485 transceiver or a ProfiBus transceiver . The demodulator output 21 is coupled via the microcontroller 22 and the transceiver 26 to the converter output 25 .

Additionally, the signal converter 11 comprises a power supply 41 that is coupled via a supply output 98 to di f ferent circuits of the signal converter 11 such as , for example , the demodulator 20 , the microcontroller 22 , the transceiver 26 and circuit parts coupled to the secondary side 18 of the transformer 16. Additionally, the signal converter 11 comprises a display 42 that is coupled to the microcontroller 22. The display 42 is implemented e.g. as a light-emitting diode. Furthermore, the signal converter 11 comprises a power supply indicator 43 that is coupled to the power supply 41. The power supply indicator 43 is implemented e.g. as a lightemitting diode.

The arrangement 10 further comprises a smart meter 50. The smart meter 50 is coupled on its output side to the converter input 12. Thus, a first output terminal 51 of the smart meter 50 is coupled to the first input terminal 13. A second output terminal 52 of the smart meter 50 is coupled to the second input terminal 14. The smart meter 50 includes e.g. further outputs. The further outputs realize e.g. data communication via a power line, not shown.

Additionally, the arrangement 10 comprises a device 55. The device 55 is coupled on its input side to the converter output 25. The device 55 is e.g. an energy storage device or an uninterruptible power supply, abbreviated UPS. The energy storage device is e.g. realized by an X Storage product provided by Eaton Corporation pic, Ireland.

The smart meter 50 provides an input signal SI that is applied via the converter input 12 to the primary side 17 of the transformer 16. The smart meter 50 is connected to the converter input 12 by the input signal SI. More specifically, the input signal SI is applied to the first input terminal 13. The smart meter 50 provides a further input signal S2 that is applied via the converter input 12 to the primary side 17 of the transformer 16. More specifically, the further input signal S2 is applied to the second input terminal 14.

For example, SI = - S2.

The input signal SI is realized as a telecommunication interface customer signal, abbreviated TIC signal. Thus, in an example, the TIC signal from the Linky smart meter is applied to the converter input 12. The TIC signal is generated using an "on off keying" protocol (amplitude modulated, abbreviated AM, frequency of the TIC signal is 50 kHz, a duty cycle is 50 %, 9600 Bds, 0.8 V peak to peak, abbreviated 0.8 V PR) . The input signal SI includes information about e.g. active power, reactive power, voltage and/or current measured by the smart meter 50.

The demodulator 20 generates a demodulator output signal SD as a function of the input signal SI. The demodulator output signal SD is provided at the demodulator output 21. The demodulator output signal SD is formed by the transformer 16 and the demodulator 20 as a function of the input signal SI.

A converter output signal SO is provided at the converter output 25. The converter output signal SO is a function of the demodulator output signal SD. The converter output signal SO is generated by the microcontroller 22 and the transceiver 26 depending on the demodulator output signal SD. The converter output signal SO is e.g. a RS485 signal. The converter output signal SO is a half-duplex signal. The converter output signal SO uses e.g. a Modbus protocol such as the Modbus Remote Terminal Unit protocol, abbreviated Modbus RTU protocol. The transceiver 26 performs a halfduplex communication. The microcontroller 22 and the transceiver 26 perform a data processing of a demodulator output signal SD into a converter output signal SO. The power supply 41 receives a voltage VS. In an example, the voltage VS is in a range between 5 V and 25 V. The power supply 41 generates a supply voltage VDD using the voltage VS. The supply voltage VDD is provided to the different circuit parts of the signal converter 11. The supply voltage VDD has e.g. a value of 3.3 V. The supply power indicator 43 indicates that the power supply 41 is correctly working. The power supply 41 generates the supply voltage VDD at the supply output 98.

The display 42 indicates that the input signal SI from the smart meter 50 is correct e.g. according to requests of Enedis .

In an alternative, not shown embodiment, another device is connected to the converter input 12.

In an alternative, not shown embodiment, the microcontroller 22 is coupled via a transmitter to the converter output 25. Thus, the transceiver 26 is replaced by a transmitter. The transmitter is implemented e.g. as RS 422 transmitter.

Figure 2A shows an example of details of a signal converter 11 which is a further development of the example shown in Figure 1. In Figure 2A, the electronic part providing galvanic isolation and a high sensitivity demodulation circuit is described. The galvanic isolation is achieved by the transformer 16. The signal converter 11 comprises a first socket 60 that includes the first and the second input terminal 13, 14. Moreover, the first socket 60 includes a third input terminal 61. Additionally, the signal converter 11 includes a second socket 62. A first input terminal 63 of the second socket 62 is connected to the third input terminal

61 of the first socket 60. A second input terminal 64 of the second socket 62 is connected to the second input terminal 14 of the first socket 60. A third input terminal 65 of the second socket 62 is connected to the first input terminal 13 of the first socket 60.

The first input terminal 13 is coupled to a first terminal 71 of the primary side 17 of the transformer 16. The second input terminal 14 is coupled to a second terminal 72 of the primary side 17 of the transformer 16. The signal converter 11 comprises a transformer capacitor 73 that couples the first input terminal 13 to the first terminal 71 of the primary side 17 of the transformer 16. A first transformer resistor 74 couples the second input terminal 14 to the second terminal 72 of the primary side 17 of the transformer 16. In an example, a second transformer resistor 75 is optionally connected in parallel to the first transformer resistor 74.

The signal converter 11 is free from any conducting connection of a terminal or node on the primary side 17 of the transformer 16 to a terminal or node at the secondary side 18 of the transformer 16. By construction, the transformer 16 provides a galvanic isolation (SELV) , high sensitivity and impedance matching e.g. according to Enedis specification requests. Inside the signal converter 11, the signals and the supply voltage VDD are realized as safety extra low voltages, abbreviated SELV. The impedance matching is performed by the transformer capacitor 73, the first transformer resistor 74, the optional second transformer resistor 75 and the primary side 17 of the transformer 16.

The signal converter 11 comprises an antiparallel circuit of diodes 80. The antiparallel circuit of diodes 80 includes a first diode 81 and a second diode 82. An anode of the first diode 81 is connected to a cathode of the second diode 82. A cathode of the first diode 81 is coupled or connected to an anode of the second diode 82. The anode of the first diode 81 is coupled to a first terminal 83 of the secondary side 18 of the transformer 16. The cathode of the first diode 81 is coupled to a second terminal 84 of the secondary side 18 of the transformer 16. A voltage between the first terminal 83 and the second terminal 84 of the secondary side 18 is kept low by the antiparallel circuit of diodes 80. Low means that the voltage between the first and the second terminal 83, 84 of the secondary side 18 is configured to be seen as low impedance from the current transformer 16 (similar at a short circuit) and to have a small sine signal when the signal carrier from the smart meter 50 is present. The first and the second diode 81, 82 are realized e.g. as Schottky diodes. Advantageously, Schottky diodes are suitable to decrease a secondary voltage on the secondary side 18 of the transformer 16, e.g. to reduce a magnetizing current and to make the transformer 16 smaller.

Moreover, the demodulator 20 comprises a comparator 86 having a first and a second input 87, 88. In an example, the first input 87 is realized as an inverting input and the second input 88 is realized as a non-inverting input. The first and the second input 87, 88 of the comparator 86 are coupled to the first and the second terminal 83, 84 of the secondary side 18 of the transformer 16 via a filter 90.

The filter 90 includes a high pass filter. The filter 90 comprises a first filter capacitor 91 that couples the second terminal 84 of the secondary side 18 of the transformer 16 to the first input 87 of the comparator 86. The first terminal 83 of the secondary side 18 is coupled via a first filter resistor 92 to the second terminal 84 of the secondary side 18 via the first filter capacitor 91 , to select a cutting frequency of the high pass filter . The first filter resistor 92 couples the first terminal 83 of the secondary side 18 to a node between the first filter capacitor 91 and the first input 87 of the comparator 86 . A second filter capacitor 93 couples the first terminal 83 of the secondary side 18 to a re ference potential terminal 94 . The first terminal 83 of the secondary side 18 is coupled via a second filter resistor 95 to the second input 88 of the comparator 86 . A third filter resistor 96 couples the second input 88 of the comparator 86 to the reference potential terminal 94 . A fourth filter resistor 97 couples the first terminal 83 of the secondary side 18 to the supply output 98 of the power supply 41 . The fourth filter resistor 97 generates a stable potential re ference from the supply voltage VDD at the supply output 98 for the signal from the secondary side 18 of the current trans former 16 . The fourth filter resistor 97 and the second fi lter capacitor 93 form a filter . The second, third and fourth filter resistor 95 , 96 , 97 generate a voltage re ference from the supply voltage VDD tapped at the supply output 98 . This voltage reference is applied to the second input 88 of the comparator 86 .

The output of the high pass filter made of the first filter capacitor 91 and the first filter resistor 92 is compared with this reference made by the supply voltage VDD and the second, third and fourth filter resistor 95 , 96 , 97 by the comparator 86 to detect the presence of the signal carrier in the input signal S I . I f the signal is higher than the re ference , a signal at a comparator output 100 is high, else low . Thus , the comparator 86 generates a train of pulses when the signal carrier is present in the input signal S I . The second filter resistor 95 introduces a hysteresis . The comparator 86 is reali zed e . g . as the device LMV331 of Texas Instruments , Texas , US . The comparator 86 detects a rising edge or a falling edge of a signal provided by the smart meter 50 . Whether the rising edge or the falling edge of the signal provided by the smart meter 50 is determined depends e . g . on which terminal of the smart meter 50 is connected to the first converter input 13 and which further terminal of the smart meter 50 is connected to the second input 14 .

The filter 90 implements a high pass . The filter 90 is configured such that a voltage at the second input 88 of the comparator 86 is nearly constant . A DC part of said voltage is determined by the value of the supply voltage VDD and the values of the third, fourth and fi fth filter resistor 95 to 97 . An AC part of said voltage is low due to the second fi lter capacitor 93 . Thus , the second input 88 of the comparator 86 receives a reference voltage . The first input 87 of the comparator 86 receives a signal generated by the secondary side 18 of the trans former 16 and filtered by the high pass filter of the filter 90 .

The comparator 86 has a supply input connected to the supply output 98 of the power supply 41 . A stabili zation capacitor 99 couples the supply output 98 to the reference potential terminal 94 . Moreover, the comparator 86 is connected to the re ference potential terminal 94 . A comparator resistor 101 optionally couples the comparator output 100 of the comparator 86 to the supply output 98 . The comparator resistor 101 is useful in case the comparator output 100 is reali zed e . g . according to an open drain or open connector style . The comparator 86 generates a comparator output signal SC at the comparator output 100 .

Moreover, the signal converter 11 comprises an edge detector

110 . The edge detector 110 is reali zed e . g . as an envelope detector . The edge detector 110 comprises a multivibrator 111 . The multivibrator 111 is implemented as a monostable multivibrator . The multivibrator 111 is fabricated as a retriggerable monostable multivibrator . In an example , the multivibrator 111 is implemented by the device 74HC123 of Texas Instruments , Texas , USA. This device includes a second multivibrator which is not used . The multivibrator 111 has an input 112 which is coupled to the comparator output 100 . A coupling resistor 113 is optionally arranged between the comparator output 100 and the first input 112 of the multivibrator 111 . The multivibrator 111 includes an output 114 that is connected to the demodulator output 21 . An output resistor 120 is optionally arranged between the output 114 of the multivibrator 111 and the demodulator output 21 .

A supply terminal of the multivibrator 111 is connected to the supply terminal 98 . A stabili zation capacitor 121 is connected to the supply terminal of the multivibrator 111 . A re ference terminal of the multivibrator 111 is connected to the reference potential terminal 94 . A control capacitor 115 couples a first control terminal 116 of the multivibrator 111 to a second control terminal 117 of the multivibrator 111 . A control resistor 118 couples the second control terminal 117 to the supply output 98 . A further control resistor 119 is optionally connected in parallel to the first control resistor 118 to improve accuracy . The multivibrator 111 has two further input terminals which are connected to the re ference potential terminal 94 or the supply output 98 .

The edge detector 110 generates the demodulator output signal SD . A pulse width TD of the demodulator output signal SD has a predetermined value . Since the multivibrator 111 is retriggerable , the pulse width TD of the demodulator output signal SD has a predetermined minimum value . The predetermined minimum value of the pulse width TD is calculated e . g . according to the following equation :

TD = k • RX • CX, wherein Cx is a capacitance value of the control capacitor 115 , Rx is a resistance value of the parallel circuit of the two control resistors 118 , 119 and k is a constant ( e . g . k=0 . 45 ) . Alternatively, the further control resistor 119 is omitted; in this case , Rx is a resistance value of the control resistor 118 . The pulse width TD is calculated to have a duration j ust above the delay between two pulses from the comparator output signal SC . The pulse width TD is set to have a duration longer than a distance between two pulses of the comparator output signal SC .

Advantageously, the first and the second socket 60 , 62 are used to connect the smart meter 50 to the signal converter 11 and additionally to another signal converter or any other device having the capability to get information from the smart meter 50 .

Since the galvanic isolation is achieved by the trans former 16 , the signal converter 11 is free of an opto-isolator ( also called optocoupler ) . An opto-isolator typically requires a high voltage for operation . Such a high voltage is avoided by the use of the trans former 16 .

In an alternative , not shown embodiment , at least a further diode is connected in series to the first diode 81 and at least an additional diode is connected in series to the second diode 82 . In case the number of diodes in series is increased, the current trans former 16 may be bigger due to a higher output voltage on the secondary side 18 of the trans former 16 .

In an alternative , not shown embodiment , the coupling resistor 113 is omitted and is replaced by a connection line .

In an alternative , not shown embodiment , the output resistor 120 is omitted and is replaced by a connection line .

In an alternative , not shown embodiment , the further control resistor 119 is omitted .

Figure 2B shows an example of details of a signal converter 11 which is a further development of the examples shown in Figures 1 and 2A. The edge detector 110 is reali zed as a pulse generator 130 . The pulse generator 130 is also implemented as a monostable multivibrator . The pulse generator 130 is implemented as a one-shot pulse generator . Thus , the pulse generator 130 can also be named "monostable pulse generator" . The pulse generator 130 is retriggerable . The pulse generator 130 has a programmable pulse width . In an example , the pulse generator 130 is reali zed as the device LTC6993 of Analog Devices , Inc . , USA.

The pulse generator 130 comprises an input 131 that is coupled or directly connected to the comparator output 100 . An output 132 of the pulse generator 130 is coupled or directly connected to the demodulator output 21 . The pulse generator 130 comprises a set terminal 134 that is reali zed as a pulse width setting input . The set terminal 134 is connected to the reference potential terminal 94 via a set resistor 135 . The voltage at the set terminal 134 is regulated e . g . to 1 V above ground potential GND that is tapped at the reference potential terminal 94 . An amount of current that flows through the set terminal 134 programs a master oscillator frequency of the pulse generator 130 . The set resistor 135 determines this current and thus determines the master oscillation frequency .

Moreover, the pulse generator 130 comprises a voltage divider 136 and a divider input 137 . The voltage divider 136 is coupled between the supply output 98 and the reference potential terminal 94 . A tap of the voltage divider 136 is connected to the divider input 137 . A voltage tapped at the divider input 137 is converted into a digital value by a not- shown analog-to-digital converter (which has e . g . a 4-bit resolution) of the pulse generator 130 . The voltage divider 136 includes a first and a second divider resistor 138 , 139 . The first divider resistor 138 couples the supply output 98 to the tap of the voltage divider 136 . The second divider resistor 139 couples the reference potential terminal 94 to the tap of the voltage divider 136 .

A signal at the output of the analog-to-digital converter programs a programmable frequency divider that is coupled between an output of the master oscillator and the output 132 of the pulse generator 130 . Thus , a pulse width TD of the demodulator output signal SD is a function of the resistance values of the resistors of the voltage divider 136 and of the set resistor 135 . The pulse width TD is calculated to have a duration j ust above the delay between two pulses from the comparator output signal SC . The pulse width TD is set to have a duration longer than a distance between two pulses of the comparator output signal SC .

Figure 2C shows a further example of details of a signal converter 11 which is a further development of the examples shown in Figures 1 , 2A and 2B . The comparator output 100 is directly connected to the demodulator output 21. The microcontroller 22, as shown in Figure 1, is configured to determine whether the demodulator output signal SD is a series of pulses or whether the demodulator output signal SD is free of a series of pulses. Thus, the microcontroller 22 includes a software or a firmware which combines pulses into a longer pulse in the case that a duration between two pulses in the output signal of the comparator is small. In Figure 2C, the demodulator output signal SD is e.g. equal or approximately equal to the comparator output signal SC. In an example, the coupling resistor 113 is optionally arranged between the comparator output 100 and the demodulator output 21.

Figure 3 shows an example of signals of a signal converter 11 as shown in Figures 1, 2A, 2B and 2C. The comparator output signal SC, the input signal SI and the demodulator output signal SD are shown as a function of a time t. As shown in Figure 3, in a first period A, the input signal SI includes a series of five sinewaves with different amplitudes which are converted by the transformer 16, the filter 90 and the comparator 86 to form four rectangular pulses included in the comparator output signal SC. The rectangular pulses of the comparator output signal SC are converted by the edge detector 110 as shown e.g. in Figures 2A and 2B into one pulse of the demodulator output signal SD. The pulse in the demodulator output signal SD represents a first logical value, for example the value 1. A pulse duration TD of the demodulator output signal SD is longer than a pulse duration TC of the comparator output signal SC. A period may be named cycle .

In a next period B, the input signal SI has approximately the value of 0 V. The input signal SI is e.g. a voltage signal. Thus, the comparator output signal SC and also the demodulator output signal SD are constant and have, for example, the value of 0 V. This state of the demodulator output signal SD represents a second logical value, for example 0.

In a third period C, the input signal SI includes about six sinewaves with different amplitudes. Thus, the comparator output signal SC provides five pulses. The edge detector 110 forms a single pulse out of the five pulses of the comparator output signal SC.

When the signal carrier is present in the input signal SI (e.g. with a value or an amplitude > 0.8V) , the smart meter 50 transmits a first logical value, e.g. a bit logic 1. When the signal carrier is absent in the input signal SI (e.g. with a value <0.8V) , the smart meter 50 transmits a second logical value, e.g. a bit logic 0. The smart meter 50 transmits information by transmitting a stream of bits. The bit stream is encoded using on-off keying modulation, abbreviated OOK modulation. Thus, the demodulator output signal SD of the three periods A, B, C has the bit logic 101. A length of the pulse of the demodulator output signal SD in the third period C and a length TD of the pulse in the first period A may be different. The different pulse lengths do not contain e.g. an information.

Figure 4A shows an example of an arrangement 10 with a signal converter 11 which is a further development of the aboveshown examples. The signal converter 11 comprises a converter housing 140. The circuit parts as shown in Figures 1 and 2A to 2C are inserted into the converter housing 140. The converter housing 140 includes an opening 141. The opening

141 is formed such that the signal converter 11 can be attached to a rail 142 of a switchboard 143. The rail 142 is e.g. a DIN rail. The signal converter 11 receives its electrical power e.g. from the switchboard 143. The smart meter 50 provides electrical power EP to the device 55. Data provided by the smart meter 50 is applied to the signal converter 11. The signal converter 11 provides converted data using a Modbus protocol to the device 55.

Figure 4B shows a further example of an arrangement 10 which is a further development of the above-shown examples. The smart meter 50 includes a housing 145. The signal converter 11 is formed such that it fits inside the housing 145 of the smart meter 50. The smart meter 50 obtains a free space in which the converter housing 140 of the signal converter can be inserted. Thus, the signal converter 11 is integrated into the housing 145 of the smart meter 50. The housing 145 of the smart meter 50 has an opening for the connection line or connection lines which couple the signal converter 11 e.g. to the device 55.

The embodiments shown in Figures 1 to 4B as stated represent examples of the improved signal converter 11 and the arrangement 10; therefore, they do not constitute a complete list of all embodiments according to the improved signal converter and the arrangement. Actual signal converters and arrangements may vary from the embodiments shown in terms of parts, structures and shape, for example. Re ference signs

10 arrangement

11 signal converter

12 converter input

13 first input terminal

14 second input terminal

16 trans former

17 primary side

18 secondary side

20 demodulator

21 demodulator output

22 microcontroller

23 input

24 output

25 converter output

26 transceiver

41 power supply

42 display

43 power supply indicator

50 smart meter

51 , 52 output terminal

55 device

57 computer

58 display

60 first socket

61 third input terminal

62 second socket

63 - 65 input terminal

71 , 72 terminal

73 trans former capacitor

74 , 75 trans former resistor

80 antiparallel circuit of diodes

81 , 82 diode , 84 terminal comparator , 88 input filter first filter capacitor first filter resistor second filter capacitor reference potential terminal- 97 resistor supply output stabili zation capacitor 0 comparator output 1 comparator resistor 0 edge detector 1 multivibrator 2 input 3 coupling resistor 4 output 5 control capacitor 6 , 117 control terminal 8 , 119 control resistor 0 output resistor 1 stabili zation capacitor 0 pulse generator 1 input 2 output 4 set terminal 5 set resistor 6 voltage divider 7 divider input 8 , 139 divider resistor 0 converter housing 1 opening 2 rail 143 switchboard

145 housing

EP electrical power

S I input signal S2 further input signal

SC comparator output signal

SD demodulator output signal

SO converter output signal t time TC , TD pulse duration

VDD supply voltage

VS voltage

Claims

26

Claims

1. Signal converter (11) , comprising a converter input (12) , a transformer (16) with a primary side (17) coupled to the converter input (12) , an anti-parallel circuit of diodes (80) including a first diode (81) and a second diode (82) , a demodulator (20) comprising a filter (90) , a comparator (86) and a demodulator output (21) , and a converter output (25) coupled to the demodulator output (21) , wherein the filter (90) is coupled to a secondary side (18) of the transformer (16) , and wherein an input side of the comparator (86) is coupled to the filter (90) and a comparator output (100) of the comparator (86) is coupled to the demodulator output (21) , wherein an anode of the first diode (81) is connected to a cathode of the second diode (82) and a cathode of the first diode (81) is connected to an anode of the second diode (82) , wherein the anode of the first diode (81) is coupled to a first terminal (83) of the secondary side (18) of the transformer (16) , and wherein the cathode of the first diode (81) is coupled to a second terminal (84) of the secondary side (18) of the transformer (16) .

2. Signal converter (11) of claim 1, wherein the signal converter (11) is configured to receive an input signal (SI) at the converter input (12) and to convert the input signal (SI) in a converter output signal (SO) that is provided at the converter output (25) , and wherein the input signal (SI) is an amplitude modulated signal, an amplitude shift keying signal or an on-off-keying signal .

3. Signal converter (11) of claim 1 or 2, wherein the transformer (16) is realized as a current transformer .

4. Signal converter (11) of one of claims 1 to 3, wherein a turn ratio R of the transformer (16) is calculated according to the following equation: wherein NPRI is number of turns of windings on the primary side (17) of the transformer (16) and NSEC is a number of turns of windings on the secondary side (18) of the transformer (16) , and wherein 1.2 > R .

5. Signal converter (11) of one of claims 1 to 4, wherein the first and the second diode (81, 82) are implemented as Schottky diodes.

6. Signal converter (11) of one of claims 1 to 5, wherein the demodulator (20) comprises a edge detector (110) which comprises an input side coupled to the comparator output (100) and an output side coupled to the demodulator output (21) .

7. Signal converter (11) of claim 6, wherein the edge detector (110) is configured to generate a demodulator output signal (SD) as a function of a comparator output signal (SC) of the comparator (86) , and wherein a pulse duration (TD) of the demodulator output signal (SD) is longer than a pulse duration (TC) of the comparator output signal (SC) .

8. Signal converter (11) of claim 6 or 7, wherein the edge detector (110) comprises at least one of a monostable multivibrator (111) or a pulse generator (130) .

9. Signal converter (11) of one of claims 1 to 8, wherein the signal converter (11) comprises a microcontroller (22) having an input (23) coupled to the demodulator output (21) and an output (24) coupled to the converter output (25) .

10. Signal converter (11) of claim 9, wherein the signal converter (11) comprises a transceiver

(26) having an input coupled to the output (24) of the microcontroller (22) and an output coupled to the converter output (25) .

11. Signal converter (11) of one of claims 1 to 10, wherein the signal converter (11) includes a converter housing (140) which is configured to be attached to a switchboard (143) .

12. Signal converter (11) of claim 11, wherein the converter housing (140) is configured to be attached to a rail (142) of the switchboard (143) .

13. Arrangement (10) , comprising

- the signal converter (11) of one of claims 1 to 12, and

- a smart meter (50) coupled to the converter input (12) .

14. Arrangement (10) of claim 13, - 29 - wherein the smart meter (50) includes a housing (145) and wherein the signal converter (11) is inserted into the housing (145) of the smart meter (50) .