EP3984035A4 - Gestion de mémoire et décodage d'effacement pour dispositif de mémoire - Google Patents
Gestion de mémoire et décodage d'effacement pour dispositif de mémoire Download PDFInfo
- Publication number
- EP3984035A4 EP3984035A4 EP20822879.1A EP20822879A EP3984035A4 EP 3984035 A4 EP3984035 A4 EP 3984035A4 EP 20822879 A EP20822879 A EP 20822879A EP 3984035 A4 EP3984035 A4 EP 3984035A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- erasure decoding
- memory device
- management
- memory management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2255—Bit-line or column circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/441,722 US10984847B2 (en) | 2019-06-14 | 2019-06-14 | Memory management for charge leakage in a memory device |
| US16/840,286 US11301320B2 (en) | 2020-04-03 | 2020-04-03 | Erasure decoding for a memory device |
| PCT/US2020/032100 WO2020251708A1 (fr) | 2019-06-14 | 2020-05-08 | Gestion de mémoire et décodage d'effacement pour dispositif de mémoire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP3984035A1 EP3984035A1 (fr) | 2022-04-20 |
| EP3984035A4 true EP3984035A4 (fr) | 2023-06-28 |
Family
ID=73781592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP20822879.1A Withdrawn EP3984035A4 (fr) | 2019-06-14 | 2020-05-08 | Gestion de mémoire et décodage d'effacement pour dispositif de mémoire |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP3984035A4 (fr) |
| CN (1) | CN114144834A (fr) |
| TW (2) | TWI762932B (fr) |
| WO (1) | WO2020251708A1 (fr) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11366976B2 (en) * | 2019-05-09 | 2022-06-21 | Micron Technology, Inc. | Updating manufactured product life cycle data in a database based on scanning of encoded images |
| US20230008349A1 (en) * | 2021-07-09 | 2023-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sram device for fpga application |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120297115A1 (en) * | 2011-05-18 | 2012-11-22 | Phison Electronics Corp. | Program code loading and accessing method, memory controller, and memory storage apparatus |
| US20140233314A1 (en) * | 2011-08-23 | 2014-08-21 | Micron Technology, Inc. | Memory cell coupling compensation |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7283398B1 (en) * | 2004-05-04 | 2007-10-16 | Spansion Llc | Method for minimizing false detection of states in flash memory devices |
| WO2007132456A2 (fr) * | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Dispositif de mémoire présentant une capacité adaptative |
| KR101598382B1 (ko) * | 2010-03-02 | 2016-03-02 | 삼성전자주식회사 | 상태 기반 불휘발성 메모리 장치 및 그것의 에러 정정 방법 |
| KR102083491B1 (ko) * | 2012-12-05 | 2020-03-02 | 삼성전자 주식회사 | 메모리 장치, 메모리 시스템 및 이의 동작 방법 |
| US9367391B2 (en) * | 2013-03-15 | 2016-06-14 | Micron Technology, Inc. | Error correction operations in a memory device |
| GB2525430B (en) * | 2014-04-25 | 2016-07-13 | Ibm | Error-correction encoding and decoding |
| US9583183B2 (en) * | 2014-09-26 | 2017-02-28 | Sandisk Technologies Llc | Reading resistive random access memory based on leakage current |
| US9589655B1 (en) * | 2015-10-02 | 2017-03-07 | Seagate Technology Llc | Fast soft data by detecting leakage current and sensing time |
| US9881661B2 (en) * | 2016-06-03 | 2018-01-30 | Micron Technology, Inc. | Charge mirror-based sensing for ferroelectric memory |
| US10067827B2 (en) * | 2016-06-29 | 2018-09-04 | Micron Technology, Inc. | Error correction code event detection |
| US10372566B2 (en) * | 2016-09-16 | 2019-08-06 | Micron Technology, Inc. | Storing memory array operational information in nonvolatile subarrays |
| KR102314481B1 (ko) * | 2017-05-08 | 2021-10-20 | 에스케이하이닉스 주식회사 | Siso 복호 방법, 디코더 및 반도체 메모리 시스템 |
| KR102350957B1 (ko) * | 2017-10-26 | 2022-01-14 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 리프레시 제어 방법 |
-
2020
- 2020-05-08 WO PCT/US2020/032100 patent/WO2020251708A1/fr active Application Filing
- 2020-05-08 CN CN202080052191.XA patent/CN114144834A/zh not_active Withdrawn
- 2020-05-08 EP EP20822879.1A patent/EP3984035A4/fr not_active Withdrawn
- 2020-05-20 TW TW109116783A patent/TWI762932B/zh active
- 2020-05-20 TW TW111111558A patent/TW202230388A/zh unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120297115A1 (en) * | 2011-05-18 | 2012-11-22 | Phison Electronics Corp. | Program code loading and accessing method, memory controller, and memory storage apparatus |
| US20140233314A1 (en) * | 2011-08-23 | 2014-08-21 | Micron Technology, Inc. | Memory cell coupling compensation |
Non-Patent Citations (1)
| Title |
|---|
| See also references of WO2020251708A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3984035A1 (fr) | 2022-04-20 |
| TWI762932B (zh) | 2022-05-01 |
| WO2020251708A1 (fr) | 2020-12-17 |
| TW202105402A (zh) | 2021-02-01 |
| TW202230388A (zh) | 2022-08-01 |
| CN114144834A (zh) | 2022-03-04 |
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| RIC1 | Information provided on ipc code assigned before grant |
Ipc: G11C 29/44 20060101ALI20230522BHEP Ipc: G11C 29/04 20060101ALI20230522BHEP Ipc: G06F 11/10 20060101ALI20230522BHEP Ipc: G11C 29/52 20060101ALI20230522BHEP Ipc: G11C 11/22 20060101AFI20230522BHEP |
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| 18D | Application deemed to be withdrawn |
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