EP3881611A2

EP3881611A2 - User equipment power saving in new radio system

Info

Publication number: EP3881611A2
Application number: EP19884144.7A
Authority: EP
Inventors: Gang Xiong; Hong He; Yushu Zhang; Jie Cui
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2018-11-13
Filing date: 2019-11-12
Publication date: 2021-09-22
Also published as: EP3881611A4; WO2020102146A2; WO2020102146A3

Abstract

Embodiments of the present disclosure provide for activation and deactivation of bandwidth parts or search space sets for user equipment power saving. Other embodiments may be described and claimed.

Description

USER EQUIPMENT POWER SAVING IN NEW RADIO SYSTEM

Cross Reference to Related Application

The present application claims priority to U.S. Provisional Patent Application No. 62/760,346, filed November 13, 2018, and entitled“User Equipment Power Saving in 5GNew Radio System.” The disclosure of this application is hereby incorporated by reference in its entirety.

Field

Embodiments of the present invention relate generally to the technical field of wireless communications.

Background

User equipment (UE) battery life is an important aspect of the user experience and will influence the adoption of Third Generation Partnership Project (3GPP) Fifth Generation (5G) handsets and services. Legacy UE power consumption has been approved to ensure that UE power efficiency for 5G New Radio (NR) UEs can be at least not worse than 3GPP Long Term Evolution (LTE).

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 illustrates a network in accordance with some embodiments.

Figure 2 is a diagram that illustrates activation/deactivation of search space sets in accordance with some embodiments.

Figure 3 is a diagram that illustrates activation/deactivation of various search space sets in accordance with some embodiments.

Figure 4 is a media access control data unit sub-header in accordance with some embodiments.

Figure 5 is a diagram that illustrates a power-efficient monitoring operation in accordance with some embodiments.

Figure 6 illustrates an operation flow/ algorithmic structure in accordance with some embodiments.

Figure 7 illustrates an operation flow/algorithmic structure in accordance with some embodiments.

Figure 8 illustrates an operation flow/algorithmic structure in accordance with some embodiments. Figure 9 illustrates a platform in accordance with various embodiments.

Figure 10 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (for example, a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein.

Detailed Description

The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail. For the purposes of the present document, the phrases“A or B” and“A/B” mean (A), (B), or (A and B).

Embodiments disclosed herein may be directed to various processes and/or techniques to save UE power by adapting to the traffic and UE power consumption characteristics in different dimensions, e.g. frequency, time, antenna domains, discontinuous reception (DRX)

configuration, and UE processing timeline for UE power saving.

This disclosure may describe processes or techniques to reduce power consumption of NR UEs. These processes/techniques may include: enhanced management of search space sets, including both media access control - control element (MAC-CE) and downlink control information (DCI) based management schemes; dynamic physical downlink control channel (PDCCH) monitoring operations; and schemes to improve bandwidth part (BWP) operation. Certain aspects of this disclosure may provide ways to reduce power consumption of an NR UE in a 5G wireless communication system.

Figure 1 schematically illustrates an example wireless network 100 (hereinafter“network 100”) in accordance with various embodiments herein. The network 100 may include a UE 105 in wireless communication with an access node (AN) 110. In some embodiments, the network 100 may be a 3GPP 5G/NR network. The UE 105 may be configured to connect, for example, to be communicatively coupled, with the AN 110 via connection 112. In this example, the connection 112 is illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols such as an LTE protocol, a 5GNR protocol operating at mmWave and sub-6GHz, a Global System for Mobile Communications (GSM) protocol, a code-division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, and the like.

The UE 105 may be any mobile or non-mobile computing devices, such as a smartphone, personal data assistant (PDA), pager, laptop computer, desktop computer, wireless handset, customer premises equipment (CPE), fixed wireless access (FWA) device, vehicle mounted UE or any computing device including a wireless communications interface. In some embodiments, the UE 105 can comprise an Internet of Things (IoT) UE, which can comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections. An IoT UE can utilize technologies such as narrowband IoT (NB-IoT), machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), Proximity-Based Service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. The M2M or MTC exchange of data may be a machine-initiated exchange of data. An NB-IoT/MTC network describes

interconnecting NB-IoT/MTC UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. The NB- IoT/MTC UEs may execute background applications (for example, keep-alive message, status updates, location related services, etc.).

The AN 110 can enable or terminate the connection 112. The AN 110 can be referred to as a base station (BS), NodeB, evolved-NodeB (eNB), Next-Generation NodeB (gNB or ng- gNB), NG-RAN node, cell, serving cell, neighbor cell, and so forth, and can comprise ground stations (for example, terrestrial access points) or satellite stations providing coverage within a geographic area.

The AN 110 can be the first point of contact for the UE 105. In some embodiments, the AN 110 can fulfill various logical functions including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

The UE 105 may include protocol processing circuitry 115, which may implement one or more of layer operations related to medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC) and non-access stratum (NAS). The protocol processing circuitry 115 may include one or more processing cores (not shown) to execute instructions and one or more memory structures (not shown) to store program and data information.

The UE 105 may further include digital baseband circuitry 125, which may implement physical layer (PHY) functions including one or more of hybrid automatic repeat request- acknowledgment (HARQ-ACK) functions, scrambling and/or descrambling, coding and/or decoding, layer mapping and/or de-mapping, modulation symbol mapping, received symbol and/or bit metric determination, multi-antenna port pre-coding and/or decoding, which may include one or more of space-time, space-frequency or spatial coding, reference signal generation and/or detection, preamble sequence generation and/or decoding, synchronization sequence generation and/or detection, control channel signal blind decoding, and other related functions.

The UE 105 may further include transmit circuitry 135, receive circuitry 145, radio frequency (RF) circuitry 155, and RF front end (RFFE) 165, which may include or connect to one or more antenna panels 175.

As used herein, the term“circuitry” may refer to, is part of, or includes hardware components such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group), an Application Specific Integrated Circuit (ASIC), a field-programmable device (FPD) (e.g., a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable system on chip (SoC)), digital signal processors (DSPs), etc., that are configured to provide the described functionality. In some embodiments, the circuitry may execute one or more software or firmware programs to provide at least some of the described functionality. In addition, the term“circuitry” may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) with the program code used to carry out the functionality of that program code. In these embodiments, the combination of hardware elements and program code may be referred to as a particular type of circuitry.

In some embodiments, RF circuitry 155 may include multiple parallel RF chains or branches for one or more of transmit or receive functions; each chain or branch may be coupled with one antenna panel 175.

In some embodiments, the protocol processing circuitry 115 may include one or more instances of control circuitry (not shown) to provide control functions for the digital baseband circuitry 125 (or simply,“baseband circuitry 125”), transmit circuitry 135, receive circuitry 145, radio frequency circuitry 155, RFFE 165, and one or more antenna panels 175.

A UE reception may be established by and via the one or more antenna panels 175,

RFFE 165, RF circuitry 155, receive circuitry 145, digital baseband circuitry 125, and protocol processing circuitry 115. The one or more antenna panels 175 may receive a transmission from the AN 110 by receive-beamforming signals received by a plurality of antennas/antenna elements of the one or more antenna panels 175. The transmission from the AN 110 may be transmit-beamformed by antennas of the AN 110. In some embodiments, the baseband circuitry 125 may contain both the transmit circuitry 135 and the receive circuitry 145. In other embodiments, the baseband circuitry 125 may be implemented in separate chips or modules, for example, one chip including the transmit circuitry 135 and another chip including the receive circuitry 145.

Similar to the UE 105, the AN 110 may include protocol processing circuitry 120, digital baseband circuitry 130 (or simply,“baseband circuitry 130”), transmit circuitry 140, receive circuitry 150, RF circuitry 160, RFFE 170, and one or more antenna panels 180.

A cell transmission may be established by and via the protocol processing circuitry 120, digital baseband circuitry 130, transmit circuitry 140, RF circuitry 160, RFFE 170, and one or more antenna panels 180. The transmission components of the UE 105 may apply a spatial filter to the data to be transmitted to form a transmit beam emitted by the antenna elements of the one or more antenna panels 180.

In 5G design, a carrier bandwidth may be segmented into a plurality of different bandwidth parts (BWPs). The BWP may be a contiguous set of physical resource blocks selected from a contiguous subset of common resource block for a given numerology on a given carrier. The AN may configure the UE 105 with a number of uplink (UL) and downlink (DL) BWPs. In general, the UE 105 may be configured with up to four UL/DL BWPs with a single BWP being active at a given time; however, this may be different in some embodiments.

In one or more embodiments, for each DL BWP configured to the UE 105 in a serving cell, the UE 105 may be provided by higher-layer (for example, higher than PHY layer) with S search space sets (SSSs) with different PDCCH monitoring periodicities of k_P,s slots and a PDCCH monitoring offset of o_P,s where p is a control resource set (CORESET) identifier (ID).

In some embodiments, one or more fields in a power saving signal, for example, a wake-up signal (WUS) or go-to-sleep signal (GTS), may include information for PDCCH monitoring.

The fields may include a BWP indicator field, a search space set indictor field (SSSIF), or a joint field for BWP and SSS. In some embodiments, the information for PDCCH monitoring may include a BWP indicator or an SSS indicator.

The BWP indicator may be a 0-, 1-, or 2-bit value, for example, depending on a number of DL BWPs configured by higher layers. The BWP indicator may indicate an active BWP at a start of an active time of a DRX cycle.

The SSS indicator may be a 0-, 1-, 2-, 3-, or 4-bit value, for example, that indicates one or more active SSSs from those configured by higher layers for PDCCH monitoring. In some designs, a bitmap information element (IE) may include multiple bits and each bit may indicate the activation/deactivation state of an SSS with an SSS index i that is numbered within the associated BWP starting from 0. The SSS, field may be set to“1” to indicate that the SSS with SSS index i within a BWP is activated for PDCCH monitoring.

Figure 2 is a diagram 200 that illustrates activation/deactivation of various search space sets of a BWP 205 in accordance with some embodiments. In this embodiment, the UE 105 may be configured with two search space sets, SSS 220 and SSS 230, of the BWP 205. The two SSSs may be inactive by default. The SSS 220 may correspond to an SSSIF of zero, while the SSS 230 may correspond to an SSSIF of one. The AN 110 may transmit a power saving signal 210 to the UE 105 with an SSSIF set to zero to indicate that the SSS 220 is to be active for PDCCH monitoring after an offset 215. In some embodiments, the value of the offset 215 may be signaled to the UE 105 by higher layers (for example, above the PHY layer). The UE 105 may monitor the activated PDCCH monitoring occasions in the first two instances of the SSS 220.

In the second instance of the SSS 220, the UE 105 may detect another power saving signal 225 transmitted by the AN 110. The power saving signal 225 may have an SSSIF set to one to indicate that the SSS 230 is to be activated after another offset value for PDCCH monitoring and the SSS 220 is to be deactivated. Thus, the third instance of the SSS 220 is to be deactivated, while the fourth, fifth, and sixth instances of the SSS 230 are to be activated.

In the sixth instance of the SSS 230, the UE 105 may detect another power saving signal 235 transmitted by the AN 110. The power saving signal 235 may have an SSSIF sent to zero to indicate that the SSS 220 is to be activated after another offset value for PDCCH monitoring and the SSS 230 is to be deactivated.

In some embodiments, the offset 215 may be similar to the offsets after a power saving signal 225 and power saving signal 235. However, in other embodiments, one or more of these offsets may be configured separately.

Figure 3 is a diagram 300 that illustrates activation/deactivation of various search space sets of a BWP 305 in accordance with some embodiments. In this embodiment, the UE 105 may be configured with two search space sets, SSS 320 and SSS 330, of the BWP 305. The two SSSs may be inactive by default. The SSS 320 may correspond to an SSSIF of zero, while the SSS 330 may correspond to an SSSIF of one. The AN 110 may transmit a power saving signal 310 to the UE 105 with an SSSIF set to zero to indicate that the SSS 320 is to be active for PDCCH monitoring after an offset 315. In some embodiments, the value of the offset 315 may be signaled to the UE 105 by higher layers (for example, above the PHY layer). The UE 105 may monitor the activated PDCCH monitoring occasions of the SSS 320.

In the second instance of the SSS 320, the UE 105 may detect another power saving signal 325 transmitted by the AN 110. The power saving signal 325 may have an SSSIF set to one to indicate that the SSS 330 is to be activated after another offset value for PDCCH monitoring. However, instead of deactivating the primary SSS 320, it may remain activated. After the second instance of the SSS 320, the UE may monitor PDCCH occasions in both the primary SSS 320 and the secondary SSS 330.

In the fourth instance of the SSS 320, the UE may detect another power saving signal 335 transmitted by the AN 110. The power saving signal 335 may have an SSSIF set to one to indicate that the SSS 330 is to be deactivated after another offset value. Thus, the last two instances of the SSS 330 may be deactivated and the UE 105 may not need to monitor the PDCCH monitoring occasions.

In this manner, the primary SSS 320 may always include activated PDCCH monitoring occasions once the BWP 305 is activated, while the PDCCH monitoring occasions of the secondary SSS 330 may be dynamically activated/deactivated by power saving signals transmitted in the primary SSS 320. In some embodiments, the power saving signals 325/335 may be GTS signals, which may always be transmitted in the primary SSS 320.

Figures 2 and 3 illustrate two search space sets being configured. However, in various embodiments any number of search space sets may be configured. Furthermore, some embodiments may include a plurality of search space sets associated with one another in a group. The SSS groups (SSSGs) may be established by higher-layer configuration (for example, above the PHY layer). Activation/deactivation of PDCCH monitoring occasions of the different SSSGs may be similar to activation/deactivation a PDCCH monitoring occasions of different SSSs, such as that described above. For example, in some embodiments a signal may include an IE having a plurality of bits with each bit indicating an activation/deactivation state of an SSSG with SSSG index i.

In some embodiments, an IE may indicate an index of an SSS index i that is numbered within an associated BWP starting from a value of 0.

In some embodiments, no SSSIF IE is included in WUS/GTS DCI formats. Instead, an SSS with a largest PDCCH monitoring periodicity k_P,s of the configured SSSs may be used for PDCCH monitoring at the start of active time of DRX cycle. Consider, for example, the embodiment of Figure 2. In this embodiment, the UE 105 may determine that the SSS 220 includes the largest PDCCH monitoring periodicity of the configured SSSs (for example, SSS 220 has a larger PDCCH monitoring periodicity than SSS 230). Thus, in this embodiment, the SSS 220 may automatically be activated at a start of the active BWP 205.

In some embodiments, a timer-based SSS switching may be utilized. The UE 105 may be configured with a higher-layer parameter SSS inactivity time ( SSS-InactivityTimer ) that indicates a timer value. The UE 105 may start the SSS-InactivityTimer at a beginning of an active DL BWP. If the SSS-InactivityTimer associated with the active DL BWP expires, the UE 105 may perform SSS switching to an SSS indicated by a default SSS identifier ( defaultSSS-Id) if one is configured. If a default SSS identifier is not configured, the UE 105 may perform, upon expiration of the SSS-InactivityTimer, SSS switching to an SSS with the largest SSS periodicity, for example, SSS 220 as shown in Figure 2 and SSS 320 in Figure 3.

In some embodiments, the network (for example, the AN 110) may activate/deactivate configured SSSs/SSSGs/BWPs of a serving cell by sending an activation/deactivation MAC CE. In some embodiments a configured SSS/BWP may initially be deactivated upon configuration and after a handover. The activation/deactivation MAC CE may be identified by a MAC PDU subheader 400 with a dedicated logical channel identifier (LCID) as shown in Figure 4 in accordance with some embodiments. The MAC PDU subheader 400 may have a fixed size with the following fields.

An A/D field 404 may be used to indicate whether the MAC CE is used to activate or deactivate an indicated SSS or SSSG. In some embodiments, the field may be set to“1” to indicate activation; otherwise, it may indicate deactivation.

A serving cell ID field 408 may be used to indicate an identity of a serving cell for which the MAC CE applies. In some embodiments, the length of this field may be five bits.

A BWP ID field 412 may include a BWP identity of a downlink bandwidth part for which the MAC CE applies. In some embodiments, the length of this field may be two bits.

An SSS ID or SSSG ID field may include an index of an SSS or an SSSG to indicate an SSS or SSSG to be activated or deactivated. In some embodiments, the length of this field may be four bits.

In some embodiments, a power saving signal may include a cross-slot scheduling indicator field. This may be a one bit field that provides information with respect to slot offsets between a scheduling PDCCH and a scheduled PDSCH/PUSCH. In some embodiments, a slot offset for PDSCH reception may be referred to as Ko, while a slot offset for PUSCH

transmission may be referred to as K2.

In one embodiment, a cross-slot scheduling indicator field may indicate whether Ko>0 K2 0 may be assumed for PDCCH monitoring.

In another embodiment, slot offset K₀ > 0 for PDSCH reception and slot offset K₂ > 0 for PUSCH transmission may be predefined and assumed by the UE 105 during a DRX cycle until the UE 105 detects a first DCI format for PDSCH or PUSCH scheduling, when an associated WUS was received before the start of the DRX cycle so as to reduce UE’s power consumption. An example of this is shown in Figure 5. Figure 5 is a diagram 500 that illustrates a power-efficient PDCCH monitoring operation within a DRX cycle triggered by a WUS in accordance with some embodiments. The UE 105 may receive a WUS 510 transmitted by the AN 110 and may determine an active time for a DRX cycle after an offset.

At the start of the active time of the DRX cycle, the UE 105 may assume first values of K_Q and K^® for PDCCH monitoring for a first PDCCH monitoring period 510. The first values may be predefined, configured by higher layers (for example, RRC), or indicated by the WUS 510.

The PDCCH monitoring period 525 may start from PDCCH monitoring occasion 520. The UE 105 may determine that second values K_Q and A"! value, which are different than the first values K and K^. are to be used for PDCCH monitoring by the UE 105 in the PDCCH monitoring period 525. The second values may be configured by RRC, indicated by power saving signal (for example, 510 or 515) dynamically, or predefined in specification. In some embodiments, for example, the second values may be K_Q = A'₂ ¹ = 0.

In some embodiments, the length of the periods 510 and 525, or updates thereto, may be configured by RRC, indicated by power-saving signal (for example, 510 or 515), or predefined in specification.

In some embodiments, to further improve the efficiency in periods 510 and 525, a set of Ko and K2 values can be first configured by an RRC message and then be dynamically selected from these configured values by a DCI format (for example, WUL signal or the GTS signal) for (K_Q , A'₂°) or (K_Q . A'₂ ¹) for subsequent PDCCH monitoring occasions in periods 510 and 525, respectively.

In some embodiments, a minimum offset value for Ko>0, K2 0 may be configured by higher layers and the UE 105 may not be expected to be dynamically scheduled for PDSCH or PUSCH with an offset value smaller than this minimum value. The same rule can be also applied for aperiodic - channel state information (A-CSI) triggering.

In some embodiments, a power saving signal (for example, WUS or GTS) may include a sleep duration (SD) field. An SD field may be, for example, two bits that indicate a duration of PDCCH monitoring skip. Table 1 illustrates example sleep durations, S, which may be defined relative to periodicity, P, of the power saving signal. In various embodiments, the units of S and P may be time (e.g., ms), slots, or subframes.

In some embodiments, the sleep duration may begin from reception of the power saving signal that includes the SD field.

Figure 6 illustrates an operation flow/algorithmic structure 600 in accordance with some embodiments. The operation flow/algorithmic structure 600 may be performed, in part or in whole, by the UE 105 or components thereof. For example, in some embodiments the operation flow/algorithmic structure 600 may be performed by baseband circuitry of the UE 105.

The operation flow/algorithmic structure 600 may include, at 604, receiving a power saving signal. The power-saving signal may be a WUS or a GTS. In some embodiments, the power-saving signal may be transmitted from the AN 110 to the UE 105 outside of an activated BWP. For example, the power-saving signal may be a WUS that is transmitted in as part of a DRX operation. See, for example, power saving signal 210 of Figure 2 and 310 of Figure 3. In other embodiments, the power-saving signal may be transmitted in an activated BWP. See, for example, power saving signals 225 or 235 of Figure 2 or power saving signals 325 or 335 of Figure 3.

The operation flow/algorithmic structure 600 may further include, at 608, identifying an SSS. The SSS may be identified based on information transmitted in the power-saving signal. For example, the information may include a bandwidth part indicator to indicate the active bandwidth in which the SSS is found; or a search space set indicator to provide an index of the SSS. In some embodiments, the identifying of the SSS at 608 may include identifying a plurality of SSSs of a particular group that is identified through information in the power-saving signal.

The operation flow/algorithmic structure 600 may further include, at 612, monitoring PDCCH candidates in the identified SSS. In some embodiments, the monitoring of the PDCCH candidates may result in the detection of the DCI within a power saving signal that starts the operation flow/algorithmic structure 600 again.

Figure 7 illustrates an operation flow/algorithmic structure 700 in accordance with some embodiments. The operation flow/algorithmic structure 700 may be performed, in part or in whole, by the UE 105 or components thereof. For example, in some embodiments the operation flow/algorithmic structure 700 may be performed by baseband circuitry of the UE 105.

The operation flow/algorithmic structure 700 may include, at 704, receiving

configuration information to configure a plurality of SSSs or BWPs. In some embodiments, the configuration information may be transmitted in higher-layer signaling such as, but not limited to, RRC signaling. Thus, the UE may process the RRC signaling to receive the configuration information.

The operation flow/algorithmic structure 700 may further include, at 708, receiving a MAC CE. The MAC CE may include a MAC PDU subheader with a dedicated LCID. In some embodiments, the MAC PDU subheader may include information to identify one or more SSS or BWPs, indicate whether the MAC CE is to activate or deactivate the identified SSSs/BWPs. In some embodiments, the MAC PDU subheader may include information to identify an SSSG that is to be activated or deactivated.

The operation flow/algorithmic structure 700 may further include, at 712, activating or deactivating one or more SSSs/BWPs based on the MAC CE. In some embodiments, upon activating the SSSs/BWPs, the UE may monitor PDCCH candidates within the activated SSS.

Figure 8 illustrates an operation flow/algorithmic structure 800 in accordance with some embodiments. The operation flow/ algorithmic structure 800 may be performed, in part or in whole, by the UE 105 or components thereof. For example, in some embodiments the operation flow/algorithmic structure 800 may be performed by baseband circuitry of the UE 105.

The operation flow/algorithmic structure 800 may include, at 804, receiving DCI. The downlink control information may be a DCI format four PDSCH or PUSCH scheduling. The DCI may be detected in a PDCCH monitoring occasion.

The operation flow/algorithmic structure 800 may further include, at 804, selecting a slot offset value from the set of slot offset value stored in memory based on receiving the DCI. In some embodiments, the UE 105 may use a first set of slot offset values for a first period of time and a second set of slot offset values for a second period of time. The receipt of the DCI may indicate when to switch from the first period of time to the second period of time. In some embodiments, the DCI may provide an indication of specific slot offset values that are to be used. The indication may reference slot offset values previously configured by, for example, RRC signaling.

The operation flow/algorithmic structure 800 may further include, at 812, detecting PDCCH that schedules a PUSCH transmission or a PDSCH reception. In some embodiments, the detecting of the PDCCH may be performed by monitoring PDCCH candidates as described elsewhere herein.

The operation flow/algorithmic structure 800 may further include, at 816, determining a slot of the scheduled PUSCH/PDSCH based on the slot offset value. As described above, the slot offset values may be specific to the scheduled channel. For example, Ko may correspond to a PDSCH reception and K2 may correspond to a PUSCH transmission. Figure 9 illustrates an example of a platform 900 (or“device 900”) in accordance with various embodiments. In embodiments, the computer platform 900 may be suitable for use as UE 105 or AN 110 and/or any other element/device discussed herein. The platform 900 may include any combinations of the components shown in the example. The components of platform 900 may be implemented as integrated circuits (ICs), portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or a combination thereof adapted in the computer platform 900, or as components otherwise incorporated within a chassis of a larger system. The block diagram of Figure 9 is intended to show a high level view of components of the computer platform 900. However, some of the components shown may be omitted, additional components may be present, and different arrangement of the components shown may occur in other implementations.

Application circuitry 905 includes circuitry such as, but not limited to one or more processors (or processor cores), cache memory, and one or more of LDOs, interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose I/O, memory card controllers such as SD MMC or similar, USB interfaces, MIPI interfaces, and JTAG test access ports. The processors (or cores) of the application circuitry 905 may be coupled with or may include memory /storage elements and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the system 900. In some implementations, the memory /storage elements may be on-chip memory circuitry, which may include any suitable volatile and/or non-volatile memory, such as DRAM, SRAM,

EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology, such as those discussed herein.

The processor(s) of application circuitry XS105 may include, for example, one or more processor cores, one or more application processors, one or more GPUs, one or more RISC processors, one or more ARM processors, one or more CISC processors, one or more DSP, one or more FPGAs, one or more PLDs, one or more ASICs, one or more microprocessors or controllers, a multithreaded processor, an ultra-low voltage processor, an embedded processor, some other known processing element, or any suitable combination thereof. In some

embodiments, the application circuitry XS105 may comprise, or may be, a special-purpose processor/controller to operate according to the various embodiments herein.

As examples, the processor(s) of application circuitry 905 may include an Intel®

Architecture Core™ based processor, such as a Quark™, an Atom™, an i3, an i5, an i7, or an MCU-class processor, or another such processor available from Intel® Corporation, Santa Clara, CA. The processors of the application circuitry 905 may also be one or more of Advanced Micro Devices (AMD) Ryzen® processor(s) or Accelerated Processing Units (APUs); A5-A9 processor(s) from Apple® Inc., Snapdragon™ processor(s) from Qualcomm® Technologies, Inc., Texas Instruments, Inc.® Open Multimedia Applications Platform (OMAP)™ processor(s); a MIPS-based design from MIPS Technologies, Inc. such as MIPS Warrior M-class, Warrior I- class, and Warrior P-class processors; an ARM-based design licensed from ARM Holdings,

Ltd., such as the ARM Cortex-A, Cortex-R, and Cortex-M family of processors; or the like. In some implementations, the application circuitry 905 may be a part of a system on a chip (SoC) in which the application circuitry 905 and other components are formed into a single integrated circuit, or a single package, such as the Edison™ or Galileo™ SoC boards from Intel®

Corporation.

Additionally or alternatively, application circuitry 905 may include circuitry such as, but not limited to, one or more a field-programmable devices (FPDs) such as FPGAs and the like; programmable logic devices (PLDs) such as complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), and the like; ASICs such as structured ASICs and the like; programmable SoCs (PSoCs); and the like. In such embodiments, the circuitry of application circuitry 905 may comprise logic blocks or logic fabric, and other interconnected resources that may be programmed to perform various functions, such as the procedures, methods, functions, etc. of the various embodiments discussed herein. In such embodiments, the circuitry of application circuitry 905 may include memory cells (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, static memory (e.g., static random access memory (SRAM), anti-fuses, etc.)) used to store logic blocks, logic fabric, data, etc. in look-up tables (LUTs) and the like.

The baseband circuitry 910 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits. The various hardware electronic elements of baseband circuitry 910 are discussed infra with regard to Figure XT.

The RFEMs 915 may comprise a millimeter wave (mmWave) RFEM and one or more sub-mmWave radio frequency integrated circuits (RFICs). In some implementations, the one or more sub-mmWave RFICs may be physically separated from the mmWave RFEM. The RFICs may include connections to one or more antennas or antenna arrays (see e.g., antenna array XT111 of Figure XT infra), and the RFEM may be connected to multiple antennas. In alternative implementations, both mmWave and sub-mmWave radio functions may be implemented in the same physical RFEM 915, which incorporates both mmWave antennas and sub-mmWave.

The memory circuitry 920 may include any number and type of memory devices used to provide for a given amount of system memory. As examples, the memory circuitry 920 may include one or more of volatile memory including random access memory (RAM), dynamic RAM (DRAM) and/or synchronous dynamic RAM (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc. The memory circuitry 920 may be developed in accordance with a Joint Electron Devices Engineering Council (JEDEC) low power double data rate (LPDDR)-based design, such as LPDDR2, LPDDR3, LPDDR4, or the like. Memory circuitry 920 may be implemented as one or more of solder down packaged integrated circuits, single die package (SDP), dual die package (DDP) or quad die package (Q17P), socketed memory modules, dual inline memory modules (DIMMs) including microDIMMs or MiniDIMMs, and/or soldered onto a motherboard via a ball grid array (BGA). In low power implementations, the memory circuitry 920 may be on-die memory or registers associated with the application circuitry 905. To provide for persistent storage of information such as data, applications, operating systems and so forth, memory circuitry 920 may include one or more mass storage devices, which may include, inter alia, a solid state disk drive (SSDD), hard disk drive (HDD), a micro HDD, resistance change memories, phase change memories, holographic memories, or chemical memories, among others. For example, the computer platform 900 may incorporate the three-dimensional (3D) cross-point (XPOINT) memories from Intel® and Micron®.

Removable memory circuitry 923 may include devices, circuitry, enclosures/housings, ports or receptacles, etc. used to couple portable data storage devices with the platform 900. These portable data storage devices may be used for mass storage purposes, and may include, for example, flash memory cards (e.g., Secure Digital (SD) cards, microSD cards, xD picture cards, and the like), and USB flash drives, optical discs, external HDDs, and the like.

The platform 900 may also include interface circuitry (not shown) that is used to connect external devices with the platform 900. The external devices connected to the platform 900 via the interface circuitry include sensor circuitry 921 and electro-mechanical components (EMCs) 922, as well as removable memory devices coupled to removable memory circuitry 923.

The sensor circuitry 921 include devices, modules, or subsystems whose purpose is to detect events or changes in its environment and send the information (sensor data) about the detected events to some other a device, module, subsystem, etc. Examples of such sensors include, inter alia, inertia measurement units (IMUs) comprising accelerometers, gyroscopes, and/or magnetometers; microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) comprising 3-axis accelerometers, 3-axis gyroscopes, and/or magnetometers; level sensors; flow sensors; temperature sensors (e.g., thermistors); pressure sensors; barometric pressure sensors; gravimeters; altimeters; image capture devices (e.g., cameras or lensless apertures); light detection and ranging (LiDAR) sensors; proximity sensors (e.g., infrared radiation detector and the like), depth sensors, ambient light sensors, ultrasonic transceivers; microphones or other like audio capture devices; etc.

EMCs 922 include devices, modules, or subsystems whose purpose is to enable platform 900 to change its state, position, and/or orientation, or move or control a mechanism or (sub)system. Additionally, EMCs 922 may be configured to generate and send

messages/signalling to other components of the platform 900 to indicate a current state of the EMCs 922. Examples of the EMCs 922 include one or more power switches, relays including electromechanical relays (EMRs) and/or solid state relays (SSRs), actuators (e.g., valve actuators, etc.), an audible sound generator, a visual warning device, motors (e.g., DC motors, stepper motors, etc.), wheels, thrusters, propellers, claws, clamps, hooks, and/or other like electro-mechanical components. In embodiments, platform 900 is configured to operate one or more EMCs 922 based on one or more captured events and/or instructions or control signals received from a service provider and/or various clients.

In some implementations, the interface circuitry may connect the platform 900 with positioning circuitry 945. The positioning circuitry 945 includes circuitry to receive and decode signals transmitted/broadcasted by a positioning network of a GNSS. Examples of navigation satellite constellations (or GNSS) include United States’ GPS, Russia’s GLONASS, the European Union’s Galileo system, China’s BeiDou Navigation Satellite System, a regional navigation system or GNSS augmentation system (e.g., NAVIC), Japan’s QZSS, France’s DORIS, etc.), or the like. The positioning circuitry 945 comprises various hardware elements (e.g., including hardware devices such as switches, filters, amplifiers, antenna elements, and the like to facilitate OTA communications) to communicate with components of a positioning network, such as navigation satellite constellation nodes. In some embodiments, the positioning circuitry 945 may include a Micro-PNT IC that uses a master timing clock to perform position tracking/estimation without GNSS assistance. The positioning circuitry 945 may also be part of, or interact with, the baseband circuitry XS110 and/or RFEMs 915 to communicate with the nodes and components of the positioning network. The positioning circuitry 945 may also provide position data and/or time data to the application circuitry 905, which may use the data to synchronize operations with various infrastructure (e.g., radio base stations), for tum-by -turn navigation applications, or the like

In some implementations, the interface circuitry may connect the platform 900 with Near-Field Communication (NFC) circuitry 940. NFC circuitry 940 is configured to provide contactless, short-range communications based on radio frequency identification (RFID) standards, wherein magnetic field induction is used to enable communication between NFC circuitry 940 and NFC-enabled devices external to the platform 900 (e.g., an“NFC touchpoint”). NFC circuitry 940 comprises an NFC controller coupled with an antenna element and a processor coupled with the NFC controller. The NFC controller may be a chip/IC providing NFC functionalities to the NFC circuitry 940 by executing NFC controller firmware and an NFC stack. The NFC stack may be executed by the processor to control the NFC controller, and the NFC controller firmware may be executed by the NFC controller to control the antenna element to emit short-range RF signals. The RF signals may power a passive NFC tag (e.g., a microchip embedded in a sticker or wristband) to transmit stored data to the NFC circuitry 940, or initiate data transfer between the NFC circuitry 940 and another active NFC device (e.g., a smartphone or an NFC-enabled POS terminal) that is proximate to the platform 900.

The driver circuitry 946 may include software and hardware elements that operate to control particular devices that are embedded in the platform 900, attached to the platform 900, or otherwise communicatively coupled with the platform 900. The driver circuitry 946 may include individual drivers allowing other components of the platform 900 to interact with or control various input/output (I/O) devices that may be present within, or connected to, the platform 900. For example, driver circuitry 946 may include a display driver to control and allow access to a display device, a touchscreen driver to control and allow access to a touchscreen interface of the platform 900, sensor drivers to obtain sensor readings of sensor circuitry 921 and control and allow access to sensor circuitry 921, EMC drivers to obtain actuator positions of the EMCs 922 and/or control and allow access to the EMCs 922, a camera driver to control and allow access to an embedded image capture device, audio drivers to control and allow access to one or more audio devices.

The power management integrated circuitry (PMIC) 925 (also referred to as“power management circuitry 925”) may manage power provided to various components of the platform 900. In particular, with respect to the baseband circuitry 910, the PMIC 925 may control power- source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMIC 925 may often be included when the platform 900 is capable of being powered by a battery 930, for example, when the device is included in a UE XQ01, XQ02, XR101. In some embodiments, the PMIC 925 may control, or otherwise be part of, various power saving mechanisms of the platform 900. For example, if the platform 900 is in an

RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the platform 900 may power down for brief intervals of time and thus save power. If there is no data traffic activity for an extended period of time, then the platform 900 may transition off to an RRC Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The platform 900 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The platform 900 may not receive data in this state; in order to receive data, it must transition back to RRC Connected state. An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

A battery 930 may power the platform 900, although in some examples the platform 900 may be mounted deployed in a fixed location, and may have a power supply coupled to an electrical grid. The battery 930 may be a lithium ion battery, a metal-air battery, such as a zinc- air battery, an aluminum-air battery, a lithium-air battery, and the like. In some implementations, such as in V2X applications, the battery 930 may be a typical lead-acid automotive battery.

In some implementations, the battery 930 may be a“smart battery,” which includes or is coupled with a Battery Management System (BMS) or battery monitoring integrated circuitry. The BMS may be included in the platform 900 to track the state of charge (SoCh) of the battery 930. The BMS may be used to monitor other parameters of the battery 930 to provide failure predictions, such as the state of health (SoH) and the state of function (SoF) of the battery 930. The BMS may communicate the information of the battery 930 to the application circuitry 905 or other components of the platform 900. The BMS may also include an analog-to-digital (ADC) convertor that allows the application circuitry 905 to directly monitor the voltage of the battery 930 or the current flow from the battery 930. The battery parameters may be used to determine actions that the platform 900 may perform, such as transmission frequency, network operation, sensing frequency, and the like.

A power block, or other power supply coupled to an electrical grid may be coupled with the BMS to charge the battery 930. In some examples, the power block XS30 may be replaced with a wireless power receiver to obtain the power wirelessly, for example, through a loop antenna in the computer platform 900. In these examples, a wireless battery charging circuit may be included in the BMS. The specific charging circuits chosen may depend on the size of the battery 930, and thus, the current required. The charging may be performed using the Airfuel standard promulgated by the Airfuel Alliance, the Qi wireless charging standard promulgated by the Wireless Power Consortium, or the Rezence charging standard promulgated by the Alliance for Wireless Power, among others.

User interface circuitry 950 includes various input/output (I/O) devices present within, or connected to, the platform 900, and includes one or more user interfaces designed to enable user interaction with the platform 900 and/or peripheral component interfaces designed to enable peripheral component interaction with the platform 900. The user interface circuitry 950 includes input device circuitry and output device circuitry. Input device circuitry includes any physical or virtual means for accepting an input including, inter alia, one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphones, scanner, headset, and/or the like. The output device circuitry includes any physical or virtual means for showing information or otherwise conveying information, such as sensor readings, actuator position(s), or other like information. Output device circuitry may include any number and/or combinations of audio or visual display, including, inter alia, one or more simple visual outputs/indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touchscreens (e.g., Liquid Chrystal Displays (LCD), LED displays, quantum dot displays, projectors, etc.), with the output of characters, graphics, multimedia objects, and the like being generated or produced from the operation of the platform 900. The output device circuitry may also include speakers or other audio emitting devices, printer(s), and/or the like. In some embodiments, the sensor circuitry 921 may be used as the input device circuitry (e.g., an image capture device, motion capture device, or the like) and one or more EMCs may be used as the output device circuitry (e.g., an actuator to provide haptic feedback or the like). In another example, NFC circuitry comprising an NFC controller coupled with an antenna element and a processing device may be included to read electronic tags and/or connect with another NFC-enabled device. Peripheral component interfaces may include, but are not limited to, a non-volatile memory port, a USB port, an audio jack, a power supply interface, etc.

Although not shown, the components of platform XS200 may communicate with one another using a suitable bus or interconnect (IX) technology, which may include any number of technologies, including ISA, EISA, PCI, PCIx, PCIe, a Time-Trigger Protocol (TTP) system, a FlexRay system, or any number of other technologies. The bus/IX may be a proprietary bus/IX, for example, used in a SoC based system. Other bus/IX systems may be included, such as an I2C interface, an SPI interface, point-to-point interfaces, and a power bus, among others.

Figure 10 is a block diagram illustrating components, according to some example embodiments, able to read instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically, Figure 10 shows a diagrammatic representation of hardware resources 1000 including one or more processors (or processor cores) 1010, one or more memory /storage devices 1020, and one or more communication resources 1030, each of which may be communicatively coupled via a bus 1040. As used herein, the term“computing resource,”“hardware resource,” etc., may refer to a physical or virtual device, a physical or virtual component within a computing environment, and/or a physical or virtual component within a particular device, such as computer devices, mechanical devices, memory space, processor/CPU time and/or processor/CPU usage, processor and accelerator loads, hardware time or usage, electrical power, input/output operations, ports or network sockets, channel/link allocation, throughput, memory usage, storage, network, database and applications, and/or the like. For embodiments where node virtualization (e.g., NFV) is utilized, a hypervisor 1002 may be executed to provide an execution environment for one or more network slices/sub-slices to utilize the hardware resources 1000. A“virtualized resource” may refer to compute, storage, and/or network resources provided by virtualization infrastructure to an application, device, system, etc.

The processors 1010 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereol) may include, for example, a processor 812 and a processor 1014.

The memory /storage devices 1020 may include main memory, disk storage, or any suitable combination thereof. The memory /storage devices 1020 may include, but are not limited to, any type of volatile or nonvolatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), Flash memory, solid-state storage, etc.

The communication resources 1030 may include interconnection or network interface components or other suitable devices to communicate with one or more peripheral devices 1004 or one or more databases 1006 via a network 1008. For example, the communication resources 830 may include wired communication components (e.g., for coupling via a universal serial bus (USB)), cellular communication components, NFC components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components. As used herein, the term“network resource” or“communication resource” may refer to computing resources that are accessible by computer devices via a communications network. The term “system resources” may refer to any kind of shared entities to provide services, and may include computing and/or network resources. System resources may be considered as a set of coherent functions, network data objects or services, accessible through a server where such system resources reside on a single host or multiple hosts and are clearly identifiable.

Instructions 1050 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least any of the processors 1010 to perform any one or more of the methodologies discussed herein. The instructions 1050 may reside, completely or partially, within at least one of the processors 1010 (e.g., within the processor’s cache memory), the memory /storage devices 1020, or any suitable combination thereof. Furthermore, any portion of the instructions 1050 may be transferred to the hardware resources 1000 from any combination of the peripheral devices 1004 or the databases 1006. Accordingly, the memory of processors 1010, the memory /storage devices 1020, the peripheral devices 1004, and the databases 1006 are examples of computer-readable and machine-readable media.

For one or more embodiments, at least one of the components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the example section below. For example, the baseband circuitry as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below. For another example, circuitry associated with a UE, base station, network element, etc. as described above in connection with one or more of the preceding figures may be configured to operate in accordance with one or more of the examples set forth below in the example section.

EXAMPLES

Example 1 may include a method comprising: receiving a power-saving signal transmitted in a first downlink (DL) slot; identifying, based on the power saving signal, activation of a search space set; and monitoring, based on identification of the activation, physical downlink control channel (PDCCH) candidates in the search space set.

Example 2 may include the method of example 1 or some other example herein, further comprising determining, based on the power-saving signal, a bandwidth part indicator, a search space set indicator, cross-slot scheduling timing for physical downlink shared channel and physical uplink shared channel, or a sleep duration. Example 3 may include the method of example 2 or some other example herein, wherein the power-saving signal includes a bandwidth part indicator field to indicate an active bandwidth part (BWP) at a start of an active time of a discontinuous reception (DRX) cycle, and the UE is to determine the bandwidth part indicator based on a value of the bandwidth part indicator field.

Example 4 may include the method of example 1 or some other example herein, further comprising determining, based on radio resource control signaling, an offset between the power saving signal and a start of an active bandwidth part that includes the search space set.

Example 5 may include the method of any one of examples 1-4 or some other example herein, wherein the power-saving signal includes a search space set indicator field (SSSIF) to indicate search space set activation/deactivation information.

Example 6 may include the method of example 5 or some other example herein, further comprising: receiving higher-layer signaling to configure a plurality of search space sets, wherein the SSSIF is to indicate that one or more search spaces of the plurality of search space sets is to be activated or deactivated.

Example 7 may include the method of example 6 or some other example herein, wherein the SSSIF is a bitmap field that includes a bit corresponding to each of the plurality of search space sets, wherein a setting of an individual bit is to indicate whether a corresponding search space set is activated or deactivated.

Example 8 may include the method of any one of examples 1-7 or some other example herein, wherein the power-saving signal includes downlink control information (DCI) transmitted in a configured search space set with a predefined aggregation level and the instructions, when executed, further cause the UE to monitor the configured search space set upon activation of a bandwidth part that includes the configured search space set.

Example 9 may include the method of any one of examples 1-7 or some other example herein, further comprising: identifying, based on another power-saving signal, deactivation of the search space set; and ceasing, based on said identification of deactivation, monitoring of PDCCH candidates in the search space set.

Example 10 may include a method comprising: receiving configuration information to configure a plurality of search space sets (SSSs) or bandwidth parts (BWPs) of a serving cell; receiving a media access control (MAC) control element (CE) from an access node; and activating or deactivating an SSS or BWP of the plurality of SSSs or BWPs based on the MAC CE. Example 11 may include the method of example 10 or some other example herein, wherein the MAC CE includes a MAC packet data unit (PDU) subheader with a dedicated logical channel identifier (LCID).

Example 12 may include the method of example 11 or some other example herein, wherein the MAC PDU subheader includes an activate/deactivate field to indicate whether the MAC CE is to activate or deactivate the SSS or BWP; a serving cell identifier field to indicate an identity of the serving cell; a BWP identifier field to indicate a BWP identifier of a downlink bandwidth part to which the MAC CE applies; or an SSS identifier field to indicate an index of the SSS.

Example 13 may include the method of example 11 or some other example herein, wherein the configuration information is to configure an SSS group (SSSG) including the SSS and at least one other SSS of the plurality of SSSs and the MAC PDU subheader includes an SSSG identifier field to indicate an index of the SSSG.

Example 14 may include the method of example 13 or some other example herein, wherein the configuration information is to configure a plurality of SSSGs and the SSSG identifier field includes a plurality of bits respectively corresponding to the plurality of SSSGs, wherein individual bits are to indicate an activation or deactivation state of a respective SSSG.

Example 15 may include the method of any one of examples 10-14 or some other example herein, further comprising processing radio resource control signaling to receive the configuration information.

Example 16 may include a method comprising: receiving downlink control information (DCI); selecting a slot offset value from the set of slot offset values based on the DCI; detecting physical downlink control channel (PDCCH) that schedules a physical uplink shared channel (PUSCH) or a physical downlink shared channel (PDSCH); and determining a slot of the scheduled PUSCH or PDSCH based on the slot offset value.

Example 17 may include the method of example 16 or some other example herein, further comprising receiving the DCI in wake-up signal or a go-to-sleep signal.

Example 18 may include the method of example 16 or some other example herein, wherein the set of slot offset values include a Ko value that provides a slot offset for physical downlink shared channel (PDSCH) reception or a Ki value that provides the slot offset for physical uplink shared channel (PUSCH) reception. Example 19 may include the method of example 16 or some other example herein, further comprising selecting a default slot offset value and determining slots of scheduled PUSCH or PDSCH based on the default slot offset value until receipt of the DCI.

Example 20 may include the method of example 19 or some other example herein, further comprising determining the default slot offset value based on a pre-configuration or dynamic indication in a wake-up signal.

Example 21 may include the method of any one of example 16-20, further comprising: receiving a radio resource control message to configure the set of slot offset values; and storing the set of slot offset values in the memory.

Example 22 may include an apparatus comprising means to perform one or more elements of a method described in or related to any of examples 1-21, or any other method or process described herein.

Example 23 may include one or more non-transitory computer-readable media comprising instructions to cause an electronic device, upon execution of the instructions by one or more processors of the electronic device, to perform one or more elements of a method described in or related to any of examples 1-21, or any other method or process described herein.

Example 24 may include an apparatus comprising logic, modules, or circuitry to perform one or more elements of a method described in or related to any of examples 1-21, or any other method or process described herein.

Example 25 may include a method, technique, or process as described in or related to any of examples 1-21, or portions or parts thereof.

Example 26 may include an apparatus comprising: one or more processors and one or more computer readable media comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform the method, techniques, or process as described in or related to any of examples 1-21, or portions thereof.

Example 27 may include a signal as described in or related to any of examples 1-21, or portions or parts thereof.

Example 28 may include a signal in a wireless network as shown and described herein.

Example 29 may include a method of communicating in a wireless network as shown and described herein.

Example 30 may include a system for providing wireless communication as shown and described herein.

Example 31 may include a device for providing wireless communication as shown and described herein. Any of the above described examples may be combined with any other example (or combination of examples), unless explicitly stated otherwise. The foregoing description of one or more implementations provides illustration and description, but is not intended to be exhaustive or to limit the scope of embodiments to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of various embodiments.

Claims

Claims What is claimed is:

1. One or more computer-readable media having instructions that, when executed by one or more processors, cause a user equipment (UE) to:

receive a power-saving signal transmitted in a first downlink (DL) slot;

identify, based on the power saving signal, activation of a search space set; and monitor, based on identification of the activation, physical downlink control channel (PDCCH) candidates in the search space set.

2. The one or more computer-readable media of claim 1, wherein the instructions, when executed, further cause the UE to determine, based on the power-saving signal, a bandwidth part indicator, a search space set indicator, cross-slot scheduling timing for physical downlink shared channel and physical uplink shared channel, or a sleep duration.

3. The one or more computer-readable media of claim 2, wherein the power-saving signal includes a bandwidth part indicator field to indicate an active bandwidth part (BWP) at a start of an active time of a discontinuous reception (DRX) cycle, and the UE is to determine the bandwidth part indicator based on a value of the bandwidth part indicator field.

4. The one or more computer-readable media of claim 1, wherein the instructions, when executed, further cause the UE to determine, based on radio resource control signaling, an offset between the power-saving signal and a start of an active bandwidth part that includes the search space set.

5. The one or more computer-readable media of claim 1, wherein the power-saving signal includes a search space set indicator field (SSSIF) to indicate search space set activation/deactivation information.

6. The one or more computer-readable media of claim 5, wherein the instructions, when executed, further cause the UE to:

receive higher-layer signaling to configure a plurality of search space sets,

wherein the SSSIF is to indicate that one or more search spaces of the plurality of search space sets is to be activated or deactivated.

7. The one or more computer-readable media of claim 6, wherein the SSSIF is a bitmap field that includes a bit corresponding to each of the plurality of search space sets, wherein a setting of an individual bit is to indicate whether a corresponding search space set is activated or deactivated.

8. The one or more computer-readable media of any one of claims 1-7, wherein the power-saving signal includes downlink control information (DCI) transmitted in a configured search space set with a predefined aggregation level and the instructions, when executed, further cause the UE to monitor the configured search space set upon activation of a bandwidth part that includes the configured search space set.

9. The one or more computer-readable media of any one of claims 1-7, wherein the instructions, when executed, further cause the UE to: identify, based on another power-saving signal, deactivation of the search space set; and cease, based on said identification of deactivation, monitoring of PDCCH candidates in the search space set.

10. One or more computer-readable media having instructions that, when executed by one or more processors of a user equipment (UE), cause the UE to:

receive configuration information to configure a plurality of search space sets (SSSs) or bandwidth parts (BWPs) of a serving cell;

receive a media access control (MAC) control element (CE) from an access node; and activate or deactivate an SSS or BWP of the plurality of SSSs or BWPs based on the MAC CE.

11. The one or more computer readable media of claim 10, wherein the MAC CE includes a MAC packet data unit (PDU) subheader with a dedicated logical channel identifier (LCID).

12. The one or more computer readable media of claim 11, wherein the MAC PDU subheader includes an activate/deactivate field to indicate whether the MAC CE is to activate or deactivate the SSS or BWP; a serving cell identifier field to indicate an identity of the serving cell; a BWP identifier field to indicate a BWP identifier of a downlink bandwidth part to which the MAC CE applies; or an SSS identifier field to indicate an index of the SSS.

13. The one or more computer-readable media of claim 11, wherein the configuration information is to configure an SSS group (SSSG) including the SSS and at least one other SSS of the plurality of SSSs and the MAC PDU subheader includes an SSSG identifier field to indicate an index of the SSSG.

14. The one or more computer-readable media of claim 13, wherein the configuration information is to configure a plurality of SSSGs and the SSSG identifier field includes a plurality of bits respectively corresponding to the plurality of SSSGs, wherein individual bits are to indicate an activation or deactivation state of a respective SSSG.

15. The one or more computer-readable media of any one of claims 10-14, wherein the instructions, when executed, further cause the UE to process radio resource control signaling to receive the configuration information.

16. An apparatus comprising:

memory to store a set of slot offset values; and

processing circuitry coupled with the memory to:

receive downlink control information (DCI);

select a slot offset value from the set of slot offset values based on the DCI; detect physical downlink control channel (PDCCH) that schedules a physical uplink shared channel (PUSCH) or a physical downlink shared channel (PDSCH); and determine a slot of the scheduled PUSCH or PDSCH based on the slot offset value.

17. The apparatus of claim 16, wherein the processing circuitry is further to receive the DCI in wake-up signal or a go-to-sleep signal.

18. The apparatus of claim 16, wherein the set of slot offset values include a Ko value that provides a slot offset for physical downlink shared channel (PDSCH) reception or a Ki value that provides the slot offset for physical uplink shared channel (PUSCH) reception.

19. The apparatus of claim 16, wherein the processing circuitry is to select a default slot offset value and determine slots of scheduled PUSCH or PDSCH based on the default slot offset value until receipt of the DCI.

20. The apparatus of claim 19, wherein the processing circuitry is to determine the default slot offset value based on a pre-configuration or dynamic indication in a wake-up signal.

21. The apparatus of any one of claims 16-20, wherein the processing circuitry is further to:

receive a radio resource control message to configure the set of slot offset values; and

store the set of slot offset values in the memory.