EP3871256A1

EP3871256A1 - Sensing device and method of designing a sensing device

Info

Publication number: EP3871256A1
Application number: EP19791351.0A
Authority: EP
Inventors: Alessandro Michel BRUNETTI
Original assignee: Oxford University Innovation Ltd
Current assignee: Oxford University Innovation Ltd
Priority date: 2018-10-26
Filing date: 2019-10-18
Publication date: 2021-09-01
Also published as: GB201817489D0; WO2020084284A1

Abstract

A sensing device (56) has multiple rows of sensing elements (112). Each row has multiple sensing elements, with each sensing element having an active area (118) and a circuit element (120), and each circuit element having multiple components for processing signals captured by the active area of the sensing element. The circuit elements extend linearly in the direction along the respective sensing element rows. The active areas of the sensing elements in one sensing element row are offset in the direction along the sensing element row from the active areas of the sensing elements in the adjacent row.

Description

Sensing Device and Method of Designing A Sensing Device

This invention relates to a method of designing a sensing device, in particular to a method of designing an image sensor to maximise the fill factor of the image sensor.

Image sensors, e.g. implemented using complementary metal oxide semiconductor (CMOS) technology, may be used for a wide range of applications to detect light for the capture of images. Such image sensors typically include plural (e.g.

substantially identical)“pixels” arranged in a tessellating array. Each pixel occupies an area of the image sensor on which light to be detected may be incident. Such pixels are typically square so that they tessellate easily. Each pixel includes a light sensitive area which is sensitive to incident light and an inactive area which is used to read out the amount of light falling on the light sensitive area. Any light that is incident upon the inactive area (i.e. not falling on the photodiode) will not be detected. CMOS image sensors often suffer from poor performance, particularly in low light conditions and limited dynamic range. The limited dynamic range may depend on the pixel architecture and the operation of the image sensor.

To improve the pixel architecture, the ratio of the light sensitive area to the total area of the pixel may be maximised, which thus maximises the capability of the image sensor to collect light. This ratio is known as the“fill factor” and provides a measure of the capability of a pixel (and thus the image sensor as a whole) to collect light. The fill factor may be maximised by taking a pixel and making the non-sensitive area that is dedicated to transistors as small as possible, thus maximising the sensitive area that can be occupied by the photodiode. Such a pixel can then be used repeatedly in an array across the whole of the image sensor, thus maximising the fill factor of the image sensor (for a given pixel pitch). However, owing to the constraints of having to provide a repeatable array of pixels in an image sensor, there appears to be little scope for improving the fill factor.

The aim of the present invention is to provide an improved sensing device layout through an improved method of designing a sensing device.

When viewed from a first aspect the invention provides a method of designing the layout of a sensing device, wherein the sensing device comprises a plurality of sensing elements, each sensing element comprising an active area for detecting the incidence of a particle and a circuit element comprising a plurality of components for processing signals captured by the active area of the sensing element, wherein each component comprises a plurality of terminals;

the method comprising, for a sensing element of the sensing device:

identifying, among the plurality of components in the circuit element of the sensing element, one or more pairs of terminals each having a common voltage;

determining a path through the plurality of components in the circuit element such that the path directly connects the terminals in one or more of the pairs of terminals identified as having a common voltage; and

arranging a layout of the circuit element in the sensing element according to the determined path, wherein the plurality of components are arranged in the layout of the circuit element such that the one or more pairs of terminals directly connected by the determined path are formed as a shared terminal.

The present invention provides a method of designing a sensing device (e.g. an image sensor) layout. The sensing device includes a plurality of sensing elements (e.g. pixels) that each has an active area and some (e.g. readout) circuitry in the form of a circuit element that includes a plurality of (connected) components (e.g. transistors). The components each include (e.g. a pair of) terminals. The circuitry of a sensing element is provided to process (e.g. read out) signals received by the sensing element, e.g. when a particle to be detected is incident upon the sensing element.

The method of designing the sensing device layout includes, for a sensing element of the sensing device, the step of identifying pairs of terminals in the components in the circuit element of the sensing element which have common voltages. Thus the two terminals from the different components in the pair that are identified have the same operating voltage. It will be appreciated that terminals from different components having the same voltage may be combined into a single, shared terminal without affecting the operation of the circuit element.

Once such pair(s) of terminals have been identified, a path through the components is determined such that (if possible) the path includes, and directly connects (e.g. avoiding any intermediate components), (e.g. each of the) one or more of the pairs of terminals that have been identified as having a common voltage. Using this determined path, the layout of the circuit element is then arranged. The layout is such that a shared terminal is formed for (e.g. each of) the one or more pairs of terminals that are directly connected by the determined path.

It will be appreciated that by identifying common terminal voltages for the components in the circuit element of a sensing element and determining a (e.g. optimum) path through the components in the circuit element, the terminals of the components in an identified pair may be combined such that a shared terminal is formed. By forming shared terminals which join together terminals of different components, the area of a sensing element occupied by the (inactive) circuit element may be reduced. This allows the sensitive area of the sensing element (occupied by an active area, e.g. a photodiode) to be maximised, thus helping to maximise the fill factor of the sensing element and thus of the sensing device (e.g. for a given sensing element pitch).

The Applicant has appreciated that by discarding the constraint of the sensing elements in a sensing device having to be square (which was assumed to help maximise the overall fill factor of an image sensor owing to the tessellating nature of square pixels), and instead identifying terminals that can be combined together in order to reduce the area occupied by the components in the circuit element, this may help to provide an improved fill factor for the sensing device. Thus it will be seen that the present invention provides a sensing element layout technique that increases the capability of a sensing device to detect incident particles (e.g. collect light). The sensing device may comprise any suitable and desired type of sensing device that comprises a plurality (e.g. an array or matrix) of sensing elements, e.g. for determining the position at which a particle to be detected is incident upon the (e.g. active area) of the sensing device. Preferably the sensing device comprises a device in which it is desired for the active area to be maximised relative to the inactive area. Thus, for example, the sensing device may comprise a particle detector for detecting incident particles, a photodetector (e.g. a single-photon avalanche diode) or a microelectromechanical systems (MEMS) detector.

In a preferred embodiment the sensing device comprises an image sensor for detecting light (i.e. photons) incident upon the sensing element of the image sensor. The image sensor being designed may be any suitable and desired type of image sensor. Preferably the image sensor comprises a complementary metal oxide semiconductor (CMOS) image sensor.

In one embodiment (e.g. when the sensing device comprises an image sensor), preferably the plurality of sensing elements comprises a plurality of pixels.

Preferably the active area comprises a light sensitive area, e.g. a photodiode or a single-photon avalanche diode.

The plurality of components of the circuit element may comprise any suitable and desired components for processing (e.g. reading out) the signals captured by the active area of the sensing element. For example, the components may comprise one or more of capacitor(s), storage node(s), etc.. These components may be used for any suitable and desired functions for processing the signals captured by the active area of the sensing element, e.g. to perform high dynamic range operations, to provide local (e.g. in pixel) memory, to perform full well modulation, to act as an anti-blooming gate, to provide multiple readouts, etc..

In a preferred embodiment the plurality of components comprises, inter alia, a plurality of transistors. The transistors are preferably arranged to readout and/or reset the sensing element but may perform other functions, to perform high dynamic range operations, to provide local (e.g. in pixel) memory, to perform full well modulation, to act as an anti-blooming gate, to provide multiple readouts, etc.. The sensing device may comprise any suitable and desired number of sensing elements(e.g. have any suitable and desired sensing element resolution). In one embodiment the sensing device has a total number of sensing elements (e.g.

pixels) that is greater than 1 megapixel, e.g. greater than 2 megapixels, e.g. greater than 4 megapixels, e.g. greater than 8 megapixels.

The plurality of sensing elements may be any suitable and desired shape. While the sensing elements may be rectangular (e.g. square) as a result of the process of designing the sensing device, in one embodiment the sensing elements are not rectangular. Thus preferably the method comprises not imposing a rectangular shape as a constraint on the shape of the sensing elements when designing the sensing device layout.

The plurality of sensing elements may (e.g. all) be the same shape and/or size. However, embodiments are envisaged in which the plurality of sensing elements may not all be the same shape and/or size. For example the plurality of sensing elements may comprise at least two different shapes and/or sizes of sensing elements, e.g. which tessellate together. Thus preferably the plurality of sensing elements have respective shape(s) and/or size(s) such that they tessellate together to form the sensing device layout.

The plurality of sensing elements may comprise any suitable and desired type of sensing elements, e.g. pixels implemented using CMOS technology. In particular, the circuit element of each sensing element may comprise any suitable and desired set of components (including the plurality of transistors). For example, each sensing element may comprise a“3T” pixel. However, preferably each sensing element comprises a“4T” pixel. Thus preferably each circuit element comprises one or more (e.g. all) of: a transfer (transistor) gate, a reset (transistor) gate, a row selection (transistor) gate, a source-follower readout transistor, a supply voltage and an output contact.

Preferably the plurality of components (e.g. transistors) in the circuit element comprises metal oxide semiconductor field effect transistors (MOSFETs). It will be appreciated that this helps to provide CMOS-based pixels. In another embodiment the plurality of components comprises thin-film transistors. Preferably each sensing element (e.g. each circuit element) comprises a floating diffusion. The floating diffusion stores charge for readout of the active area.

Preferably the transfer transistor and the reset transistor are connected to the floating diffusion. Preferably the floating diffusion is connected between the transfer transistor and the reset transistor. Preferably the (e.g. gate of the) source-follower readout transistor is connected to the floating diffusion.

The terminals of each transistor (which are to be paired with those of other transistors in the circuit element) preferably form the source and drain terminals of each transistor.

The type of sensing element (e.g. pixel) to be used for the sensing device (e.g. image sensor) may then be used as the input for the method of designing the layout of the sensing device. Preferably the method comprises determining the (e.g.

relative) voltage of the terminals in the plurality of components in the circuit element. This then enables, for the type of sensing elements forming the sensing device, pairs of terminals having common voltages to be identified. The terminals (and the components and the sensing element) may comprise any suitable and desired type of terminals (and thus any suitable and desired type of components and sensing element). As outlined above, preferably the sensing elements comprise CMOS pixels and the components comprise MOSFETs. Thus preferably the terminals comprise diffusion terminals and thus, in these

embodiments, the shared terminals comprise shared diffusions.

The one or more pairs of terminals each having a common voltage may be identified, among the plurality of components in the circuit element of the sensing element, in any suitable and desired way. In one embodiment a pair of terminals from different components in the circuit element having a common voltage (i.e. the same voltage for each of the terminals in the pair) is identified by identifying a source terminal of one transistor and a drain terminal of another transistor having a common voltage. Only one pair of terminals having a common voltage may be identified but preferably a plurality of pairs of terminals, each (pair) having a common voltage, are identified. When a plurality of pairs of terminals are identified, it may not be important as to the relative voltages of different pairs; what is important is that for each pair of terminals, the voltage at the terminals for that pair is common (the same).

Preferably the method comprises maximising the number of pairs of terminals (identified as) having a common voltage in the pair. This helps to maximise the number of terminals which may be combined, thus helping to reduce the area of the sensing element occupied by the components.

In one embodiment the sensing elements of the sensing device may be treated individually such that pairs of terminals having the same voltage are only identified with each sensing element. However, in one embodiment, the method comprises identifying, among the plurality of components in the circuit elements of two or more sensing elements, one or more pairs of terminals each having a common voltage (e.g. where the pair of terminals comprises a terminal from each of two different sensing elements). This allows two or more sensing elements to be connected together, e.g. via their output contacts and/or having a shared terminal across the sensing elements, which may lead to further reduction in size of the circuit elements. In this embodiment the method preferably comprises determining the path through the plurality of components in the circuit elements of two or more sensing elements and then arranging the layout of the circuit elements of the two or more sensing elements according to the determined path.

In one embodiment the sensing element (e.g. pixel) may comprise a plurality of active areas (e.g. photodiodes) and a (single) circuit element for reading out the plurality of active areas (e.g. photodiodes). Such a“shared” sensing element (e.g. a 4T 4-shared pixel comprising four photodiodes and shared circuitry) may be treated in the same manner as a sensing element with a single active area and

accompanying circuit element.

The path through the plurality of the components in the circuit element(s), such that the path directly connects the terminals in one or more of the pairs of terminals identified as having a common voltage, may be determined in any suitable and desired way. Preferably an“optimal” path through (e.g. each of) the one or more pairs of terminals having been identified as having a common voltage is

determined. Thus preferably the method comprises optimising the path through the plurality of components in the circuit element(s) such that the path directly connects the terminals in each of the one or more of the pairs of terminals identified as having a common voltage.

The path may be optimised in any suitable and desired way. In a preferred embodiment the path is optimised to maximise the number of pairs of terminals identified as having a common voltage that the path passes through, e.g. to maximise the number of pairs of terminals that are able to be formed as shared terminals in the layout of the circuit element(s).

In one embodiment, in order to optimise the path, the method comprises (e.g. setting up and) evaluating a cost function. The cost function may be evaluated as a function of any suitable and desired variables, e.g. the number of pairs of terminals having a common voltage (which is preferably maximised) and thus the number of shared terminals in the layout of the circuit element, the number of discrete terminals in the layout of the circuit element(s) (which is preferably minimised, to maximise the number of shared terminals), the area (of the sensing element) occupied by the plurality of components (and thus the circuit element(s)) (which is preferably minimised).

Thus the cost function may be evaluated both to determine the path through the plurality of components in the circuit element and to arrange the layout of the circuit element(s).

The cost function may be set up dependent upon (and therefore be different for) the particular architecture of the circuit element(s). Thus, for example, the cost function may depend on the type of sensing element (e.g. 3T, 4T, 8T, etc.) in the sensing device. As an example, for a 4T pixel architecture, one path through the

components of the circuit element may be, from the photodiode: the transfer transistor gate, the floating diffusion, the reset transistor gate, the supply voltage, the source-follower readout transistor, the row selection transistor gate and the output contact.

Preferably an extremum (e.g. maximum or minimum) of the cost function is determined (e.g. the cost function is minimised or maximised, depending on the variables used), to optimise the path and/or the layout.

The path determined (e.g. in any of the ways outlined above) may pass through the plurality of components in the circuit element(s) in any suitable and desired way. In a preferred embodiment the path passes through (e.g. two or more of, e.g. three or more of, e.g. four or more of, e.g. all of) the plurality of the components in the circuit element(s) in series. Thus preferably the path through the components is (at least partly) a linear path. This helps to simplify the path through the components and the layout of the circuit element(s), which thus helps to reduce the area occupied by the circuit element(s) in the sensing element(s).

Thus the step of optimising the path may comprise constraining the path to pass through (e.g. two or more of, e.g. three or more of, e.g. four or more of, e.g. all of) the plurality of the components in the circuit element(s) in series. Preferably the step of optimising the path comprises constraining the path to pass through the floating diffusion in the circuit element.

The layout of the circuit element(s) in the sensing element(s), according to the determined path, may be arranged in any suitable and desired way. As has been discussed above, preferably the layout is arranged without imposing the constraint that the sensing element(s) are required to be rectangular (e.g. square) in shape. Instead, the layout may be arranged such that the sensing element(s) have any suitable and desired shape, preferably a shape that tessellates over the sensing device.

Preferably the layout of the circuit element is arranged to maximise the fill factor of the sensing element (e.g. for a given sensing element pitch), e.g. the layout is arranged to minimise the area occupied by the circuit element of the sensing element. Thus preferably the cost function is optimised to maximise the fill factor of the sensing element, e.g. the cost function is optimised to minimise the area occupied by the circuit element in the layout of the sensing element.

As the path has been determined preferably to maximise the number of pairs of terminals identified as having a common voltage that the path passes through, preferably the layout of the circuit element is arranged to maximise the number of pairs of terminals which are formed as shared terminals. Preferably the number of pairs of terminals formed as shared terminals is equal to the number of pairs of terminals identified as each having a respective common voltage. Thus preferably the method (e.g. the step of arranging the layout of the circuit element) comprises forming a shared terminal for each of the one or more pairs of terminals directly connected by the determined path (i.e. each of the one or more pairs of terminals having a common voltage).

The layout of the circuit element may be arranged to match the topography of the determined path. Thus preferably the circuit element has a linear (e.g. straight) layout, e.g. the components in the circuit element may be arranged in a straight line. It will be appreciated that in a (e.g. conventional) square sensing element, arranging the circuit element in this configuration would not help in trying to reduce the area occupied by the circuit element as it would be unlikely to be able to fit a linear set of components into a square sensing element. However, when there is preferably not the constraint of a rectangular shaped sensing element, a linear circuit element may help to reduce the area occupied by the circuit element.

When the sensing element (e.g. the circuit element thereof) comprises a floating diffusion, preferably the layout is arranged such that the floating diffusion is arranged according to its position in the determined path, e.g. between two or more components (e.g. transistors). Preferably the floating diffusion is formed as part of a shared (e.g. diffusion) terminal, e.g. with the terminals of the components (e.g. transistors) that the floating diffusion is positioned between in the (e.g. determined path through the) circuit element. Thus preferably the floating diffusion is formed as part of a shared terminal with the (e.g. transistor) terminals with which it has a common voltage. Preferably the method comprises arranging the layout of the sensing element according to the determined path (which preferably comprises arranging the layout of the circuit element and, e.g., arranging the layout (e.g. size and shape) of the active area). Preferably the step of arranging the layout of the sensing element (and arranging the layout of the active area) comprises one or more (e.g. all) of:

arranging the position of the active area relative to the circuit element in the sensing element, arranging the size of the active area relative to the circuit element in the sensing element and arranging the shape of the active area in the sensing element.

The position, size and/or shape of the active area (e.g. photodiode) may be determined in any suitable and desired way. For example, the active area may simply be placed in the space remaining in the sensing element once the layout of the circuit element has been arranged. However, preferably the size and/or shape of the active area is chosen to provide a desired sensing element size, e.g. for a desired sensing element pitch.

In a preferred embodiment the method comprises arranging the layout of the plurality of sensing elements in the sensing device, e.g. once the layout of the sensing element has been determined. Preferably the position, size and/or shape of the active area and/or the circuit element (e.g. in each sensing element) is chosen such that the sensing element tessellates with other (e.g. identical) sensing elements across the sensing device (the sensing elements may be reflected and/or rotated relative to each other to achieve this tessellation). Thus preferably the position, size and/or shape of the active area and/or the circuit element is chosen to provide a desired sensing element shape.

The cost function may, for example, be optimised to provide a particular shape and/or size of sensing element and/or to optimise the shape and/or size of the sensing element (and/or of the circuit element and/or active area) to tessellate over the sensing device, e.g. to maximise the fill factor of the sensing device as a whole. Thus, for example, the layout of the sensing element and the plurality of elements in the sensing device may be optimised together, rather than one after each other.

The active area may, for example, be (substantially) rectangular or (substantially) pentagonal. When the active area is (substantially) pentagonal, preferably at least two (e.g. three) of the corners (e.g. adjacent corners) of the active area are right angles. It will be appreciated that the active area may be any suitable and desired shape, e.g. to fill the available space.

Preferably the layout of the sensing device is arranged such that the sensing elements tessellate over the sensing device in a regular (e.g. periodic) array, e.g. having one or more translational degrees of symmetry. This may be achieved with one or more sensing element shapes of any suitable and desired shape and/or size. The constraint of the sensing elements being arranged in a regular (e.g.

tessellating) array is preferably implemented when optimising the layout of the sensing device using the cost function.

The base unit which is repeated in the regular array may be a single sensing element or may be a group of plural (e.g. two, four or eight) sensing elements. The sensing elements in the group may all be the same orientation or may, for example, be rotated and/or reflected versions of each other. This may help to form a group of sensing elements which may then be used to tessellate over the sensing device.

In one embodiment the layout of the sensing element is arranged such that the circuit element extends linearly from the (e.g. edge of the) active area. The circuit element may extend from the centre of an edge of the active area, e.g. such that the sensing element resembles a lollipop. Alternatively the circuit element may extend from the corner of the active area, e.g. such that the sensing element resembles a flag and flagpole. Thus the tessellating sensing elements may be (substantially) identical sensing elements or the tessellating sensing elements may be (substantially) symmetrical to each other.

In some embodiments, as was described above with reference to the step of determining the path through the circuit element, two (or more) sensing elements may be connected together, e.g. via their outputs, and the path is determined through the connected circuit elements. Then, when the layout of these connected circuit elements (and, e.g., sensing elements) is arranged, preferably the layout is arranged according to the determined path for the connected circuit elements (and thus, for example, eight transistors (from two 4T pixels) may be arranged in a row). This may allow the forming of (and preferably the method comprises forming) a shared terminal from the terminal in each circuit element (i.e. the terminals that are directly connected to (e.g. closest to) the respective outputs of the circuit elements). This is because the outputs of the circuit elements are preferably operated at a common voltage.

Along with appreciating that connecting the circuit elements of two (or more) sensing elements in this way helps to save space by being able to form a further shared terminal, the Applicant has appreciated that this configuration of connected sensing elements may also help with the tessellating of the sensing elements over the sensing device.

In one example, the 8T double pixel is arranged with a layout that has the pixels positioned either side of the linear connected circuit elements (e.g. in a“dumbbell” shape). The circuit elements may extend from the centre or the corner of the respective active areas (e.g. photodiodes), as outlined above. This configuration may be repeated in the direction in which the circuit elements extend, such that two active areas are arranged back to back. Thus preferably the sensing device comprises a plurality of rows of sensing elements, wherein each row comprises a plurality of sensing elements.

It will be appreciated that such sensing elements may be tessellated across the sensing device by placing sensing elements in the next row which are offset from the sensing elements in the other row, i.e. preferably the active areas of the sensing elements in one row are offset in the direction along the row from the active areas of the sensing elements in the adjacent row. For example the active areas of these sensing elements may be positioned adjacent to the circuit elements of the sensing elements in the other row, e.g. with the active areas of sensing elements in one row nesting into the vacant area next to the circuit elements (owing to the width of the circuit element being less than the width of the active area).

The (e.g. above described) arrangement of the layout of tessellating sensing elements is preferably repeated (periodically) across the sensing device. This preferably results in an array of sensing elements in which the sensing elements in adjacent rows are offset (staggered) from each other, e.g. by half a sensing element pitch in this direction. While this is not a regular square array, this (e.g. hexagonal-like array) still provides a sensing device having a defined sensing element pitch and thus a sensing device that preferably has pitch-defined row control and column readout, e.g. such that the sensing elements may be assigned a position which is equivalent to that of a rectangular (e.g. square) sensing element. Furthermore, it will be appreciated that a staggered sensing element array helps to provide position discrimination (e.g. better than a square array) in an array (e.g. image), e.g. when a boundary lies along the line of a row or column of the array, owing to the staggered sensing elements straddling this boundary.

Such a sensing device is considered novel and inventive in its own right and thus when viewed from a further aspect the invention provides a sensing device comprising a plurality of sensing element rows, each sensing element row comprising a plurality of sensing elements, each sensing element comprising an active area and a circuit element, each circuit element comprising a plurality of components for processing signals captured by the active area of the sensing element;

wherein the circuit elements extend linearly in the direction along the respective sensing element rows; and

wherein the active areas of the sensing elements in one sensing element row are offset in the direction along the sensing element row from the active areas of the sensing elements in the adjacent row.

As will be appreciated by those skilled in the art, this aspect of the present invention can, and preferably does, include any one or more or all of the preferred and optional features of the present invention discussed herein, as appropriate. For example, preferably the sensing device comprises an image sensor. Preferably the plurality of sensing elements comprises a plurality of pixels. Preferably the active area of the sensing element comprises a photodiode. Preferably at least some pairs of terminals of the components (e.g. transistors) in the circuit element are formed as shared terminals. Preferably the plurality of sensing elements in the sensing element rows are connected together as double (e.g. 8T) pixels, e.g. via their circuit elements.

The method may be performed in any suitable and desired way and on any suitable and desired platform. In a preferred embodiment the method is a computer implemented method, e.g. the steps of the method are performed by processing circuitry.

The methods in accordance with the present invention may be implemented at least partially using software e.g. computer programs. It will thus be seen that when viewed from further embodiments the present invention provides computer software specifically adapted to carry out the methods herein described when installed on a data processor, a computer program element comprising computer software code portions for performing the methods herein described when the program element is run on a data processor, and a computer program comprising code adapted to perform all the steps of a method or of the methods herein described when the program is run on a data processing system.

The present invention also extends to a computer software carrier comprising such software arranged to carry out the steps of the methods of the present invention. Such a computer software carrier could be a physical storage medium such as a ROM chip, CD ROM, RAM, flash memory, or disk, or could be a signal such as an electronic signal over wires, an optical signal or a radio signal such as to a satellite or the like.

It will further be appreciated that not all steps of the methods of the present invention need be carried out by computer software and thus from a further broad embodiment the present invention provides computer software and such software installed on a computer software carrier for carrying out at least one of the steps of the methods set out herein.

The present invention may accordingly suitably be embodied as a computer program product for use with a computer system. Such an implementation may comprise a series of computer readable instructions either fixed on a tangible, non- transitory medium, such as a computer readable medium, for example, diskette, CD ROM, ROM, RAM, flash memory, or hard disk. It could also comprise a series of computer readable instructions transmittable to a computer system, via a modem or other interface device, over either a tangible medium, including but not limited to optical or analogue communications lines, or intangibly using wireless techniques, including but not limited to microwave, infrared or other transmission techniques. The series of computer readable instructions embodies all or part of the

functionality previously described herein.

Those skilled in the art will appreciate that such computer readable instructions can be written in a number of programming languages for use with many computer architectures or operating systems. Further, such instructions may be stored using any memory technology, present or future, including but not limited to,

semiconductor, magnetic, or optical, or transmitted using any communications technology, present or future, including but not limited to optical, infrared, or microwave. It is contemplated that such a computer program product may be distributed as a removable medium with accompanying printed or electronic documentation, for example, shrink wrapped software, pre-loaded with a computer system, for example, on a system ROM or fixed disk, or distributed from a server or electronic bulletin board over a network, for example, the Internet or World Wide Web.

Preferably the invention also extends to a sensing device (e.g. an (e.g. CMOS) image sensor) designed and manufactured according to the method outlined above, as well as a method of manufacturing a sensing device according to the method outlined above, e.g. including the step of manufacturing the sensing device using the determined layout.

As will be appreciated by those skilled in the art, these aspects of the present invention can, and preferably do, include any one or more or all of the preferred and optional features of the present invention discussed herein, as appropriate.

Various embodiments of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which:

Figure 1 shows a block diagram of a camera system including an image sensor;

Figure 2 shows schematically the layout of an image sensor;

Figure 3 shows the circuit diagram of an image sensor pixel;

Figure 4 shows the layout of an image sensor;

Figure 5 shows a flow chart of the method steps according to an

embodiment of the present invention; Figure 6 shows an optimisation path through the circuit diagram of an image sensor pixel;

Figure 7 shows an embodiment of a layout of a pixel determined using the optimisation path shown in Figure 6;

Figure 8 shows the terminals of two transistors being combined;

Figure 9 shows an optimisation path through the circuit diagram of two image sensor pixels;

Figure 10 shows an embodiment of a layout of two pixels determined using the optimisation path shown in Figure 9;

Figure 11 shows an embodiment of a layout of an image sensor using the pixels shown in Figure 10; and

Figure 12 shows another embodiment of a layout of an image sensor.

Embodiments of the invention will now be discussed in the context of designing the layout of an image sensor.

Image sensors, e.g. implemented using complementary metal oxide semiconductor (CMOS) technology, may be used for a wide range of applications to detect light for the capture of images. One application is in a digital camera. Figure 1 shows a block diagram of a camera system 1.

The camera system 1 includes optics 4 (e.g. a lens system) which focus light 2 onto the focal plane of an image sensor 6 of the camera 1. The image sensor 6 detects the incident light 2 which it converts into electrical signals. These analogue electrical signals are encoded into a digital signal which is processed by processing circuitry 8 and transferred to a storage device and/or a display 10.

Figure 2 shows schematically the layout of an image sensor 6. The image sensor 6 is a mixed signal device that includes both analogue and digital circuits. The principal elements of the image sensor are pixels 12 which are organised into an array of rows and columns as shown in Figure 2. Light is collected by each pixel 12, such that a signal representative of the light incident at each position of the image sensor array may be read out by vertical and horizontal scanners 14, 16. Each pixel 12 shown in the image sensor 6 of Figure 2 includes a light sensitive photodiode 18 occupying a sensitive,“active” area of the pixel, and an inactive area occupied by a circuit element 20 including readout transistors which are used to read out the amount of light falling on the light sensitive area. Any light that is incident upon the inactive area 20 (i.e. not falling on the photodiode 18) will not be detected.

The light-collecting capability of a pixel, and thus an image sensor, for a given pixel pitch, can be characterised by the“fill factor” (the ratio of the light sensitive area to the total area of the pixel). It will be appreciated that the fill factor of an image sensor may be increased, and thus the light-collecting capability improved, if the inactive area occupied by the circuit elements in the image sensor is reduced, as this enables more space to be provided for the photodiodes.

Figure 3 shows the circuit diagram for one type of CMOS pixel 12 having four transistors (and thus known as a“4T” pixel). The pixel 12 has a pinned photodiode (PD) 18 that includes three layers: a p+ layer, an n-implantation layer and a p- substrate layer. The circuit element 20 of the pixel 12 includes a reset transistor (RST) switch 22, a source follower (SF) transistor 24, a row-selector transistor (Row Sel) switch 26 and a transfer gate transistor (TX) 28. The circuit element 20 also includes a floating diffusion (FD) 30, a supply voltage (VDD) 32 and an output (Out) 34.

Figure 4 shows a layout of a 4T pixel 12. This shows how the components of the pixel 12 (e.g. those shown schematically in Figure 3) may be arranged over the area of the pixel 12. This conventional square pixel 12 is then able to be copied and tessellated over the whole area of an image sensor. One implementation of such a pixel layout achieves a fill factor of 28% for a pitch of 2.4 pm.

An embodiment of a method of designing the layout of an image sensor will now be described with reference to Figures 5 to 14.

Figure 5 shows a flow chart showing the main steps of the method according to an embodiment of the invention. First, the type of pixel to be used for the image sensor (e.g. a 4T pixel as shown in Figure 3) is provided as the input for designing the layout of the image sensor (step 51 , Figure 5). Using this type of pixel 12, pairs of diffusion terminals in the circuit element 20 of the pixel 12 having common respective voltages are identified (step 52, Figure 5).

For the 4T layout, one of the diffusion terminals of the transfer gate transistor 28 may be paired with one of the diffusion terminals of the reset transistor switch 22, as these diffusion terminals have a common voltage. The other of the diffusion terminals of the reset transistor switch 22 may be paired with one of the diffusion terminals of the source follower transistor 24, as these diffusion terminals have a common voltage. The other of the diffusion terminals of the source follower transistor 24 may be paired with one of the diffusion terminals of the row-selector transistor switch 26, as these diffusion terminals have a common voltage.

Once the pairs of diffusion terminals of the transistors in the circuit element 20 of the pixel 12 having common respective voltages have been identified, a path through the transistors in the circuit element 20 which directly connect the common voltage diffusion terminals is found (step 53, Figure 5). Such a path 36 is shown in the 4T pixel 12 in Figure 6.

Figure 6 shows a 4T pixel (e.g. as shown in Figure 3) in which a path connecting the transistors of the circuit element is determined. It can be seen from Figure 6 that in order to connect all of the pairs of common voltage diffusion terminals that were identified previously, the path 36 starts from the photodiode 18 and passes through the transfer gate transistor 28 to the floating diffusion 30 (as shown in Figure 3). From the floating diffusion 30, the path 36 passes through the reset transistor switch 22 to the supply voltage 32. The path 36 then passes through the source follower transistor 24 and through the row-selector transistor switch 26 to the output 34 of the circuit element 20 of the pixel 12.

Once the path 36 has been determined (as shown in Figure 6), the layout of the pixel may be arranged according to this path 36 (step 54, Figure 5). Figure 7 shows one example of a layout of a 4T pixel 12 using the determined path 36 as shown in Figure 6. Owing to the single, linear path 36 that has been determined for the pixel 12, the layout of the pixel 12 can reflect this, as shown in Figure 7. Thus the layout of the pixel starts with the photodiode 18, the size of which is chosen to give a pixel size corresponding to a desired pixel pitch for the image sensor. The photodiode is connected to the transfer gate transistor 28 and then to the reset transistor switch 22 via the floating diffusion 30. The reset transistor switch 22 is connected to the source follower transistor 24 via the supply voltage 32. The source follower transistor 24 is connected to the row-selector transistor switch 26 and the row-selector transistor switch 26 is then connected to the output 34, all in a linear arrangement.

A conducting link 38 is also formed between the gate of the source follower transistor 24 and the floating diffusion 30, to provide the 4T circuit element 20 layout as shown in Figures 3 and 6. As will be seen with reference to Figure 11 , the shape of the photodiode 18 and the arrangement of the transistors is also chosen to enable a plurality of pixels 12 to be tessellated together for an image sensor.

As can be seen in Figure 7 (and will also be described with reference to Figure 8), the layout of the transistors in the circuit element 20 of the pixel 12 allows the adjacent diffusion terminals to be combined into shared diffusion terminals (step 55, Figure 5). Figure 8 shows schematically a pair of diffusion terminals from separate transistors being combined. The two separate transistors (G1 , G2) 41 , 42 each have two diffusion terminals 43, 44, 45, 46 which operate at respective voltages A, B, B and C. As the two diffusion terminals 44, 45 operate at a common voltage (B), these diffusion terminals 44, 45 can be combined into a single, shared diffusion terminal 47. It will be seen that the pair of transistors 41 , 42 now occupies less space in the circuit element.

Figure 9 shows two 4T pixels which have been joined together via their outputs 134 to form a double 8T pixel 112. This is possible because the outputs 134 are held at a common voltage. The 8T double pixel 112 enables a path 136 connecting the transistors in both the circuit elements 120 to be determined. The path 136 through the transistors of the circuit elements 120 is the same in each circuit element 120, which are each the same as the path determined for the 4T pixel shown in Figure 6.

The path 136 (which is both linear and continuous through the circuit elements 120 of the double pixel 112) is connected together, and passes between the individual circuit elements 120, via the outputs 134 of the circuit elements 120. Forming a path in this way through a double pixel 112 enables the diffusion terminals of the row-selector transistor switches 126 in the two circuit elements, via the two outputs 134, to be combined into a single diffusion terminal, as can be seen from Figure 10.

Figure 10 shows one example of a layout of an 8T pixel 112 using the determined path 136 as shown in Figure 9. The layout of the 8T pixel 112 is arranged in a very similar way to the layout of the 4T pixel shown in Figure 7, i.e. using the determined path 136 through the 8T pixel 112. Thus, again, the linear nature of the determined path 136 through the 8T pixel 112 is reflected in the linear arrangement of the circuit element 120 between the two photodiodes 118 of the 8T pixel 112.

The layout of the 8T pixel 112 is then used to form an array of pixels in an image sensor. Figure 11 shows one embodiment of a layout of an image sensor 56 that includes the 8T pixels 112 shown in Figure 10. In the image sensor 56, columns of 8T pixels 112 are formed, with back to back photodiodes 118 and the linear circuit elements 120 extending between pairs of photodiodes 118.

Adjacent columns of 8T pixels 112 are arranged, with the pixels 112 in one column being offset from the pixels 112 in the next column, such that the photodiodes 118 of the pixels 112 in one column are nested into the gap next to the circuit elements 120 in the next column. This produces a staggered array for the image sensor 56. One implementation of the image sensor 56 shown in Figure 11 achieves a fill factor of 42% for a pitch of 2.4 pm. Thus it can be seen that this represents a significant improvement over the fill factor of the pixel shown in Figure 4.

Figure 12 shows another embodiment of a layout of an image sensor 66 that includes 8T pixels 142. The layout of the image sensor 66 shown in Figure 12 is similar to that of the image sensor shown in Figure 11 , except that the circuit elements 121 extend linearly from the corner of the respective photodiodes 119. In a similar manner as for the image sensor shown in Figure 11 , the photodiodes 119 in one column of the image sensor 66 shown in Figure 12 are nested into the hap next to the circuit elements 121 in the next column, with the pixels 142 in adjacent columns being a reflected version of each other. It will be seen that the layout of the image sensor 66 shown in Figure 12 helps to reduce the offset of the photodiodes 119 in one column relative to an adjacent column, compared to the layout of the image sensor shown in Figure 11. The image sensor 66 shown in Figure 12 has a fill factor of 43% for a pitch of 2.4 pm. Thus, again it can be seen that this represents a significant improvement over the fill factor of the pixel shown in Figure 4.

It can be seen from the above that in at least preferred embodiments the invention provides a method of designing an image sensor layout in which shared diffusion terminals are formed for pairs of common voltage diffusion terminals. This allows the area of the pixel occupied by the circuit element to be reduced which helps to maximise the fill factor of the image sensor.

Claims

1. A method of designing the layout of a sensing device, wherein the sensing device comprises a plurality of sensing elements, each sensing element comprising an active area for detecting the incidence of a particle and a circuit element comprising a plurality of components for processing signals captured by the active area of the sensing element, wherein each component comprises a plurality of terminals;

the method comprising, for a sensing element of the sensing device:

2. The method as claimed in claim 1 , wherein the sensing device comprises an image sensor, wherein the plurality of sensing elements comprises a plurality of pixels, and wherein each pixel comprises a photodiode and a circuit element comprising a plurality of transistors.

3. The method as claimed in claim 1 or 2, wherein the method comprises not imposing a rectangular shape as a constraint on the shape of the sensing elements when designing the sensing device layout.

4. The method as claimed in claim 1 , 2 or 3, wherein each sensing element comprises a 4T pixel comprising one or more of: a transfer transistor gate, a reset transistor gate, a row selection transistor gate, a source-follower readout transistor, a floating diffusion, a supply voltage and an output contact.

5. The method as claimed in any one of the preceding claims, wherein the step of identifying one or more pairs of terminals comprises determining the voltage of the terminals in the plurality of components in the circuit element.

6. The method as claimed in any one of the preceding claims, wherein the method comprises determining the path through the plurality of components in the circuit elements of two or more sensing elements and arranging the layout of the circuit elements of the two or more sensing elements according to the determined path.

7. The method as claimed in any one of the preceding claims, wherein the step of determining the path comprises optimising the path through the plurality of components in the circuit element(s) such that the path directly connects the terminals in each of the one or more of the pairs of terminals identified as having a common voltage.

8. The method as claimed in any one of the preceding claims, wherein the step of determining the path comprises optimising the path to maximise the number of pairs of terminals identified as having a common voltage that the path passes through.

9. The method as claimed in any one of the preceding claims, wherein the step of determining the path comprises setting up and evaluating a cost function to optimise the path.

10. The method as claimed in any one of the preceding claims, wherein the determined path passes the plurality of the components in the circuit element(s) in series.

11. The method as claimed in any one of the preceding claims, wherein the determined path through the components is at least partly a linear path.

12. The method as claimed in any one of the preceding claims, wherein the layout of the circuit element is arranged without imposing the constraint that the sensing element(s) are required to be rectangular in shape.

13. The method as claimed in any one of the preceding claims, wherein the layout of the circuit element is arranged to maximise the fill factor of the sensing element.

14. The method as claimed in any one of the preceding claims, wherein the layout of the circuit element is arranged to maximise the number of pairs of terminals which are formed as shared terminals.

15. The method as claimed in any one of the preceding claims, wherein the circuit element has a linear layout with the components in the circuit element arranged in a straight line.

16. The method as claimed in any one of the preceding claims, wherein the method comprises arranging the layout of the sensing element according to the determined path, wherein the step of arranging the layout of the sensing element comprises one or more: arranging the position of the active area relative to the circuit element in the sensing element, arranging the size of the active area relative to the circuit element in the sensing element and arranging the shape of the active area in the sensing element.

17. The method as claimed in any one of the preceding claims, wherein the layout of the sensing element is arranged such that the circuit element extends linearly from the active area.

18. The method as claimed in any one of the preceding claims, wherein the method comprises arranging the layout of the plurality of sensing elements in the sensing device, wherein the position, size and/or shape of the active area and/or the circuit element in the layout of the sensing element is arranged such that the sensing element tessellates with other sensing elements across the sensing device.

19. The method as claimed in claim 18, wherein the layout of the sensing device is arranged such that the sensing elements tessellate over the sensing device in a regular array.

20. The method as claimed in any one of the preceding claims, wherein the sensing device comprises a plurality of rows of sensing elements, wherein each row comprises a plurality of sensing elements, and wherein the active areas of the sensing elements in one row are offset in the direction along the row from the active areas of the sensing elements in the adjacent row.

21. The method as claimed in any one of the preceding claims, further comprising manufacturing the sensing device using the designed layout.

22. A computer readable storage medium storing computer software code which when executing on a data processing system performs a method as claimed in any one of claims 1 to 19.

23. A method of manufacturing a sensing device comprising:

manufacturing the sensing device using the layout design according to the method as claimed in any one of claims 1 to 20.

24. A sensing device manufactured using the layout designed according to the method of claim 23.

25. A sensing device comprising a plurality of rows of sensing elements, each row comprising a plurality of sensing elements, each sensing element comprising an active area and a circuit element, each circuit element comprising a plurality of components for processing signals captured by the active area of the sensing element;