EP3821335A4 - Accélérateur de tri bitonique - Google Patents
Accélérateur de tri bitonique Download PDFInfo
- Publication number
- EP3821335A4 EP3821335A4 EP19833244.7A EP19833244A EP3821335A4 EP 3821335 A4 EP3821335 A4 EP 3821335A4 EP 19833244 A EP19833244 A EP 19833244A EP 3821335 A4 EP3821335 A4 EP 3821335A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- bitonic sorting
- sorting accelerator
- accelerator
- bitonic
- sorting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
- G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/22—Indexing scheme relating to groups G06F7/22 - G06F7/36
- G06F2207/228—Sorting or merging network
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Complex Calculations (AREA)
- Memory System (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Image Processing (AREA)
- Advance Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN201841026064 | 2018-07-12 | ||
US16/237,447 US10901692B2 (en) | 2018-07-12 | 2018-12-31 | Bitonic sorting accelerator |
PCT/US2019/041315 WO2020014424A1 (fr) | 2018-07-12 | 2019-07-11 | Accélérateur de tri bitonique |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3821335A1 EP3821335A1 (fr) | 2021-05-19 |
EP3821335A4 true EP3821335A4 (fr) | 2021-09-01 |
Family
ID=69139378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19833244.7A Pending EP3821335A4 (fr) | 2018-07-12 | 2019-07-11 | Accélérateur de tri bitonique |
Country Status (6)
Country | Link |
---|---|
US (3) | US10901692B2 (fr) |
EP (1) | EP3821335A4 (fr) |
JP (2) | JP7404332B2 (fr) |
KR (1) | KR102687186B1 (fr) |
CN (1) | CN112654962A (fr) |
WO (1) | WO2020014424A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220222510A1 (en) * | 2021-01-13 | 2022-07-14 | Apple Inc. | Multi-operational modes of neural engine circuit |
JP2022117853A (ja) * | 2021-02-01 | 2022-08-12 | パナソニックIpマネジメント株式会社 | 診断回路、電子デバイス及び診断方法 |
US11593106B1 (en) * | 2021-09-24 | 2023-02-28 | Apple Inc. | Circuits and methods for vector sorting in a microprocessor |
CN114356512A (zh) * | 2021-10-25 | 2022-04-15 | 腾讯科技(深圳)有限公司 | 一种数据处理方法、设备以及计算机可读存储介质 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4567572A (en) | 1983-02-22 | 1986-01-28 | The United States Of America As Represented By The Director Of The National Security Agency | Fast parallel sorting processor |
US5179717A (en) * | 1988-11-16 | 1993-01-12 | Manco, Ltd. | Sorting circuit using first and last buffer memories addressed by reference axis data and chain buffer memory addressed by datum number of the first and last buffer memories |
US5206947A (en) * | 1989-06-30 | 1993-04-27 | Digital Equipment Corporation | Stable sorting for a sort accelerator |
US6041398A (en) * | 1992-06-26 | 2000-03-21 | International Business Machines Corporation | Massively parallel multiple-folded clustered processor mesh array |
JPH0774988B2 (ja) * | 1993-01-19 | 1995-08-09 | 日本電気株式会社 | ート処理装置 |
JP3518034B2 (ja) * | 1995-03-30 | 2004-04-12 | 三菱電機株式会社 | ソート方法並びにソート処理装置並びにデータ処理装置 |
US6088353A (en) | 1997-07-08 | 2000-07-11 | Lucent Technologies, Inc. | Sorting networks having reduced-area layouts |
KR101662769B1 (ko) * | 2010-03-09 | 2016-10-05 | 삼성전자주식회사 | 고속 정렬 장치 및 방법 |
US9558903B2 (en) | 2012-05-02 | 2017-01-31 | National Instruments Corporation | MEMS-based switching system |
US20160283549A1 (en) | 2015-03-27 | 2016-09-29 | Intel Corporation | Value sorter |
US10102180B2 (en) * | 2015-11-25 | 2018-10-16 | Hitachi, Ltd. | Majority circuit |
EP3526665B1 (fr) * | 2016-11-14 | 2020-07-15 | Google LLC | Tri pour dispositifs informatiques parallèles aux données |
US10809978B2 (en) * | 2017-06-02 | 2020-10-20 | Texas Instruments Incorporated | Merge sort accelerator |
-
2018
- 2018-12-31 US US16/237,447 patent/US10901692B2/en active Active
-
2019
- 2019-07-11 KR KR1020217004049A patent/KR102687186B1/ko active IP Right Grant
- 2019-07-11 CN CN201980058652.1A patent/CN112654962A/zh active Pending
- 2019-07-11 JP JP2021500789A patent/JP7404332B2/ja active Active
- 2019-07-11 WO PCT/US2019/041315 patent/WO2020014424A1/fr unknown
- 2019-07-11 EP EP19833244.7A patent/EP3821335A4/fr active Pending
-
2021
- 2021-01-25 US US17/156,731 patent/US11714603B2/en active Active
-
2023
- 2023-06-15 US US18/335,452 patent/US20230418555A1/en active Pending
- 2023-12-13 JP JP2023210257A patent/JP2024028966A/ja active Pending
Non-Patent Citations (4)
Title |
---|
CHUNG JINIL ET AL: "Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, vol. 63, no. 1, 1 January 2016 (2016-01-01), pages 91 - 102, XP011599965, ISSN: 1549-8328, [retrieved on 20160215], DOI: 10.1109/TCSI.2015.2497558 * |
See also references of WO2020014424A1 * |
STONE H S: "PARALLEL PROCESSING WITH THE PERFECT SHUFFLE", IEEE TRANSACTIONS ON COMPUTERS, IEEE, USA, vol. C-20, no. 2, 1 February 1971 (1971-02-01), pages 153 - 161, XP000867145, ISSN: 0018-9340 * |
THOMPSON C D: "THE VLSI COMPLEXITY OF SORTING", IEEE TRANSACTIONS ON COMPUTERS, IEEE, USA, vol. C-32, no. 12, 1 December 1983 (1983-12-01), pages 1171 - 1184, XP000648503, ISSN: 0018-9340 * |
Also Published As
Publication number | Publication date |
---|---|
US11714603B2 (en) | 2023-08-01 |
EP3821335A1 (fr) | 2021-05-19 |
WO2020014424A1 (fr) | 2020-01-16 |
JP2021531570A (ja) | 2021-11-18 |
CN112654962A (zh) | 2021-04-13 |
US20210149632A1 (en) | 2021-05-20 |
US10901692B2 (en) | 2021-01-26 |
KR102687186B1 (ko) | 2024-07-24 |
JP7404332B2 (ja) | 2023-12-25 |
US20200019374A1 (en) | 2020-01-16 |
US20230418555A1 (en) | 2023-12-28 |
KR20210025113A (ko) | 2021-03-08 |
JP2024028966A (ja) | 2024-03-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20210212 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20210802 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G06F 7/16 20060101AFI20210727BHEP Ipc: G06F 5/06 20060101ALI20210727BHEP Ipc: G06F 7/24 20060101ALI20210727BHEP |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20230915 |