EP3794721A1

EP3794721A1 - Quadratic buck converter

Info

Publication number: EP3794721A1
Application number: EP19724463.5A
Authority: EP
Inventors: Mauricio DALLA VECCHIA; Johan Driesen
Original assignee: Katholieke Universiteit Leuven
Current assignee: Katholieke Universiteit Leuven
Priority date: 2018-05-14
Filing date: 2019-05-14
Publication date: 2021-03-24
Also published as: JP2021523661A; BR112020022096A2; WO2019219681A1

Abstract

A quadratic step-down converter (1) is disclosed. The converter (1) comprises an input port (2) for receiving an input DC voltage; an output port (3) for outputting an output DC voltage; and a first voltage regulation stage (4) in series with a second voltage regulation stage (5) between the input port (2) and the output port (3). At least one of the first voltage regulation stage (4) and the second voltage regulation stage (5) comprises a first topology (T2, T3) comprising first and second diodes (D3, D4, D5, D6) and first and second inductors (L1, L2, L3, L4), wherein the first diode (D3, D4) and the first inductor (L1, L2) are in parallel with the second diode (D5, D6) and the second inductor (L3, L4).

Description

QUADRATIC BUCK CONVERTER

Field of the invention

Embodiments of the present invention relate to a quadratic buck converter.

Background of the invention DC-DC converters are used in many applications to increase, decrease, or regulate DC voltages. Such converters often include components the failure of which result in a change in the output voltage of the device. This can be detrimental, for example in applications wherein a constant output voltage is required to be supplied by the converter.

Existing methods of failure protection focus on active monitoring of the converter in order to detect any failure and protect the output. However, these methods can have one or more disadvantages. There is a delay time between failure and protection. Also, restoration of the converter to a functioning state can require replacement of part or all of the converter.

Summary of the invention

It is an object to provide a converter or method for converting an input voltage signal into a lower output voltage.

According to a first aspect of the present invention there is provided a quadratic step-down converter comprising an input port for receiving an input DC voltage; an output port for outputting an output DC voltage; and a first voltage regulation stage in series with a second voltage regulation stage between the input port and the output port, wherein at least one of the first voltage regulation stage and the second voltage regulation stage comprises a first topology comprising first and second diodes and first and second inductors, and wherein the first diode and the first inductor are in parallel with the second diode and the second inductor. It is an advantage of embodiments of the present invention that an automatic diode failure redundancy mechanism can be provided, to provide continued of the functionality of a device according to embodiments of the present invention in the event of a diode failure. It is a further advantage of embodiments of the present invention that the converter does not need to be replaced in part or entirely in order to provide the same functionality as before the failure.

The first topology may comprise a third diode configured to connect a point between the first inductor and the first diode with a point between the second inductor and the second diode. The first topology may comprise a first capacitor connected between a first point between the first inductor and the first diode and a second point between the second inductor and the second diode.

The first voltage regulation stage may comprise the first topology and the second voltage regulation stage may comprise a third inductor.

The first voltage regulation stage may comprise a third inductor and the second voltage regulation stage may comprise the first topology.

The first voltage regulation stage and the second voltage regulation stage may comprise the first topology. The converter may comprise a first switch connected between the first voltage drop stage and the second voltage drop stage.

The converter may comprise a second switch connected in parallel with the first voltage regulation stage and the second voltage regulation stage.

According to a second aspect of the present invention there is provided apparatus comprising a converter according to the first aspect and a control module, wherein the control module is configured to control a duty cycle of the converter.

The control module may be configured to, in response to detecting a failure of a diode comprised in the first voltage stage or the second voltage stage, modify the duty cycle of the converter. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

Brief description of the drawings Further features of the present invention will become apparent from the examples and figures, wherein:

Figure 1 is a schematic representation of a device according to embodiments of the present invention comprising first and second voltage regulation stages; Figure 2a illustrates a first topology which can be comprised in a voltage regulation stage according to embodiments of the present invention;

Figure 2b illustrates a second topology which can be comprised in a voltage regulation stage according to embodiments of the present invention;

Figure 2c illustrates a third topology which can be comprised in a voltage regulation stage according to embodiments of the present invention;

Figure 3 is a schematic representation of a converter according to embodiments of the present invention along with the possible topologies Tl, T2, T3 for each voltage regulation stage;

Figure 4 is a plot of relative size of duty cycles of a first and second switch which may be comprised in a converter according to embodiments of the present invention, indicating regions of operation;

Figure 5 is a plot of output gain profile for various combinations of the first, second, and third topologies according to embodiments of the present invention;

Figure 6a is a schematic representation of a device according to embodiments of the present invention before failure of a diode;

Figure 6b is a schematic representation of a device according to embodiments of the present invention after failure of a diode;

Figure 7 is a plot of inductor current and voltage during the transient after an open-circuit failure of diode D2 as shown in Figure 5b;

Figure 8 is a schematic representation of a device according to embodiments of the present invention comprising a control module;

Figure 9a is a schematic representation of a converter according to embodiments of the present invention along with the possible topologies Tl, T2, T3 for each voltage regulation stage, wherein switches SI and S2 are closed;

Figure 9b is a schematic representation of a converter according to embodiments of the present invention along with the possible topologies Tl, T2, T3 for each voltage regulation stage, wherein switches SI and S2 are open; Figure 10 presents simulated output voltages of converters according to embodiments of the present invention with various voltage regulation stage topology combinations, along with the PWM signals applied to the switches;

Figure 11 is a schematic representation of a test bench setup for testing a converter according to embodiments of the present invention;

Figures 12a-12h present experimentally measured output voltages of converters according to embodiments of the present invention with various voltage regulation stage topology combinations;

Figure 12i is a photograph of a converter according to embodiments of the present invention;

Figure 13 illustrates available PWM modes of a converter according to embodiments of the present invention operating in Region 1, along with the PWM signals applied to the switches;

Figure 14 is presents experimentally measured output voltages for the T1-T3 configuration under the operation of PWM1 and PWM2.

Detailed description of preferred embodiments

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. "a" or "an", "the", this includes a plural of that noun unless something else is specifically stated. The term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein. In the drawings, like reference numerals indicate like features; and, a reference numeral appearing in more than one figure refers to the same element. Referring to Figure 1, a converter 1 according to embodiments of the present invention is shown. The converter 1 is a quadratic step-down, or buck, converter, configured to receive an input DC voltage V_m at an input port 2 and to output an output DC voltage V_out at an output port 3. The output DC voltage V_out is lower than the input DC voltage V_m. In some embodiments, the output port 3 comprises an output resistor R_out, and the output voltage V_out is the voltage across the output resistor R_out.

The converter 1 comprises a first voltage regulation stage 4 and a second voltage regulation stage 5. The first voltage regulation stage 4 and the second voltage regulation stage 5 are in series with each other and are arranged between the input port 2 and the output port 3 such that the first voltage regulation stage 4 is between the second voltage regulation stage 5 and the output port 3.

The converter 1 comprises a diode D_P4 connected between the ground and a point between the first voltage regulation stage 4 and the second voltage regulation stage 5. The converter 1 comprises an intermediate capacitor C_mter and a diode D_P5 in parallel with the second voltage regulation stage 5. The converter 1 comprises an output capacitor C_out connected across the output resistor R_out.

In embodiments of the present invention, the first and second voltage regulation stages 4, 5 each take the form of one of the topologies shown in Figures 2a-2c.

The first topology T1 (Figure 2a) consists of a single inductor L .

The second topology T2 (figure 2b ) comprises a first inductor L_T2i, a first diode D_T2i, a second inductor L_T22, and a second diode D_T22. The first inductor L_T2i and the first diode D_T2i are in parallel with the second inductor L_T22 and the second diode D_T22. A first point P_T2i is located between the cathode of the first diode D_T2i and the first inductor Lni. A second point P_T22 is located between the anode of the second diode D_T22 and the second inductor L_T22. The second topology T2 comprises a third diode D_T23 connected between the first point P_T2i and the second point P_T22, so as to allow current to flow from P_T22 to P_T2i and to block current from flowing from P_T2i to P_T22.

The third topology T3 (Figure 2c) comprises a first inductor L_T3i, a first diode D_T3i, a second inductor 32, and a second diode D_T32. The first inductor rn and the first diode D_T3i are in parallel with the second inductor 32 and the second diode D_T32. A first point P_T3i is located between the cathode of the first diode D_T3i and the first inductor L_T3i. A second point P_T3i is located between the anode of the second diode D_T32 and the second inductor L_T32.

The third topology T3 comprises a first capacitor C_T3i connected between the first point P_T3i and the second point P_T32.The first voltage regulation (VR) stage 4 and the second voltage regulation (VR) stage 5 may take the form of any of the first, second, and third topologies, subject to the following restriction: if the first voltage regulation stage 4 takes the form of the first topology Tl, then the second voltage regulation stage 5 takes to the form of the second topology T2 or the third topology T3, and if the second voltage regulation stage 5 takes the form of the first topology Tl, then the first voltage regulation stage 4 takes the form of the second topology T2 or the third topology T3. Thus, in embodiments of the present invention, at least one of the first and the second voltage regulation stages 4, 5 takes the form of the second or the third topology. That is, at least one of the first and the second voltage regulation stages 4, 5 comprises first and second diodes and first and second inductors, wherein the first diode and the first inductor are in parallel with the second diode and the second inductor. In one embodiment, the first voltage regulation stage 4 has the second topology T2 or the third topology T3 and the second voltage regulation stage 5 has the second topology T2 or the third topology T3.

It is to be noted that whereas the first, second and third topology have been shown with particular electrical components, it will be understood that these topologies comprise at least the shown and discussed electrical components, but may, in some embodiments, also comprise further electrical components. For example, an extra resistor may be in parallel with the intermediate capacitor.

Referring to Figure 3, a converter 1 according to embodiments of the present invention is shown along with the possible topologies Tl, T2, T3 for each VR stage 4, 5. The circuit components are labelled as follows in the first VR stage 4: the inductor of the first topology T1 is denoted by LI; the first inductor Lni, L_T3i of the second and third topologies T2, T3 respectively are also denoted by LI; the second inductor L_m, L_T32 of the second and third topologies T2, T3 respectively are denoted by L3; the first diode D_T2i, D_T3i of the second and third topologies T2, T3 respectively are denoted by D3; the second diode D_T22, D_T32 of the second and third topologies T2, T3 respectively are denoted by D5; the third diode D_T23 of the second topology T2 is denoted by D7; the capacitor C_T3i of the third topology T3 is denoted by Cl.

The circuit components are labelled as follows in the second VR stage 5: the inductor of the first topology T1 is denoted by L2; the first inductor Lni, L_T3i of the second and third topologies T2, T3 respectively are also denoted by L2; the second inductor L_T22, L_T32 of the second and third topologies T2, T3 respectively are denoted by L4; the first diode D_T2i, D_T3i of the second and third topologies T2, T3 respectively are denoted by D4; the second diode D_T22, D_T32 of the second and third topologies T2, T3 respectively are denoted by D5; the third diode D_T23 of the second topology T2 is denoted by D8; the capacitor C_T3i of the third topology T3 is denoted by C2.

The behavior of a converter according to embodiments of the present invention can be categorized depending on its topology and the magnitude of a first duty cycle di provided to the first control switch SI relative to a second duty cycle 6₂ applied to the second control switch S2. In some embodiments comprising the second switch S2, the pulses applied to the first switch SI and the second switch S2 are identical and are applied synchronously, that is, without any offset in time between the two signals. In some embodiments, different signals are applied to the first switch SI and the second switch S2. For example, the first duty cycle may not be equal to the second duty cycle, i.e. di ¹ 82. Referring to Figure 4, three regions can be defined: Region 1 where the second duty cycle is greater than the first duty cycle i.e. 6₂ > di, Region 2 where the second duty cycle is less than the first duty cycle i.e. 6₂ < di, and Region 3 wherein the second duty cycle is equal to the first duty cycle i.e. i.e. 6₂ = di.

Referring to Table la, the possible combinations of topologies and the associated gain functions are shown as a function of the duty cycles di and 6₂ in Region 1. The gain is equal to the output voltage VOUT of the converter divided by the input voltage V_m of the converter. The duty cycle represents the on-time as a percentage of the period of a pulse applied to a first control switch SI, connected in series with and between the first VR stage 4 and the second VR stage 5, and to a second control switch S2 connected in series with the intermediate capacitor C_mter and between the first VR stage 4 and the second VR stage 5. In some embodiments, the second control switch S2 is not provided.

As shorthand for the combination of topologies, the notation "Tx-Ty" may be used, wherein Tx denotes the topology of the first VR stage 4 and Ty denotes the topology of the second VR stage 5. For example, in the T2-T1 configuration, the first VR stage takes the form of the second topology T2 and the second VR stage takes the form of the first topology Tl.

Table la - Associated gain functions for converter topology combinations for 6₂ > di.

In embodiments of the present invention wherein the converter comprises the first switch Si and the second switch S₂, an intermediate voltage stage V_mT can be provided being the voltage across the intermediate capacitor C_mter. This allows two voltage output levels to be generated in the same converter and both voltage levels can be used to supply loads. The level of the intermediate voltage V_mT can be controlled by controlling the duty cycle of the second switch S₂. Table lb summarizes the gain functions VmrlVm as a function of duty cycle for the intermediate voltage state. Table lb - Associated intermediate stage gain functions for converter topology combinations for 6₂ > di.

Table 2a summarizes the gain functions that represent the steady state conversion ratio of the converter in region 2, where 6₂ < di. The intermediate stage gain functions are summarized in

Table 2b.

Table 2a - Associated gain functions for converter topology combinations for 6₂ < di.

Table 2b - Associated intermediate stage gain functions for converter topology combinations for 6₂ < di.

Table 3a summarizes the gain functions that represent the steady state conversion ratio of the converter in region 3, where 6₂ = di = d. The intermediate stage gain functions are summarized in Table 3b.

It can be seen from Tables la and lb that if the difference between 6₂ and di becomes smaller enough to consider 6₂ = di = d, the gain profiles presented in Tables 3a and 3b are recovered. This behaviour can be attributed to the continuing conduction of the antiparallel diode of switch S2 even if the switch S2 is in an off state until switch SI commutes from closed to open. Thus Regions 2 and 3 can generate similar pulse-width-modulation (PWM) modes and consequently the same intermediate and output voltage levels, whereas Region 1 is distinguished by the independence between the stages. Put differently, in Region 1, the voltage regulation stages can be considered independent, because switch SI commutes to the off-state before switch S2. This behavior can also be observed in Table lb, since the intermediate voltage level is only dependent on the duty cycle 6₂, whereas in Region 2 (Table 2b), the duty cycle that defines the intermediate voltage level is di. Table 3a - Associated gain functions for converter topology combinations for 6₂=6₁=6

Table 3b - Associated intermediate state gain functions for converter topology combinations for 6₂=6₁=6

Referring to Figure 5, the output gain behavior as a function of the duty cycle is shown for the topology combinations of Table 3a. It can be seen that all combinations according to embodiments of the present invention achieve the step-down conversion for the entire range of operation (for the duty cycle ranging between 0 and 1), and exhibit less nonlinear behavior than the case where the first VR stage 4 and the second VR stage 5 take the form of the first topology. The converters according to embodiments of the present invention exhibit attenuation of the highly non-linear behavior of a quadratic buck converter as known in the art. Within the scope of the present invention various configurations of the converter are possible, for example (but not limited to): the converter operates with two switches and 6₂ = di= d; the converter operates with two switches and 6₂ ¹ di; the converter operates with just one switch (switch SI) and, instead of switch S2, operates with a diode.

In embodiments wherein switch S2 is not present, just one active switch (and one dedicated driver) are implemented in the power stage, although the overall efficiency of the converter may decrease due to the increase in losses. In embodiments comprising both switches SI and S2, and d₂¹di, the control strategy should be reassessed, since two different duty cycles can be used to control the operation of the converter, which can increase the complexity of the strategy. In embodiments wherein the converter operates with two switches and 6₂ = di= d, only one duty cycle can be used to control the converter, which decreases the complexity of the control stage, although the usage of two switches may increase the size of the PCB board due to the need of the implementation of an additional driver circuit.

Embodiments of the present invention advantageously provide a diode failure redundancy mechanism. For example, referring to Figure 6a, a device 10 according to embodiments of the present invention is shown, with the T1-T2 configuration. Figure 6b shows a modified device 10', which has experienced failure of the second diode D2 comprised in the second VR stage 5. This is an open circuit failure and the dashed line indicates a path that current can no longer take, i.e. current can no longer flow through the second diode D2.

The behavior of the modified device 10' can be explained as follows, with the assumption that the diodes Dl, D2, D3 are ideal diodes. Upon failure of the second diode D2 in open circuit, the modified device 10' transitions from the steady state of the device 10, through a transient period, to a steady state of the modified device 10'. During the transition period, the voltage across the second inductor L2 is negative, leading to a demagnetization of the second inductor L2, i.e. the current supplied by the second inductor L2 decreases. The demagnetization ends after the transient period and the modified device 10' then achieves the steady state stage. In the steady state of the modified device 10', diodes Dl and D3 can conduct, which means that the voltage across the second inductor L2 will remain zero (so the remaining L2 current will be constant). The steady state of the modified device 10' is then that of a Tl-Tl configuration, that is, the first VR stage takes the form of the first topology T1 and the second VR stage takes the form of the first topology T1 and the gain is then d². Figure 7 shows the behavior of the inductor current and voltage during the transient after an open-circuit failure of diode D2.

If instead diode D2 fails, a similar process of transient period to steady state occurs with diode Dl, that is, the device again obtains a steady state of the Tl-Tl configuration. If diode D3 fails in open-circuit, the device obtains a steady state configuration wherein diode Dl conducts the inductor LI current and diode D2 conducts the inductor L2 current, with both paths operating in parallel, for which the gain is d².

For a device according to embodiments of the present invention having a configuration which includes the third topology T3, in the event of failure of the capacitor Cl in open circuit, the steady state configuration after failure is the same as that in the case where the diode D3 fails in the second topology T2 (that is, the diode Dl conducts the LI current and the diode D2 conducts the L2 current).

This provides continuity of the functionality of a device according to embodiments of the present invention, even in the case that a diode fails, for example by receiving a current in excess of that which can be tolerated by the diode, by experiencing a temperature exceeding the maximum value that can be tolerated by the diode, or if internal bond wires undergo rupture after short-circuiting, characterizing an open circuit.. This can have advantages in many applications which require operation to be guaranteed in the case of failure of a component, for example data centres, PC chargers, USB-C ports, auxiliary power supplies, small battery chargers (low power and just for charger mode, as topologies according to embodiments of the present invention are unidirectional in terms of power transfer capability). Possible applications of the present invention include applications wherein domestic or industrial power supplies include DC voltage instead of, or as well as, AC : in such situations, a step-down converter according to embodiments of the present invention can be used to supply hair dryers, electronic devices, auxiliary circuits, etc.

In the event of failure of a diode, the gain profile of the device may change. In some applications of embodiments of the present invention, this change can be accepted without changing the duty cycle of the device. In some embodiments, the device includes control apparatus configured to control signals applied to the first control switch (and the second control switch if present) and optionally to adapt the duty cycle of the device so as to maintain the gain profile in the event of diode failure. Referring to Figure 8, a device 20 according to embodiments of the present invention is shown which includes a control module 21. Although in the device 20, the first VR stage 4 takes the form of the first topology and the second VR stage 5 takes the form of the second topology, it will be appreciated that any combination of the first, second, and third topologies as described herein is possible.

The control module 21 is configured to apply voltage signals having a duty cycle d to the first control switch SI and to the second control switch S2, if present. The control module 21 may be configured to apply a first signal having a first duty cycle di to the first control switch SI and to apply a second signal having a second duty cycle 6₂ to the second control switch S2. The first duty cycle di may be less than, greater than, or equal to the second duty cycle 6₂.

In some embodiments, the control module 21 is additionally configured to receive a measurement of the output voltage V_out, for example, using a voltage divider set of resistors or a dedicated voltage amplifier, and to compare the output voltage V_out with a reference voltage V_ref. In some embodiments, the microcontroller may be software-implemented and the reference voltage V_ref may be a value stored by the microcontroller. In some embodiments, the controller may be hardware-implemented and the reference voltage may be provided by the components implementing the microcontroller (for example, by choosing the parameters of the components such as capacitors, resistors etc so as to provide the desired voltage reference). The difference between the output voltage and the reference voltage is equal to an error voltage sV. The control module 21 is configured to modify the duty cycle d so as to reduce the error voltage sV. For example, the control module may apply a proportional-integral, proportional-differential, proportional-integral-differential, phase-lag, or phase-lead control scheme. The control module 21 preferably attempts to minimize the error voltage sV.

In the event of diode failure, the gain profile of the device changes and therefore the output voltage V_out changes. Embodiments of the present invention allow to compensate for the change in the gain by modifying the duty cycle and thereby ensure continued operation of the device, even in the event of diode failure.

In some embodiments, the controller may control variables other than the duty cycle in order to reduce or minimize the error voltage sV. For example, the controller may implement two control loops, an inner control loop and an outer control loop, wherein the inner loop (fast loop) is configured to control the current across one inductor and the outer loop (slow loop) is configured to control the output voltage V_out. In this example, the output of the voltage controller generates a current reference (i.e. a signal that emulates the current needed to be achieved by the converter to be able to transfer the specific power generating the specific voltage that is requested), to be compared with the measured current (that in this case can be the output current or an inductor current, dependent which topology, if Tl, T2 or T3, is being used in the second VR stage 5), and the inner control loop generates the duty cycle required to adjust the gain of the device so as to reduce or minimize the error voltage sV. Alternatively, another method is to control the phase-shift between pulse signals (method applied to control dual-active-bridge (DAB) topologies).

The voltage signals applied to the switches SI and (if present) S2 give rise to two distinct pulse- width-modulation (PWM) modes. In a first PWM mode, the first switch SI commutes from an open state to a closed state and the second switch commutes from an open state to a closed state, resulting in the circuit configuration shown in Figure 9a for each voltage regulation stage. In a second PWM mode, the first switch SI commutes from a closed state to an open state and the second switch S2 commutes from a closed state to an open state, resulting in the circuit configuration shown in Figure 9b for each voltage regulation stage. In the following analyis the first signal applied to the first switch SI and the second signal applied to the second switch S2 are assumed to be in phase with each other.

The voltage stress across each semiconductor element (switches and diodes) was determined and is shown in Table 4. It can be seen that the voltage stresses on switch SI and diode D1 are affected by the topology of the second VR stage 5. The voltage stresses on switch S2 and diode D2 are independent of the topology of the VR stages 4, 5 and are equal to the input voltage V_|N. the voltage stress across diodes D3, D4, D5, D6, D7, and D8, being diodes comprised in the second or third topologies T2, T3 respectively, are related to the operational duty cycle, the input voltage, and the VR stage in which the diodes are comprised.

The RMS current stress i_xRMs across each semiconductor element was also determined and is shown in Table 5. The RMS current stress was determined according to equation 1 as follows:

where i_xl is the current that the component needs to conduct during the first PWM mode and i_X2 is the current that the component needs to conduct during the second PWM mode.

The current and voltage stresses can be helpful in selecting the particular components to be used in the topologies Tl, T2, T3. Simulations

A numerical simulation was carried out to show the available intermediate voltage levels when an output voltage of 12V is set as standard output voltage, for various combinations of the topologies of the VR stages. The 12V voltage level is capable of, for example, supplying low voltage/low power loads such as LEDs or to charge small batteries. Different intermediate voltage levels are generated depending on the topology of the second VR stage 5 and the duty cycle of the converter, as discussed hereinbefore in relation to Tables 3a and 3b.The simulation was carried out in PLECS (Plexim GmbH). The configuration wherein both the first and the second VR stage have the third topology T3 was not simulated in these simulations, as the input voltage level is set to 48V and the output voltage level is set to 12V and the theoretical gain of this configuration is greater than 0.25.

A simulation is carried out for each configuration and the results are shown in Figure 10. The behaviour of the conventional quadratic buck converter is shown in Figure 10a, with an intermediate voltage level of 24V generated. According to Table 3, the T2-T1 and T1-T2 configurations of a converter according to embodiments of the present invention each generate the same output voltage level with different intermediate voltage levels for operation with the same duty cycle. This is seen in the simulation results in Figure 10b and lOd, where the voltage level of 20.25V (T1-T2) and 28.5V (T2-T1) are obtained for a duty cycle of 42.2%.

The configurations T1-T3 and T3-T1 operate with the same duty cycle of 36.6% and the same input/output voltages. The intermediate voltage level is different between the two configurations as different topologies are present in the second VR stage 5. The simulation results shown in Figure 10c and lOg confirm this analysis, showing an intermediate voltage of 17.6V (T3-T1) and 32.8V (T1-T3), allowing the possibility of suppling loads in different voltage ranges in a flexible way. The configurations T2-T3 and T3-T2 are also simulated. Intermediate voltages of 19.2V (T2-T3) and 30V (T3-T2) are generated and shown in Figure lOf and lOh respectively, validating the theoretical analysis presented in Tables 3a and 3b. The T3-T2 configuration presents a similar overall gain to that of the conventional buck converter but also provides an additional voltage level that can be sued to supply additional loads at different voltage levels. The T2-T2 configuration is also simulated. The voltage levels obtained are shown in Figure lOe. An intermediate voltage level of 24V is obtained, with a duty cycle of 33.3% to provide the desired output voltage of 12V.

Table 6. Theoretical expressions for current across the inductors of the structures.

The simulations were performed with a switching frequency of 300 kHz (a switching period of 3.33 ps). This frequency was used to determine the Tl, T2, and T3 inductances for further implementation of the configurations. All of the inductances were selected to guarantee a 20% ripple current across the inductors. A summary of the theoretical inductor current expressions in each scenario is presented in Table 6, as a function of the input current l_|N. Referring again to Figures 9a and 9b, the inductors of the T2 and T3 topologies charge their terminals in parallel and discharge in series, which allows to provide a natural balance between the internal currents of the topologies. This characteristic can allow direct control of the inductor current by the T2 or T3 topologies without requiring current sensors to control the inductor current.

A comparison was made between the theoretical expressions of Table 6 and the numerical simulations and the results are shown in Table 7. The input voltage of the converter is 48V and the output voltage is 12V. The rated input power is 100W. The different configurations according to embodiments of the present invention operate with their respective duty cycles (for example as determined from Figure 5) to generate an output voltage of 12V. The comparison shows that the theoretical analysis matches the simulations well. The theoretical analysis can thus be used to select appropriate inductances for experimental applications. Table 7. Inductor current comparison: theoretical / simulation.

Experimental verification

A schematic of a test bench setup 50 used to experimentally investigate a converter 1 according to embodiments of the present invention is shown in Figure 11. The test bench 50 includes a first voltmeter 51 configured to measure a voltage across the converter input, a second voltmeter 52 configured to measure a voltage across the intermediate capacitor C_mt, a third voltmeter 53 configured to measure a voltage across the output, and a scope 54 configured to receive data from the first, second, and third voltmeters 51, 52, 53. The test bench 50 includes a thermal camera (not shown) for thermally imaging the converter 1. Figure 12i shows a photograph of the converter 1 according to embodiments of the present invention which was used for the experimental measurements.

The input voltage V_|N was set to 48V, the output voltage V_out was set to 12V, the input power was set to 100W, the output capacitance C_out was chosen to be 20pF, and the switching frequency f_s of the PWM signals applied to the first and second switches SI, S2 was set to 300kHz.

Region 3 was first investigated (di = 6₂ = d). On comparing the waveforms presented in Figure 10 (simulation) and in Figures 12a-12h (experimental), it can be seen that the voltage levels in all topologies are similar in shape (DC shape) and in amplitude. Small deviations are observed between the amplitude values in simulation and in the experimental waveforms due to the non- idealities inherent in the components comprised in the converter. Voltage spikes can also be observed. This behaviour is common in circuits operating at high frequencies, when internal parasitics of the components and the parasitic inductances related to tracks and soldering points become prominent. The commutation between 'on' and 'off' states of the switches SI and S2 can also generate internal oscillations in the converter.

As discussed hereinbefore, the gain analysis performed for the operation in regions 2 and 3 results in the same gain expressions. The experimental results shown in Figure 11 are for region 3 but can be extended to operation in region 2.

For operation in region 1, an extra PWM mode is performed between the first PWM mode and the second PWM mode. This extra PWM mode allows independence between the first and second VR stages to be maintained, leading to the gain expressed as set out in Tables la and lb for all possible topology combinations. The gain for the intermediate voltage stage is only dependent on the second duty cycle , whereas the output gain is dependent on both the first duty cycle di and the second duty cycle since the VR stages are cascade connected.

Figure 13 shows the PWM modes for operation in region 1 for the T1-T3 configuration. It is noted that this analysis can be extended for all configurations. Figure 13 shows first, second, and third PWM modes, or topological stages, during the switching period. The graph shows the duration of the PWM signals applied to the first switch SI (PWM1) and to the second switch S2 (PWM2) along with the time periods during which each PWM mode is active.

Figure 14 shows the experimental results for the T1-T3 configuration under the operation of PWM1 and PWM2. Figure 14a shows a waveform with the significant voltage levels of the converter. As expected from the simulations, an intermediate voltage of 19.5V is achieved for a duty cycle of 40% with the second VR stage 5 having the form of the first topology Tl. Figure 14a also presents the second voltage reduction stage provided by the first VR stage 1 having the form of the third topology T3, operating with a duty cycle of 25% and producing an output voltage of 11.2V. Figure 14b shows the PWM modes applied to the converter and its switching period, together with the input and output voltages of the converter. As expected, the input and output voltages agree well with the theoretical analysis presented hereinbefore.

Figure 14c shows experimental measurements of the voltage stress across the first switch SI and the second switch S2. For the same duty cycles of 40% and 25%, the voltage stress across the second switch S2 is essentially constant over the duty cycle and is equal to the input voltage. The voltage stress across the first switch SI is also shown and it can be seen that the voltage that the first switch SI blocks during transition between 'on' and 'off' states is the intermediate voltage across the first capacitor Ci, although the maximum voltage stress is related to the sum of the input and intermediate voltages. The switching losses generated by the overlap between current and voltage during the transition time decrease due to the lower voltage that is blocked during this transition. For operation in region 1, the inclusion of the second switch S2 in the converter 1 according to embodiments of the present invention with a duty cycle independent of the duty cycle of the first switch SI allows to improve the flexibility of the converter and decrease switching losses across the first switch SI.

The system can operate with a broad range of components. Fast recovery and Schottky diodes are examples of possible diode technologies that can be implemented. Additionally, the inductor selection is quite open, since the implemented inductors can be selected based on the current ripple specifications in each specific application. Inductors from lOOnFI to lOOmFI can be used, depending the current level and current ripple for each application. Since the capacitors of the ICD structure are part of the power stage, the best options are film or ceramic capacitors. The values of them will also depend on the specifications defined in the project.

1 converter

2 input port

3 output port

4 first voltage regulation stage

5 second voltage regulation stage

C_mter intermediate capacitor

Dp₅ diode in parallel with the scond voltage regulation stage

T1 first topology

L single inductor in first topology

T2 second topology

I_i_2i first inductor in second topology

D _2I first diode in second topology

I__T22 second inductor in second topology

D ₂₂ second diode in second topology

Pi_2i first point in second topology located between the cathode of the first diode and the first inductor

Pi₂₂ second point in second topology located between the anode of the second diode and the second inductor

D ₂₃ third diode in second topology

T3 third topology

l__T3i first inductor in third topology

D _3I first diode in third topology

I__T32 second inductor in third topology

D ₃₂ second diode in third topology

Pi_3i first point in third topology located between the cathode of the first diode and the first inductor

Pi₃₂ second point in third topology located between the anode of the second diode and the second inductor

C _3i first capacitor in third topology

LI first inductor in the first VR stage

L2 first inductor in the second VR stage L3 second inductor in the first VR stage

L4 second inductor in the second VR stage

Dl, D3 first diode in the first VR stage D4 first diode in the second VR stage D5 second diode in the first VR stage

D6 second diode in the second VR stage

D7 third diode in the first VR stage D8 third diode in the second VR stage

Cl capacitor in first VR stage

C2 capacitor in second VR stage di first duty cycle

8₂ second duty cycle

51 first control switch

52 second control switch

V_out output voltage

V_m input voltage

V_INT intermediate voltage stage

Ci_NT intermediate capacitor

10, 20 device

10' modified device

21 controle module

sV error voltage

51 first switch

52 second switch

50 test bench setup

51 first voltmeter

52 second voltmeter

53 third voltmeter

Claims

1. A quadratic step-down converter (1) comprising:

an input port (2) for receiving an input DC voltage;

an output port (3) for outputting an output DC voltage; and

a first voltage regulation stage (4) in series with a second voltage regulation stage (5) between the input port (2) and the output port (3-;

wherein at least one of the first voltage regulation stage (4) and the second voltage regulation stage (5) comprises a first topology (Tl) comprising first (D3, D4) and second (D5, D6) diodes and first (LI, L2) and second inductors (L3, L4), wherein the first diode (D3, D4) and the first inductor (LI, L2) are in parallel with the second diode (D5, D6) and the second inductor (L3, L4).

2. A converter (1) according to claim 1, wherein the first topology further comprises a third diode configured to connect a point between the first inductor and the first diode with a point between the second inductor and the second diode.

3. A converter (1) according to claim 1, wherein the first topology further comprises a first capacitor connected between a first point between the first inductor and the first diode and a second point between the second inductor and the second diode.

4. A converter (1) according to any preceding claim, wherein the first voltage regulation stage comprises the first topology and the second voltage regulation stage comprises a third inductor.

5. A converter (1) according to any preceding claim, wherein the first voltage regulation stage comprises a third inductor and the second voltage regulation stage comprises the first topology.

6. A converter (1) according to any preceding claim, wherein the first voltage regulation stage and the second voltage regulation stage comprise the first topology.

7. A converter (1) according to any preceding claim, further comprising a first switch

connected between the first voltage drop stage and the second voltage drop stage.

8. A converter (1) according to any preceding claim, further comprising a second switch connected in parallel with the first voltage regulation stage and the second voltage regulation stage.

9. Apparatus (10, 20) comprising:

a converter (1) according to any preceding claim; and a control module (21);

wherein the control module (21) is configured to control a duty cycle of the converter (1).

10. Apparatus (10, 20) according to claim 9, wherein the control module (21) is configured to, in response to detecting a failure of a diode (D3, D4, D5, D6) comprised in the first voltage stage (4) or the second voltage stage (5), modify the duty cycle of the converter

(1).