EP3469625A4 - Thermocompression bonding with raised feature - Google Patents

Thermocompression bonding with raised feature Download PDF

Info

Publication number
EP3469625A4
EP3469625A4 EP16904801.4A EP16904801A EP3469625A4 EP 3469625 A4 EP3469625 A4 EP 3469625A4 EP 16904801 A EP16904801 A EP 16904801A EP 3469625 A4 EP3469625 A4 EP 3469625A4
Authority
EP
European Patent Office
Prior art keywords
thermocompression bonding
raised feature
raised
feature
thermocompression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP16904801.4A
Other languages
German (de)
French (fr)
Other versions
EP3469625A1 (en
Inventor
Christopher Gudeman
Paul Rubel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innovative Micro Technology
Original Assignee
Innovative Micro Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovative Micro Technology filed Critical Innovative Micro Technology
Publication of EP3469625A1 publication Critical patent/EP3469625A1/en
Publication of EP3469625A4 publication Critical patent/EP3469625A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/037—Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036
EP16904801.4A 2016-06-09 2016-06-09 Thermocompression bonding with raised feature Withdrawn EP3469625A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/036593 WO2017213652A1 (en) 2016-06-09 2016-06-09 Thermocompression bonding with raised feature

Publications (2)

Publication Number Publication Date
EP3469625A1 EP3469625A1 (en) 2019-04-17
EP3469625A4 true EP3469625A4 (en) 2020-03-04

Family

ID=60578853

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16904801.4A Withdrawn EP3469625A4 (en) 2016-06-09 2016-06-09 Thermocompression bonding with raised feature

Country Status (3)

Country Link
EP (1) EP3469625A4 (en)
JP (1) JP6755558B2 (en)
WO (1) WO2017213652A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113336182B (en) * 2021-05-19 2023-05-26 中山大学南昌研究院 Micro-electromechanical system packaging structure and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000263533A (en) * 1999-03-16 2000-09-26 Sumitomo Metal Electronics Devices Inc Ceramic base and its manufacture
US20070048898A1 (en) * 2005-08-26 2007-03-01 Innovative Micro Technology Wafer level hermetic bond using metal alloy with raised feature

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809097B1 (en) * 2010-09-22 2014-08-19 Crystal Solar Incorporated Passivated emitter rear locally patterned epitaxial solar cell
US9028628B2 (en) * 2013-03-14 2015-05-12 International Business Machines Corporation Wafer-to-wafer oxide fusion bonding
US9305890B2 (en) * 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000263533A (en) * 1999-03-16 2000-09-26 Sumitomo Metal Electronics Devices Inc Ceramic base and its manufacture
US20070048898A1 (en) * 2005-08-26 2007-03-01 Innovative Micro Technology Wafer level hermetic bond using metal alloy with raised feature

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
-: "LOCOS", WIKIPEDIA, THE FREE ENCYCLOPEDIA, 28 April 2016 (2016-04-28), XP055660339, Retrieved from the Internet <URL:https://en.wikipedia.org/w/index.php?title=LOCOS&oldid=717637282> [retrieved on 20200121] *
ANTELIUS M ET AL: "Small footprint wafer-level vacuum packaging using compressible gold sealing rings", JOURNAL OF MICROMECHANICS & MICROENGINEERING, INSTITUTE OF PHYSICS PUBLISHING, BRISTOL, GB, vol. 21, no. 8, 085011, 30 June 2011 (2011-06-30), XP020208862, ISSN: 0960-1317, DOI: 10.1088/0960-1317/21/8/085011 *
FAN J ET AL: "Low Temperature Cu-to-Cu Bonding for Wafer-Level Hermetic Encapsulation of 3D Microsystems", ELECTROCHEMICAL AND SOLID-STATE LETTERS, THE ELECTROCHEMICAL SOCIETY, vol. 14, no. 11, 23 September 2011 (2011-09-23), US, pages H470 - H474, XP055659240, ISSN: 1099-0062, DOI: 10.1149/2.025111esl *
KIM J ET AL: "A thermocompressive bonding method using a pure sputtered Au layer and its wafer scale package application", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AVS / AIP, MELVILLE, NEW YORK, NY, US, vol. 26, no. 4, 12 August 2008 (2008-08-12), pages 1363 - 1367, XP012114295, ISSN: 1071-1023, DOI: 10.1116/1.2952461 *
LAPISA M ET AL: "Wafer-level capping and sealing of heat sensitive substances and liquids with gold gaskets", SENSORS AND ACTUATORS A: PHYSICAL, vol. 201, 22 July 2013 (2013-07-22), NL, pages 154 - 163, XP055659234, ISSN: 0924-4247, DOI: 10.1016/j.sna.2013.07.007 *
MALIK N ET AL: "Al-Al thermocompression bonding for wafer-level MEMS packaging", 2013 TRANSDUCERS & EUROSENSORS XXVII: THE 17TH INTERNATIONAL CONFERENCE ON SOLID-STATE SENSORS, ACTUATORS AND MICROSYSTEMS, JUNE 16-20, 2013, BARCELONA, SPAIN, IEEE, PISCATAWAY, NJ, USA, 16 June 2013 (2013-06-16), pages 1067 - 1070, XP032499599, DOI: 10.1109/TRANSDUCERS.2013.6626955 *
See also references of WO2017213652A1 *
TABE M ET AL: "Electron Field Emission from Silicon Nanoprotrusions", 2001 6TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, OCTOBER 22-25, 2001, SHANGHAI, CHINA, PROCEEDINGS, IEEE, PISCATAWAY, NJ, USA, vol. 2, 22 October 2001 (2001-10-22), pages 1378 - 1382, XP010576232, ISBN: 978-0-7803-6520-9 *
TOFTEBERG H R ET AL: "Wafer-level Au-Au bonding in the 350-450 °C temperature range", JOURNAL OF MICROMECHANICS & MICROENGINEERING, INSTITUTE OF PHYSICS PUBLISHING, BRISTOL, GB, vol. 24, no. 8, 084002, 22 July 2014 (2014-07-22), XP020268126, ISSN: 0960-1317, [retrieved on 20140722], DOI: 10.1088/0960-1317/24/8/084002 *

Also Published As

Publication number Publication date
JP2019523983A (en) 2019-08-29
WO2017213652A1 (en) 2017-12-14
EP3469625A1 (en) 2019-04-17
JP6755558B2 (en) 2020-09-16

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