EP3326059A4 - IMPLEMENTING CHARGING / STORAGE RELEASE ACQUISITION INSTRUCTIONS USING LOADING / STORAGE OPERATION WITH DMB OPERATION - Google Patents

IMPLEMENTING CHARGING / STORAGE RELEASE ACQUISITION INSTRUCTIONS USING LOADING / STORAGE OPERATION WITH DMB OPERATION Download PDF

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Publication number
EP3326059A4
EP3326059A4 EP15899072.1A EP15899072A EP3326059A4 EP 3326059 A4 EP3326059 A4 EP 3326059A4 EP 15899072 A EP15899072 A EP 15899072A EP 3326059 A4 EP3326059 A4 EP 3326059A4
Authority
EP
European Patent Office
Prior art keywords
storage
loading
dmb
acquisition instructions
implementing charging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP15899072.1A
Other languages
German (de)
French (fr)
Other versions
EP3326059A1 (en
Inventor
Matthew Ashcraft
Christopher Nelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ampere Computing LLC
Original Assignee
Ampere Computing LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ampere Computing LLC filed Critical Ampere Computing LLC
Publication of EP3326059A1 publication Critical patent/EP3326059A1/en
Publication of EP3326059A4 publication Critical patent/EP3326059A4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
EP15899072.1A 2015-07-21 2015-07-21 IMPLEMENTING CHARGING / STORAGE RELEASE ACQUISITION INSTRUCTIONS USING LOADING / STORAGE OPERATION WITH DMB OPERATION Pending EP3326059A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/041322 WO2017014752A1 (en) 2015-07-21 2015-07-21 Implementation of load acquire/store release instructions using load/store operation with dmb operation

Publications (2)

Publication Number Publication Date
EP3326059A1 EP3326059A1 (en) 2018-05-30
EP3326059A4 true EP3326059A4 (en) 2019-04-17

Family

ID=57835180

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15899072.1A Pending EP3326059A4 (en) 2015-07-21 2015-07-21 IMPLEMENTING CHARGING / STORAGE RELEASE ACQUISITION INSTRUCTIONS USING LOADING / STORAGE OPERATION WITH DMB OPERATION

Country Status (4)

Country Link
EP (1) EP3326059A4 (en)
JP (1) JP6739513B2 (en)
CN (2) CN110795150A (en)
WO (1) WO2017014752A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0679993A2 (en) * 1994-04-28 1995-11-02 Hewlett-Packard Company A computer apparatus having special instructions to force ordered load and store operations
US20050273583A1 (en) * 2004-06-02 2005-12-08 Paul Caprioli Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
US20080163220A1 (en) * 2006-12-28 2008-07-03 Cheng Wang Efficient and consistent software transactional memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000181891A (en) * 1998-12-18 2000-06-30 Hitachi Ltd Shared memory access order guarantee method
US7552317B2 (en) * 2004-05-04 2009-06-23 Sun Microsystems, Inc. Methods and systems for grouping instructions using memory barrier instructions
US7725618B2 (en) * 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
EP2203828A1 (en) * 2007-10-18 2010-07-07 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory
GB2461716A (en) * 2008-07-09 2010-01-13 Advanced Risc Mach Ltd Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events.
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US8935513B2 (en) * 2012-02-08 2015-01-13 International Business Machines Corporation Processor performance improvement for instruction sequences that include barrier instructions
US9582276B2 (en) * 2012-09-27 2017-02-28 Apple Inc. Processor and method for implementing barrier operation using speculative and architectural color values
US9442755B2 (en) * 2013-03-15 2016-09-13 Nvidia Corporation System and method for hardware scheduling of indexed barriers
US9477599B2 (en) * 2013-08-07 2016-10-25 Advanced Micro Devices, Inc. Write combining cache microarchitecture for synchronization events

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0679993A2 (en) * 1994-04-28 1995-11-02 Hewlett-Packard Company A computer apparatus having special instructions to force ordered load and store operations
US20050273583A1 (en) * 2004-06-02 2005-12-08 Paul Caprioli Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
US20080163220A1 (en) * 2006-12-28 2008-07-03 Cheng Wang Efficient and consistent software transactional memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2017014752A1 *

Also Published As

Publication number Publication date
WO2017014752A1 (en) 2017-01-26
CN108139903B (en) 2019-11-15
CN110795150A (en) 2020-02-14
EP3326059A1 (en) 2018-05-30
CN108139903A (en) 2018-06-08
JP2018523235A (en) 2018-08-16
JP6739513B2 (en) 2020-08-12

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