EP3063873A1 - Driven dual phase lock loop - Google Patents

Driven dual phase lock loop

Info

Publication number
EP3063873A1
EP3063873A1 EP13789233.7A EP13789233A EP3063873A1 EP 3063873 A1 EP3063873 A1 EP 3063873A1 EP 13789233 A EP13789233 A EP 13789233A EP 3063873 A1 EP3063873 A1 EP 3063873A1
Authority
EP
European Patent Office
Prior art keywords
phase
input
frequency
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13789233.7A
Other languages
German (de)
French (fr)
Inventor
Steve Tanner
Yazhou Zhao
Pierre-André Farine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ecole Polytechnique Federale de Lausanne EPFL
Original Assignee
Ecole Polytechnique Federale de Lausanne EPFL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytechnique Federale de Lausanne EPFL filed Critical Ecole Polytechnique Federale de Lausanne EPFL
Priority to PCT/EP2013/072847 priority Critical patent/WO2015062663A1/en
Publication of EP3063873A1 publication Critical patent/EP3063873A1/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Abstract

The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal (LOCK), - a digital phase and frequency comparator (110), - a charge pump (111), and - an analogue phase comparator (120). The loop is essentially characterized in that it further comprises a switch (130) equipped with an output connected to the loop filter (140), and with two inputs, this switch being able to selectively connect the first input, originating from the analogue phase comparator, to its output in response to the lock indication signal; and its second input, originating from the digital phase and frequency comparator, to its output, in the absence of the lock indication signal.

Description

Description

LOCKED LOOP AND CONTROLLED DUAL STAGE

Technical area

[0001] The present invention relates to the field of phase-locked loops or phase locked loops generally known PLL (for "Phase-Locked Loop" in English).

[0002] The PLL is an electronic circuitry for slaving the phase of the output signal on the phase of the input signal, and which also allow to slave a frequency of the output signal to a multiple of the signal frequency input.

State of the art

[0003] A conventional phase locked loop comprises:

- a phase comparator,

- a charge pump,

- a loop filter,

- a voltage controlled oscillator (VCO Voltage Controlled Oscillator for English year), and

- a frequency divider.

[0004] PLLs are used primarily as frequency synthesizers (generating a high frequency from a reference frequency) in areas of very wide applications covering telecommunications, radio frequency, computers, etc.

[0005] PLL performance is affected in particular by intrinsic noise related to electronic circuit components or by extrinsic noise-related operating conditions.

[0006] In particular, the present PLL phase noise it is generally desirable to minimize.

[0007] It is known from US2002 / 0158621 a dual PLL mode that includes a digital branch and an analog branch, both connected to the charge pump.

[0008] I ntroduced u ire analog branch in u u PLL is not interesting solution that reduces the phase noise. Indeed, an analog circuit chosen with a high linearity introduces less phase noise than a digital circuit, the limited linearity is obtained by averaging.

Disclosure of the invention

[0009] A main object of the present invention is to improve the prior art solution.

[0010] More specifically, according to a first of its objects, the invention relates to a phase locked loop adapted to lock the frequency and phase of an output signal on the frequency and phase of an input signal , this loop comprising:

- a loop filter with an inlet,

- a voltage controlled oscillator comprising an output on which it generates the output signal and having an input electrically connected to an output of the loop filter,

- a digital phase and frequency comparator which one input is electrically connected to an output of the frequency divider and whose other input is connected to the input signal,

- a frequency divider having an input electrically connected to the output of the voltage controlled oscillator and whose output feeds the digital phase comparator and frequency,

- a phase locking and frequency detector which outputs a phase lock indication signal only when both inputs of the digital phase comparator and frequency have the same phase,

- a charge pump having an input electrically connected to an output of the digital phase comparator and frequency, and

- an analog phase comparator whose one input is electrically connected to an output of the frequency divider and whose other input is electrically connected to the input signal.

[001 1] It is essentially characterized in that it further comprises:

- a switch having an output electrically connected to the input of the loop filter, a first input and a second input, said switch being adapted to selectively connect the first input from the phase analog comparator at its output in response to the signal locking indication; and its second input, from the digital phase comparator and frequency at its output in the absence of the locking signal indication.

[0012] Preferably, the frequency lock detector is electrically connected to the switch, so that the frequency lock indication signal may control the switching of said switch.

[0013] Preferably, the phase comparator is a passive analog multiplier.

[0014] Provision may be an analog branch amplifier whose inputs are electrically connected to the outputs of the phase analog comparator and whose outputs are electrically connected to the switch. This amplifier has in this case the function of increasing the gain and to convert a voltage signal into a current signal.

[0015] Provision may be also an analog filter branch having inputs electrically connected to the outputs of the phase analog comparator and whose outputs are electrically connected to the analog amplifier branch entries.

[0016] Preferably, the analog branch amplifier is an operational transconductance amplifier.

[0017] According to another of its objects, the invention relates to an atomic clock comprising a phase locked loop according to the invention.

[0018] Finally, according to another of its objects, the invention relates to a timepiece comprising an atomic clock according to the invention.

[0019] According to the invention, and contrary to US2002 / 0158621 supra, the charge pump is connected at the digital phase comparator and the digital frequency branch, and not to the phase comparator of the analog branch , which improves the signal to noise ratio, the charge pump generally suffer from nonlinearities.

Brief Description of Drawings

[0020] Other features and advantages of the present invention will appear more clearly on reading the following description given by way of illustrative and nonlimiting example and with reference to the appended figures in which:

[0021] - Figure 1 illustrates one embodiment of a PLL according to the invention,

[0022] - Figure 2 illustrates an embodiment of an analog comparator passive phase according to the invention,

[0023] - Figure 3 illustrates an embodiment of an analog amplifier branch according to the invention,

[0024] - Figure 4 illustrates another embodiment of an analog comparator passive phase according to the invention,

[0025] - Figure 5 illustrates a fitted atomic clock of a phase-locked loop according to the invention, and

[0026] - Figure 6 illustrates a timepiece equipped with an atomic clock according to the invention.

Mode (s) of the invention

[0027] As illustrated in Figure 1, the phase locked loop 100 according to the invention, hereinafter PLL includes a digital phase and frequency comparator 1. 10

[0028] An input signal IN, also called reference signal enters the PLL frequency f_in and emerges as an output signal OUT to the f_out frequency.

[0029] The PLL includes a digital branch DIGIT (dashed in Figure 1) and a loop FBL against reaction (for FEEDBACK LOOP English, dashed in Figure 1). By "branch" means all electronic components arranged in series between the input of the PLL and a loop filter 140.

[0030] The Digital DIGIT branch comprises a digital phase comparator and a frequency of 1 10, and a charge pump 1 1 1.

[0031] The input signal IN is fed the input of the digital phase comparator and a frequency of 1. 10

[0032] The digital phase comparator and a frequency of 1 10 is a digital circuit (non-linear). Locking out, it outputs a correction signal COR as high or low pulses of which the number is used to control a voltage controlled oscillator 150, the high pulses to increase the frequency of the voltage controlled oscillator 150 and low pulses for decreasing the frequency of the voltage controlled oscillator 150. in the locking, it outputs a correction signal COR equal to 0 V.

[0033] It provides a charge pump 1 1 1 which transforms the pulses of the correction signal COR current pulses, and which is capable of being connected to a loop filter 140. The charge pump 1 1 1 is an inherently non-linear electronic component.

[0034] Preferably, the PLL comprises a loop filter 140 which filters, that is to say to limit the bandwidth of the correction signal COR. The loop filter 140 also serves to limit the speed control of the PLL. For this, the filter 140 is typically a passive low pass filter.

[0035] At the input of the loop filter 140, the correction signal COR is a current signal; and at the output of loop filter 140, the correction signal COR is a voltage signal.

[0036] For simplification the COR signal is illustrated as a single signal, in fact it may be a differential signal, in this case between the IN input signal and the divided signal DIV described later.

[0037] The loop compensation COR filtered by the filter signal 140 is fed as input to a voltage controlled oscillator 150 (VCO Voltage Controlled Oscillator for English year).

[0038] The voltage controlled oscillator 150 is an oscillator circuit whose oscillation frequency is controlled by the input voltage of this circuit, in this case by the filtered correction signal COR.

[0039] At the output of the voltage controlled oscillator 150 the output signal OUT is supplied as output of the PLL. Previously, it may be amplified by an amplifier, in this case a power amplifier (not shown).

[0040] The output signal OUT is also fed as input to the loop FBL against reaction. Loop response against

[0041] The loop FBL against reaction comprises a frequency divider 160.

Preferably, the frequency divider 160 is programmable.

[0042] In this case, the output signal OUT, signal against feedback is fed to the input of frequency divider 160 which generates at its output an output signal DIV, hereinafter referred to as divided signal. The frequency of the divided signal DIV is equal to the f_out frequency of the output signal OUT divided by a number N which depends on the type of frequency divider 160 implemented. In this case N can be arbitrary and not a natural number.

[0043] It can be provided that the loop FBL reaction against further comprises a duty cycle controller 170, either as standalone unit or integrated, for example integrated to the frequency divider 160.

[0044] Preferably, the duty cycle controller 170 is configured to transform the input signal to output signal whose duty cycle is closer to 50%, eg 50% +/- 10%, which improves analog branch performance. Indeed, the digital phase comparator and a frequency of 1 10 of the digital branch is triggered on the rising edges of its input signals, and is insensitive to the duty cycle. However, in an analog part, a phase analog comparator 120 explained later is responsive to the average value of the input signal. A duty ratio of 50% ensures the analog comparator to operate at an optimum point, or in the middle of its dynamics.

[0045] After the potential duty cycle controller 170, the divided signal DIV is supplied as input to the digital DIGIT branch of the PLL.

[0046] In this case, the divided signal DIV is fed the input of the digital phase comparator and a frequency of 1 10, so that it measures the difference between the phase of the divided signal DIV and the phase of the signal d input iN, as well as the difference between the frequency divided signal DIV and f_in frequency of the input signal iN. The high or low pulses issued by the digital phase comparator and a frequency of 1 10, transformed into current pulses by the charge pump 1 1 1, and converted into voltage by the loop filter 140 can increase or decrease the value of the frequency of the voltage controlled oscillator 150 according to the value of the measured difference in phase and frequency by the phase comparator. The value of the frequency of the output signal f_out can thus be corrected so that it complies with the equation f_out = f_in / N. In this case, it is said that the frequency is locked.

[0047] Advantageously, the reaction against loop further comprises a phase shifter 180, in this case 90 °. The divided signal DIV is applied to the input of the phase shifter 180, in this case downstream of the duty cycle controller 170. At the output of the phase shifter 180, the output DIV90 signal of the phase shifter 180 is the input signal whose DIV phase is rotated by 90 °.

[0048] Upon initialization of the analog part, the digital part is locked. Now, if the phase comparator of the analog branch detects an error, it is a noise PLL which then risks losing the lock. To limit this risk, it is expected that the analog comparison stage 120 generates the initialization of the analog branch a zero error signal (in this case a voltage of 0 volts). Through the phase shifter 180, the DIV90 signal is phase shifted by 90 ° relative to the input signal IN. Since both IN and DIV90 signals are fed to the input of the analog comparison stage 120, the latter property generates a signal equal to 0 V at the initialization of the analog branch. Indeed, the operating point of the digital phase comparator and a frequency of 1 10 of the digital branch (correction signal equal to 0 when the inputs are in phase) is different from the operating point of the phase comparator of the analog branch ( PHA output signal equal to 0 when the inputs are phase-shifted by 90 °).

analog branch [0049] The PLL takes further com u branch ana logiq ue ANALOG (dotted line Figure 1). In this case the phase noise generated by the analog branch is less than that generated by the digital branch, in particular because of its greater linearity compared to blocks of the digital branch, or the digital phase and frequency comparator 10 January and the charge pump 1 1 1, which are inherently non-linear blocks.

[0050] The analog part ANALOG includes the phase comparator 120.

[0051] Preferably, the analog phase comparator 120 is an analog multiplier, preferably passive, of which an embodiment is illustrated in Figure 2. The multiplier is more commonly known mixer by Anglicism. In Figure 2, RFp and RFn are the differential inputs to the END signal, while LOP and LON are the differential inputs to the signal DIV90. IFP and I Fn are the outputs. The advantage of this embodiment lies in particular in that the switching transistors are used and do not add very little thermal noise to the signal. The AC switch is implemented at high frequencies and can be easily filtered.

[0052] A change of the analog multiplier of Figure 2 is illustrated in Figure 4. In Figure 2, a transconductor g m is disposed at the RFp and RFn entries; in Figure 4, this transconductor is removed, which is possible thanks to the sufficient amplitude of DIV90 signal on one of the RFp and RFn inputs. In addition, a resistor R1, R2 is added in series with C1 and capacitor C2, respectively, so as to improve the equivalent input impedance and forming a low-pass filter, in the first-order case.

[0053] An analog multiplier passive has the advantage to have a very linear output and little flicker noise (flicker noise by Anglicism) and thermal noise. It can be used as a phase comparator, but not as the frequency comparator. It can be used only with fixed frequency, ie when the PLL is already locked. In this case, good linearity and low noise can reduce the phase noise compared to a digital comparator or even an active multiplier.

[0054] As the output of the analog com parateur phase 120 is a voltage, is preferably provided at least one electronic component for converting this voltage into current, which is used for supplying the input of the loop filter 140. [0055 ] for this purpose, the analog aNALOG branch may further comprise an analog amplifier branch.

[0056] An embodiment of an analog branch amplifier 122 is shown in Figure 3. In this example, the circuit is symmetrical and makes it possible, for reasons here partially exposed, to obtain a reduced gain and a band busy and satisfactory stability without degrading noise.

[0057] The analog branch amplifier 122 transforms an input voltage to output current. The function is the same as that of the charge pump 1 1 1 When the analog branch is activated, the loop filter 140 is supplied only by the load output of the analog amplifier 122 branch.

[0058] In this case, there is provided an operational transconductance amplifier OTA or "operational transconductance amplifier" in English, which is an inherently linear electronic circuit, i.e., the output current is a linear function of the differential input voltage.

[0059] Thanks to this feature, a single loop filter 140 may be used for both digital and analog branch leg.

[0060] In Figure 3, the OTA is based on a symmetrical fully differential amplifier. The differential input transistors M5 and M6 are PMOS, that generate less noise than NMOS. With a bias current Vbias, the PMOS transistor M4 copies the current from a bias block BIAS according to a certain ratio. A supply voltage Vcmfb originated from a CMFB block and controls the PMOS transistor M1 1, M12 to adjust and stabilize the output level of the analog branch when the PLL is locked. A first stage of the OTA is constituted by the NMOS transistors M7 and M8, connected to nodes Vb1 and Vb2. Two NMOS transistors M9 and M10 form two current mirrors for copying the output current of the first stage to a second stage according to a certain ratio. Then M13 current bridges and M14 (NMOS transistors) are connected in a cross coupling to increase the bandwidth and the ΓΟΤΑ phase margin with the load of the loop filter, to ensure system stability loop locked.

[0061] As ΓΟΤΑ is activated once the PLL is locked, the gain, which is inherently the sensitivity of the response of the detected error, becomes relatively low. In addition, the compromise between noise and phase margin is facilitated.

[0062] As an alternative, provision can be an operational amplifier as an analog branch amplifier 122 but the response thereof being in tension, it is preferred an OTA, which is still consistent with the digital branch which generates a current signal to the output of the charge pump.

[0063] There may also be an analog branch filter 121, in particular interposed between the analog comparison stage 120 and the analog amplifier branch, as shown in Figure 1, and which smoothes the output voltage of analog comparator stage 120.

[0064] The analog branch filter 121 and analog branch amplifier 122 may be self-blocks as illustrated in Figure 1, or integrated, for example to the phase comparator.

[0065] The input signal IN is supplied as input to the analogue branch, in this case at the input of phase comparator 120. Another input of the phase comparator is connected to DIV90 output signal of the phase shifter 180.

[0066] At the output of the phase comparator, a PHA phase signal is output, in this case a voltage signal. This voltage is filtered by the analog filter 121 branch then amplified by the analog branch amplifier 122 whose output is a current signal, can be connected to the input of loop filter 140.

[0067] advantageously provides for selectively connecting the loop filter 140:

- the correction signal COR from the charge pump 1 1 1, or

- the phase signal PHA of the phase comparator, in the filtered and amplified species. [0068] Selecting one of these inputs of the loop filter 140 is performed by a switch, in this case by a multiplexer 130 that selectively allows the activation of the analog part or the activation of the digital industry.

multiplexer 130

[0069] The multiplexer 130 has its output connected to the loop filter 140, and connected at its input:

- the correction signal COR from the charge pump 1 1 1, or

- the phase signal PHA of the phase comparator, in the filtered and amplified species.

[0070] The input selection of the multiplexer 130 is preferably carried out through a control signal, in particular the LOCK signal described below.

Operation

[0071] Upon initialization of the PLL, the digital branch is enabled by default: the input of the loop filter 140 is connected to the correction signal COR from the charge pump 1 1 1.

[0072] The digital phase comparator and a frequency of 1 10 first operates in frequency detection mode.

[0073] The digital phase comparator and a frequency of 1 10 and the charge pump 1 1 1 can control the f_out frequency of the output signal OUT of the voltage controlled oscillator, via the input voltage thereof , for changing said frequency f_out until the difference between the frequency divided signal DIV and f_in frequency of the input signal iN is zero, i.e. f_out = f_in / N.

[0074] When the difference between the frequencies is zero, the digital phase comparator and a frequency of 1 10 of the digital branch automatically switches to phase comparator mode. When the difference between the phases is also zero, i.e. in the linear regime of the digital phase comparator and a frequency of 1 10 of the digital branch, the PLL is said to be locked.

[0075] The digital phase comparator and a frequency of 1 10 includes a phase lock detector and a frequency of 1 13, which outputs a LOCK phase lock indication signal only when both inputs of the digital phase comparator and frequency have the same phase.

[0076] The detection of the LOCK indication signal is used to control the switch 130, thus activating the analog part or the digital part.

[0077] In this case, the multiplexer 130 is controlled by the LOCK indication signal that, upon detection of entry, selects the input of the analog part so that the input of loop filter 140 is then connected to the phase signal PHA of the phase comparator, in the filtered and amplified species.

[0078] The charge pump 1 1 1 is a component whose impulse response is nonlinear. As the charge pump 1 1 1 is present only in the digital part and the analog part is free, the behavior of the analog part is linear, which reduces the phase noise and improves performance of the PLL.

[0079] The analog part has a linear behavior and allows, by the phase comparator to compare the phase of the input signal IN to the phase of the divided signal, in this case the phase of the output signal of the phase shifter DIV90 180.

[0080] In the event of disturbance such as the PLL loses lock, the LOCK indication signal from the digital phase comparator and a frequency of 1 10 passes to 0, which pilot for example the multiplexer 130 to activate the digital branch instead of the analog branch. When the digital branch allowed to lock again the PLL, the LOCK signal becomes active and allows again to select the analog comparator in a stable operating mode.

[0081] The digital branch is successful in locking but have a high phase noise. Analog branch is not very effective in locking but performing phase noise, once locked. The invention advantageously uses the complementarity of the two branches and automatic switching from one to another to obtain a PLL having at overall better performance.

Phase-locked loop 100 may be incorporated in an atomic clock 200. The atomic clock 200 can be integrated in a timepiece 300.

Nomenclature

100 PLL

January 10 digital phase comparator and frequency

1 charge pump

1 12 Digital branch amplifier

January 13 phase locking and frequency detector

120 analog phase comparator

121 analog filter branch

122 analog amplifier branch

130 multiplexer

140 loop filter

150 voltage controlled oscillator (VCO)

160 frequency divider

170 duty cycle controller

phase shifter 180

200 atomic clock

300 timepiece

FBL loop against reaction

ANALOG analog branch

DIGIT digital branch

Claims

phase locked loop (100) adapted to lock the frequency and phase of an output signal (OUT) on the frequency and phase of an input signal (IN), this loop comprising:
- a loop filter (140) provided with an inlet,
- a voltage controlled oscillator (150) having an output on which it generates the output signal and having an input electrically connected to an output of the loop filter (140),
- a digital phase and frequency comparator (1 10) having an input electrically connected to an output of the frequency divider (160) and whose other input is connected to the input signal (IN),
- a frequency divider (160) having an input electrically connected to the output of the voltage controlled oscillator (150), whose output feeds the digital phase comparator and frequency,
- a phase and frequency lock detector (1 13), which emits a phase lock indication signal (LOCK) only when both inputs of said digital phase and frequency comparator (1 10) have the same phase ,
- a charge pump (1 1 1) having an input electrically connected to an output of the digital phase comparator and frequency (1 10), and
- a com parateur a phase nalogue (1 20) having an input electrically connected to an output of the frequency divider (160) and whose other input is electrically connected to the input signal (IN),
characterized in that it further comprises
- a switch (130) having an output electrically connected to the input of the loop filter (140), a first input and a second input; this switch being adapted to selectively connect the first input from the phase of the analog comparator (120) at its output in response to the lock indication signal; and its second input, from the digital phase comparator and frequency (1 10), at its output, in the absence of the locking signal indication.
2. Phase locked loop (100) of claim 1, wherein the phase locking and frequency detector (1 13) is electrically connected to the (130) switch, so that the lock indication signal frequency (LOCK) is adapted to control the switching of said switch (130).
3. Phase locked loop (100) according to any preceding claim, wherein the phase analog comparator (120) is a passive multiplier.
4. Phase locked loop (100) according to any preceding claim, wherein an output of the charge pump
(1 1 1) is electrically connected to the second input of the switch (130).
5. Phase-locked loop (100) according to any preceding claim, further comprising an analog amplifier branch (122) whose inputs are electrically connected to the outputs of the com parateu ra na log phase iq ue (1 20) and whose outputs are electrically connected to the switch (130).
6. Phase-locked loop (100) of claim 5, further comprising an analog filter branch (121) whose inputs are electrically connected to the analog comparator phase outputs (120) and whose outputs are electrically connected to the amplifier inputs of analog branch (122).
7. Phase-locked loop (100) according to any one of claims 5 or 6, wherein the analog amplifier branch (122) is an operational transconductance amplifier.
8. An atomic clock comprising a phase locked loop (100) according to any preceding claim.
9. Timepiece including an atomic clock according to claim 8.
EP13789233.7A 2013-10-31 2013-10-31 Driven dual phase lock loop Withdrawn EP3063873A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP2013/072847 WO2015062663A1 (en) 2013-10-31 2013-10-31 Driven dual phase lock loop

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Publication Number Publication Date
EP3063873A1 true EP3063873A1 (en) 2016-09-07

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Publication number Priority date Publication date Assignee Title
CN106452656B (en) * 2016-08-31 2019-05-14 成都市和平科技有限责任公司 A kind of radiofrequency signal interference system and method based on frequency synthesizer

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JP5284131B2 (en) * 2009-02-04 2013-09-11 株式会社東芝 Phase synchronization circuit and receiver using the same
JPWO2012143970A1 (en) * 2011-04-19 2014-07-28 三菱電機株式会社 Frequency synthesizer

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