EP3042391A1 - Verfahren zur herstellung eines substrats, substrat, metall-oxid-halbleiter-feldeffekttransistor mit einem substrat, mikroelektromechanisches system mit einem substrat, und kraftfahrzeug - Google Patents
Verfahren zur herstellung eines substrats, substrat, metall-oxid-halbleiter-feldeffekttransistor mit einem substrat, mikroelektromechanisches system mit einem substrat, und kraftfahrzeugInfo
- Publication number
- EP3042391A1 EP3042391A1 EP14747945.5A EP14747945A EP3042391A1 EP 3042391 A1 EP3042391 A1 EP 3042391A1 EP 14747945 A EP14747945 A EP 14747945A EP 3042391 A1 EP3042391 A1 EP 3042391A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- trench
- layer
- silicon carbide
- masking layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000000873 masking effect Effects 0.000 claims abstract description 51
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 51
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 46
- 238000001312 dry etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Definitions
- Metal oxide semiconductor field effect transistor with a substrate Metal oxide semiconductor field effect transistor with a substrate
- microelectromechanical system with a substrate and motor vehicle
- the present invention relates to a method of manufacturing a substrate, a substrate, a metal-oxide-semiconductor field effect transistor having a substrate, a microelectromechanical system having a substrate, and a motor vehicle.
- Substrates comprising a silicon carbide layer are finding increasing numbers
- Trench MOSFET Trench metal oxide semiconductor field effect transistor
- the substrate may further comprise a silicon dioxide layer, a
- Silicon nitride layer or comprise a silicon layer on which the
- Silicon carbide layer is deposited.
- a substrate (monocrystalline n-doped 4H-SiC substrate) is used whose
- Silicon carbide layer has a hexagonal crystal structure and is n-doped.
- An n-doped silicon carbide buffer layer is disposed between the silicon carbide layer and a low n-doped silicon carbide drift zone (n-drift zone).
- n-drift zone n-drift zone
- n-doped 4H-SiC substrate 10 Arranged on the n-doped 4H-SiC substrate 10 is a moderately p-doped silicon carbide (p " ) layer 20, which may be epitaxially grown or implanted on a portion of the p " layer 20 is a highly n-doped Silicon carbide layer (n + source) 30 may be arranged, which may be epitaxially grown or implanted and serves as a source terminal. In this case, a rear side of the 4H-SiC substrate 10 serves as a drain connection.
- p " silicon carbide
- n + source 30 n + source
- a p + terminal (p + -plug) 40 is implanted into the p " layer 20 so that an upper side of the p + -plug 40 connects to the top of the n + -source 30 and the p + -plug 40 can serve to define the channel potential
- the p " -layer 20 and the n + -source 30 are each provided with a recess
- the recesses have in cross section a same, constant width. Even the trench has, apart from a bottom area, this same width. Only in the bottom area, the width of the trench tapers due to the structuring, so that the trench has a cup-shaped profile in cross section. The trench is thus concave in cross section.
- the trench may be coated with a gate oxide after patterning.
- a highly doped implantation can take place in the bottom of the trench.
- a polysilicon gate 50 is deposited in the trench. This results in a vertical channel region 25 in the p " layer 20. This allows a higher packing density of transistors connected in parallel than in the case of transistors with a lateral channel region.
- the structurally-related transition from side wall of the trench to the bottom of the trench may in use lead to very high field strengths in this region, which are higher than a breakthrough threshold at which the
- Oxide layer is electrically broken in the case of blocking and the component is damaged. Disclosure of the invention
- a method according to claim 1 for producing a substrate for a metal-oxide-semiconductor field effect transistor or a microelectromechanical system is presented.
- the substrate comprises a silicon carbide layer.
- the method is characterized in that the method comprises the steps of: (a) dry etching a preliminary trench into the substrate using a patterned first one
- a masking layer wherein the dry etching is performed so as to leave a remainder of the first patterned masking layer, (b) applying a second masking layer at least on walls of the preliminary trench, and (c) dry etching using the remainder of the first
- step (b) may comprise: conforming the second masking layer, wherein a portion of the second
- Masking layer on walls of the preliminary trench another part is applied to a bottom of the preliminary trench and still another part on the rest of the structured first masking layer, and removing the further part and the still another part by dry etching.
- the portion of the masking layer on walls of the preliminary trench then protects the step of the trench during further etching.
- the method may further comprise implanting ions into the bottom of the preliminary trench after step (a) and before step (b).
- Step (a) may include: conforming the first
- Masking layer applying a patterned photoresist to the first Masking layer; and patterning the first masking layer by plasma etching using the photoresist.
- the structured first masking layer can thus be easily produced.
- the silicon carbide layer may have a hexagonal crystal structure, on which a moderately p-doped silicon carbide layer is arranged, wherein a highly n-doped silicon carbide layer is arranged on at least part of the moderately p-doped silicon carbide layer.
- the first masking layer may be conformally deposited on the highly n-doped silicon carbide layer and also etched in the moderately p-doped silicon carbide layer and in the highly n-doped one by etching in step (a)
- Silicon carbide layer are formed, wherein the recesses are disposed above the preliminary trench and have a same width in cross section, which corresponds to a width of the preliminary trench.
- Such a substrate is then suitable for a particularly breakdown-proof metal oxide semiconductor field effect transistor.
- a particularly breakdown-proof metal oxide semiconductor field effect transistor In such a
- Metal-oxide semiconductor field-effect transistor is then the trench filled to the stage with a dielectric. Furthermore, a gate electrode is arranged at least partially in the trench above the dielectric and also partially in the recesses, which comprises polycrystalline silicon, wherein a vertical channel region is formed by the arrangement in the moderately p-doped silicon carbide layer.
- a sufficiently thick dielectric can be realized which causes the field strengths occurring in the metal-oxide-semiconductor field-effect transistor to remain below the breakdown threshold.
- the dielectric may also cover the trench walls above the step.
- the microelectromechanical system comprises a substrate, which is produced by the method presented according to the invention.
- the substrate further comprises a silicon dioxide layer, a
- Silicon nitride layer or a silicon layer on which the Siliziumcarbid für is deposited A part of the trench above the step is completely formed in the silicon carbide layer.
- a motor vehicle according to claim 10 is further presented.
- the motor vehicle is provided with a circuit breaker comprising a metal oxide semiconductor field effect transistor proposed according to the invention.
- Figure 1 shows a trench MOSFET according to the prior art
- FIG. 2 shows an exemplary initial structure of a substrate for producing a stepped tapered trench in the substrate
- FIG. 3 shows an exemplary intermediate structure of the substrate
- FIG. 4 shows an exemplary further intermediate structure of the substrate
- FIG. 5 shows an exemplary still further intermediate structure of the substrate
- FIG. 6 shows an exemplary end structure of the substrate.
- Figures 2, 3 and 4 show exemplary structures of a substrate before and during the fabrication of a stepped tapered trench in the substrate.
- An exemplary starting material for the exemplary method of making the trench is an n-type hexagonal hexagonal silicon carbide layer
- n-drift zone Silicon carbide drift zone (n-drift zone) 10, between which an n-doped
- Silicon carbide buffer layer is arranged. Based on this, a moderately p-doped silicon carbide layer (p " layer) 20 is grown or implanted epitaxially on which a highly n-doped silicon carbide layer (n + source) 30 is epitaxially grown or implanted This n-doped silicon carbide layer 30 serves as a source A backside of the 4H-SiC substrate 10 serves as a drain terminal.
- p " layer) 20 is grown or implanted epitaxially on which a highly n-doped silicon carbide layer (n + source) 30 is epitaxially grown or implanted
- n-doped silicon carbide layer 30 serves as a source
- a backside of the 4H-SiC substrate 10 serves as a drain terminal.
- the trench 90 which is formed in FIGS. 2, 3, 4 and 5, has a stepped cross section with one step.
- the width of the trench 90 tapers down once so that an upper portion of the trench, above the stage, has the unrestrained width B1 and a lower portion of the trench, below the step, has the tapered width B2.
- a first masking layer 60 for example silicon dioxide
- a photoresist 70 over the first
- Masking layer 60 deposited and by photolithography a
- the structure is etched using the patterned photoresist and the patterned first masking layer 60 as a mask.
- the result is a preliminary trench with an unrestrained width B1.
- the patterned photoresist 70 is completely removed, but the structured first masking layer 60 is only partially removed so that a remainder 60 'of the structured first masking layer remains.
- the substrate etching may be preceded by a dry or wet chemical removal of the photoresist. The substrate etching then takes place exclusively by using the structured first masking layer 60 as mask, wherein a remainder 60 'of the structured first masking layer likewise remains.
- the resulting structure is shown by way of example in FIG.
- a second masking layer 65 is conformally applied to a surface of the remainder 60 'of the first masking layer, and the bottom and walls of the preliminary trench.
- the resulting structure is exemplified in FIG.
- the second masking layer 65 is removed on the surface of the remainder 60 'of the first masking layer as well as on the bottom of the preliminary trench, further etching causes the preliminary trench to be further recessed at the bottom in a tapered width B2, where B2 is less than B1 is.
- the part 65 'of the second masking layer is gradually removed from above.
- the remainder 60 'of the first masking layer is gradually removed.
- the etching is terminated. Any remaining material of the remainder 60 'and / or the part 65' can then be removed by wet chemical or dry chemical.
- the resulting structure is exemplified in FIG.
- the unrestrained width B1 and the tapered width B2 depend on the lithography used.
- the unrendered part can then have a width of 800 nanometers, for example.
- the distance from step 80 to the top of the n + source 30 may be 0.5 to 3 microns and the distance from the step 80 to the bottom of the tapered portion of the trench 90 may be about 0.2 to 2 microns.
- a dielectric can be deposited, which could fill, for example, the tapered portion of the trench 90 to 80 level.
- the dielectric may thinly cover walls of the trench above the step 80. It is also possible, after the first etching and before the removal of the photoresist, to carry out an ion implantation, which can be arranged deeper in the substrate.
- a polycrystalline silicon gate electrode 50 may be placed in the trench above the step such that a vertical channel region 25 is formed in the p " layer 20.
- the silicon carbide layer is deposited on a silicon dioxide layer, a silicon nitride layer or a silicon layer. Then, the part of the trench with unrestrained width completely in the
- Silicon carbide layer may be formed and formed the part of the trench with a tapered width completely in the layer on which the
- Silicon carbide layer is deposited.
- the step may coincide with the transition from the layer on which the silicon carbide layer is deposited to the silicon carbide layer.
- the portion of the tapered width trench may also completely penetrate the layer on which the silicon carbide layer is deposited.
- Ratios of unrestrained width to tapered width of 100 1 into consideration with tapered widths of 1 to 10 microns.
- the distance from the step to the top of the silicon carbide layer may be, for example, 1 to 10 microns, and the distance from the step to the bottom of the tapered part of the trench, or to the bottom of the layer to which the
- Silicon carbide layer is deposited may also be 1 to 10 microns.
- Suitable materials for the first and the second masking layer are, for example, silicon dioxide, silicon nitride, polysilicon or silicon carbide, wherein the first and the second masking layer may comprise identical and different materials, metal as material for one or both masking layers is also conceivable.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013217768.2A DE102013217768A1 (de) | 2013-09-05 | 2013-09-05 | Verfahren zur Herstellung eines Substrats, Substrat, Metall-Oxid-Halbleiter-Feldeffekttransistor mit einem Substrat, mikroelektromechanisches System mit einem Substrat, und Kraftfahrzeug |
PCT/EP2014/066951 WO2015032577A1 (de) | 2013-09-05 | 2014-08-07 | Verfahren zur herstellung eines substrats, substrat, metall-oxid-halbleiter-feldeffekttransistor mit einem substrat, mikroelektromechanisches system mit einem substrat, und kraftfahrzeug |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3042391A1 true EP3042391A1 (de) | 2016-07-13 |
Family
ID=51292972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP14747945.5A Withdrawn EP3042391A1 (de) | 2013-09-05 | 2014-08-07 | Verfahren zur herstellung eines substrats, substrat, metall-oxid-halbleiter-feldeffekttransistor mit einem substrat, mikroelektromechanisches system mit einem substrat, und kraftfahrzeug |
Country Status (5)
Country | Link |
---|---|
US (1) | US10636901B2 (de) |
EP (1) | EP3042391A1 (de) |
JP (1) | JP2016538729A (de) |
DE (1) | DE102013217768A1 (de) |
WO (1) | WO2015032577A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015113998A1 (de) * | 2015-08-24 | 2017-03-02 | Gottfried Wilhelm Leibniz Universität Hannover | Verfahren zur Herstellung eines Mikrozerspanwerkzeugs sowie Mikrozerspanwerkzeug |
CN108807177B (zh) * | 2017-05-05 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3471509B2 (ja) * | 1996-01-23 | 2003-12-02 | 株式会社デンソー | 炭化珪素半導体装置 |
US5741741A (en) * | 1996-05-23 | 1998-04-21 | Vanguard International Semiconductor Corporation | Method for making planar metal interconnections and metal plugs on semiconductor substrates |
US6656797B2 (en) * | 2001-12-31 | 2003-12-02 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation |
US6686244B2 (en) | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
JP4500530B2 (ja) * | 2003-11-05 | 2010-07-14 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
JP2006032655A (ja) | 2004-07-16 | 2006-02-02 | Kyoto Univ | 炭化珪素基板の製造方法 |
JP4491307B2 (ja) | 2004-09-21 | 2010-06-30 | トヨタ自動車株式会社 | 半導体装置およびその製造方法 |
JP5493275B2 (ja) | 2008-02-27 | 2014-05-14 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2009302510A (ja) | 2008-03-03 | 2009-12-24 | Fuji Electric Device Technology Co Ltd | トレンチゲート型半導体装置およびその製造方法 |
WO2010090024A1 (ja) | 2009-02-04 | 2010-08-12 | 日立金属株式会社 | 炭化珪素単結晶基板およびその製造方法 |
EP2258655B1 (de) | 2009-06-05 | 2012-04-25 | Acreo AB | Verfahren zur Herstellung einer Mikrostruktur von kristallinem SiC |
US9318558B2 (en) * | 2012-07-09 | 2016-04-19 | Hitachi, Ltd. | MOS field effect transistor |
-
2013
- 2013-09-05 DE DE102013217768.2A patent/DE102013217768A1/de not_active Ceased
-
2014
- 2014-08-07 JP JP2016539451A patent/JP2016538729A/ja active Pending
- 2014-08-07 US US14/917,009 patent/US10636901B2/en active Active
- 2014-08-07 WO PCT/EP2014/066951 patent/WO2015032577A1/de active Application Filing
- 2014-08-07 EP EP14747945.5A patent/EP3042391A1/de not_active Withdrawn
Non-Patent Citations (2)
Title |
---|
None * |
See also references of WO2015032577A1 * |
Also Published As
Publication number | Publication date |
---|---|
DE102013217768A1 (de) | 2015-03-05 |
JP2016538729A (ja) | 2016-12-08 |
US20160218208A1 (en) | 2016-07-28 |
US10636901B2 (en) | 2020-04-28 |
WO2015032577A1 (de) | 2015-03-12 |
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