EP3041784A1 - Method of forming deposited patterns on a surface - Google Patents
Method of forming deposited patterns on a surfaceInfo
- Publication number
- EP3041784A1 EP3041784A1 EP14824962.6A EP14824962A EP3041784A1 EP 3041784 A1 EP3041784 A1 EP 3041784A1 EP 14824962 A EP14824962 A EP 14824962A EP 3041784 A1 EP3041784 A1 EP 3041784A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- release agent
- wafer
- cavities
- bottom portions
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/30—Coatings
- H10F77/306—Coatings for devices having potential barriers
- H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/00373—Selective deposition, e.g. printing or microcontact printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/40—Optical elements or arrangements
- H10F77/413—Optical elements or arrangements directly associated or integrated with the devices, e.g. back reflectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/50—Encapsulations or containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/70—Surface textures, e.g. pyramid structures
- H10F77/707—Surface textures, e.g. pyramid structures of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
- B81C2201/0183—Selective deposition
- B81C2201/0188—Selective deposition techniques not provided for in B81C2201/0184 - B81C2201/0187
Definitions
- This disclosure relates generally to methods for forming deposited patterns on a surface and more particularly, the methods for forming anti-reflection coatings on selected areas of an optical window wafer used in wafer level packaging of optical elements.
- an optical window wafer (sometimes referred to as a cap wafer) has a plurality of cavities or recesses formed in a surface thereof, each recess being formed to provide a cavity (with vertically extending walls) associated with (spaced from and disposed over) a corresponding one of a plurality of IR detector (e.g., bolometers) arrays formed in a second, underlying wafer bonded to the cap wafer.
- the cap wafer also includes a patterned anti-reflective coating (ARC), thin film getters, if required, and bond structures.
- ARC patterned anti-reflective coating
- a window cap wafer with an anti- reflection coating for wafer level packaged IR bolometer detectors is currently done by coating the optical window through a shadow mask or by coating the whole surface (top surface and cavity surface) and polishing off the upper surface.
- a photolithographic resist lift-off method may also be used, but expensive capital equipment is required.
- the shadow mask adds the cost of the mask (often only good for a single use) and alignment tooling. Polishing requires precision polishing equipment and skilled operators. Both require cleaning to a higher level than is typical in the optics industry. Thus, patterning an anti-reflective coating on a surface can be difficult with traditional methods, which are 1. Shadow mask (limited by alignment tolerance, edge sharpness). 2.
- Photolithographic lift-off (ARCs are typically too thick for easy photoresist lift-off, and require capital equipment. Lift-off is an undesirable messy process in the semiconductor industry). 3. If over topology where recessed surface is to be coated and upper surface to be removed, polish off of upper surface may be used (requires precision optical polishing equipment). All of these have problematic issues when applied to the semiconductor world, particularly with cleanliness and particle control.
- the basic wafer level packaging process may be summarized as: Etch cavities in cap wafer; Deposit an ARC on the bottom of the cavity, Metallize a seal ring pattern on the top surface of the cap wafer surrounding the cavity; Deposit getter material on another portion of the top surface, if required; Apply solder to seal ring area; Bond to IR detector device wafer; and Saw into individual detector arrays.
- a method for forming a coating of material on selected portions of a substrate having a plurality of cavities formed in selected portions of a surface of the substrate, each cavity having outer, peripheral sidewalls extending outwardly from a floor of the cavity.
- the method includes: providing a structure having a release agent thereon; contacting top surfaces of the sidewalls with the portions of the contacted release agent being transferred to the top surfaces of the substrate while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure surface comprising: the release agent disposed on the top surfaces of the substrate and with the bottom portions of the cavities void of the release agent; exposing the surface of the intermediate structure to the material to blanket coat the material on both the release agent disposed on the top surface of the substrate and the bottom portions of the cavities; and exposing the intermediate structure having the coated release agent and the bottom portions to a process to selectively remove the release agent together with the coating material thereon from the top surface of the substrate while leaving the coating material on the bottom portions of the cavities.
- the method includes:
- a structure having a release agent thereon contacting top surface of the wafer with a portion of the release agent to transfer the release agent to the top surfaces of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure surface comprising: the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the surface of the intermediate structure to an anti-reflection coating material to blanket coat the anti-reflection material on both the release agent disposed on the top surface and the bottom portions of the cavities; and exposing the intermediate structure having both the release agent disposed on the top surface of the wafer and the bottom portions of the cavities void of the release agent to a process to selectively remove the release agent together with the anti-reflection coating material thereon while leaving the anti-reflection coating material on the bottom portions of the cavities.
- the method includes: providing a second wafer having a plurality of arrays for detectors, each one of the arrays being associated with a
- a thin water or solvent soluble layer (the release agent) is applied only to the exposed surface by controlled contact transfer prior to depositing an AR film or coating.
- the ARC film portions of the release layer are then easily removed when the release layer is removed in water or solvent in an ultrasonic cleaner. If the release agent is only a monolayer or so thick, the ARC adhesion is weakened by this layer, and is easily removed in an ultrasonic cleaner.
- the method removes the need for a shadow mask, polishing equipment, and capital equipment for these and any traditional alternative, such as a photoresist sprayer, UV exposure and development, and liftoff equipment. The equipment savings for high volume production could be several million dollars.
- FIGS. 1A-1E are simplified cross sectional diagrams of a process for forming an anti-reflection coating on selected portions of an optical energy transparent wafer according to the disclosure.
- an optically transparent window wafer 10 (a cap wafer), here for example, silicon, is shown.
- the inside surface of the wafer 10 is formed with a plurality of cavities 11 formed in selected portions of the inside surface, each cavity 11 having outer, peripheral sidewalls 13 extending outwardly from the inner surface, as indicated.
- the sidewalls 13 have top surfaces 17, as indicated.
- the outside surface 12 of the wafer 10 is temporarily attached to a vacuum chuck 14.
- a second structure 16, with a very flat surface, here for example, a polished granite surface plate, or another silicon wafer, is coated with a release agent 18, as shown.
- the release agent 18 is polyvinyl alcohol, or other suitable material, having a thickness of one molecular layer to many layers, up to a fraction of a millimeter thick.
- the top surface 17 of the wafer is contacted momentarily with a portion of the release agent 18 to transfer portions of the release agent 18 to the top surface 17 of the wafer while bottom portions 20 of the cavities 11 remain spaced from the release agent 18 to produce an intermediate structure 24 (FIG. IB) having a surface comprising: the release agent 18 disposed on the top surface 17 of the wafer and with the bottom portions 20 of the cavities 11 void of the release agent 18.
- the intermediate structure 24 is exposed to an anti- reflection coating material 27 to blanket coat the anti-reflection material 27 on both the release agent 18 disposed on the top surface 17 of the wafer and the bottom portions 20 of the cavities 11 to produce the structure 24', as shown in FIG. 1C.
- an anti- reflection coating material 27 to blanket coat the anti-reflection material 27 on both the release agent 18 disposed on the top surface 17 of the wafer and the bottom portions 20 of the cavities 11 to produce the structure 24', as shown in FIG. 1C.
- FIG. ID the structure 24' (FIG.
- the wafer 10 is wafer bonded to a second wafer 32 (shown in the bottom portion of FIG. ID) having plurality of bolometers 34 connected to readout circuitry in wafer 32that comprise wafer level package (WLP) detector devices 36, each one of detector devices 36 being associated with a corresponding one of the cavities 11. Each one of the detector devices 36 is aligned with the corresponding one of the cavities 11.
- WLP wafer level package
- the optically transparent wafer 10 is bonded to the second wafer 32, with each one on the cavities 11 having the anti-reflection coating 24 on the bottom portion of the cavities 11 displaced from the corresponding array 34 and a second portion of the distal ends 17 of the walls (top surface) being bonded to the second wafer 32.
- the bonded wafer pair (wafer 10 and wafer 32) as shown in FIG. IE are then singulated into individual completed WLP detector devices.
- a method for forming a coating of material on selected portions of a substrate having a plurality of cavities formed in selected portions of a surface of the substrate, each cavity having outer, peripheral sidewalls extending outwardly from the cavity floor includes: providing a structure having a release agent thereon; contacting a top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure with a surface comprising: the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the surface of the intermediate structure to the material to blanket coat the material on both the release agent disposed on the top surface of the wafer and the bottom portions of the cavities; exposing the intermediate structure having the coated release agent and the bottom portions to a process to selectively remove the release agent together with the coating material thereon from the top surface of the wafer while leaving the coating material on the bottom portions of the cavities.
- a method for forming an anti-reflection coating on selected portions of an optical energy transparent wafer having a plurality of cavities formed in selected portions of a surface of the wafer, each cavity having outer, peripheral sidewalls extending outwardly from the surface (cavity floor) includes: providing a structure having a release agent thereon; contacting top surface of the wafer with a portion of the release agent to transfer the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure with a surface comprising: the release agent disposed on the top surfaces of the wafer and with the bottom portions of the cavities void of the release agent; exposing the surface of the intermediate structure to an anti-reflection coating material to blanket coat the anti-reflection material on both the release agent disposed on the top surface of the wafer and the bottom portions of the cavities; exposing the intermediate structure having both the release agent disposed on the top surface of the wafer and the bottom portions of the cavities void of the release agent
- the method may also include: providing a second wafer having a plurality of arrays for detectors, each one of the arrays being associated with a corresponding one of the cavities; aligning each one of the arrays with the corresponding one of the cavities; and bonding the optically transparent wafer to the second wafer, with each one of the cavities having the anti-reflection coating thereon displaced from the corresponding array and a second portion of the top surfaces of the wafer being bonded to the second wafer.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Micromachines (AREA)
- Surface Treatment Of Optical Elements (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Physical Vapour Deposition (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/100,048 US9105800B2 (en) | 2013-12-09 | 2013-12-09 | Method of forming deposited patterns on a surface |
| PCT/US2014/067285 WO2015088771A1 (en) | 2013-12-09 | 2014-11-25 | Method of forming deposited patterns on a surface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP3041784A1 true EP3041784A1 (en) | 2016-07-13 |
| EP3041784B1 EP3041784B1 (en) | 2020-02-19 |
Family
ID=52302306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP14824962.6A Active EP3041784B1 (en) | 2013-12-09 | 2014-11-25 | Method of forming deposited patterns on a surface |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9105800B2 (en) |
| EP (1) | EP3041784B1 (en) |
| JP (1) | JP6532465B2 (en) |
| KR (1) | KR102047869B1 (en) |
| CN (1) | CN105612119B (en) |
| CA (1) | CA2924123C (en) |
| IL (1) | IL244513B (en) |
| WO (1) | WO2015088771A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9570321B1 (en) | 2015-10-20 | 2017-02-14 | Raytheon Company | Use of an external getter to reduce package pressure |
| FR3088319B1 (en) * | 2018-11-08 | 2020-10-30 | Ulis | HERMETIC CASE INCLUDING A GETTER, OPTOELECTRONIC COMPONENT OR MEMS DEVICE INTEGRATING SUCH A HERMETIC CASE AND ASSOCIATED MANUFACTURING PROCESS |
| CN114210970B (en) * | 2021-12-28 | 2023-09-22 | 北京建工环境修复股份有限公司 | Coated iron-carbon composite material, preparation and modification methods and sewage treatment method |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3161474B2 (en) * | 1991-06-20 | 2001-04-25 | 凸版印刷株式会社 | Phase shift mask and method of manufacturing the same |
| US6252229B1 (en) | 1998-07-10 | 2001-06-26 | Boeing North American, Inc. | Sealed-cavity microstructure and microbolometer and associated fabrication methods |
| CA2485022A1 (en) * | 2002-04-15 | 2003-10-23 | Schott Ag | Method for connecting substrates and composite element |
| FR2846906B1 (en) | 2002-11-08 | 2005-08-05 | Commissariat Energie Atomique | METHOD FOR PRODUCING A COMPONENT COMPRISING A MICRO-SEAL AND COMPONENT PRODUCED THEREBY |
| KR100885099B1 (en) * | 2003-12-15 | 2009-02-20 | 후루카와 덴키 고교 가부시키가이샤 | Wafer processing tape and its manufacturing method |
| US7381583B1 (en) | 2004-05-24 | 2008-06-03 | The United States Of America As Represented By The Secretary Of The Air Force | MEMS RF switch integrated process |
| JP2009130110A (en) | 2007-11-22 | 2009-06-11 | Sumitomo Electric Ind Ltd | Group III nitride surface emitting device and method for manufacturing the same |
| US20110014732A1 (en) * | 2009-07-20 | 2011-01-20 | Lee Je-Hsiang | Light-emitting module fabrication method |
| US8696740B2 (en) * | 2010-01-05 | 2014-04-15 | The Johns Hopkins University | Implantable pressure-actuated drug delivery systems and methods of manufacture and use |
| JP2011192868A (en) * | 2010-03-16 | 2011-09-29 | Tokyo Electron Ltd | Method of processing template, program, computer storage medium, and template processing device |
| EP2484629B1 (en) | 2011-02-03 | 2013-06-26 | Nivarox-FAR S.A. | Perforated complex micromechanical part |
| JP5929203B2 (en) * | 2012-01-10 | 2016-06-01 | 株式会社リコー | Lens-integrated substrate and optical sensor |
-
2013
- 2013-12-09 US US14/100,048 patent/US9105800B2/en active Active
-
2014
- 2014-11-25 KR KR1020167013973A patent/KR102047869B1/en active Active
- 2014-11-25 WO PCT/US2014/067285 patent/WO2015088771A1/en not_active Ceased
- 2014-11-25 JP JP2016535704A patent/JP6532465B2/en active Active
- 2014-11-25 CN CN201480055529.1A patent/CN105612119B/en not_active Expired - Fee Related
- 2014-11-25 EP EP14824962.6A patent/EP3041784B1/en active Active
- 2014-11-25 CA CA2924123A patent/CA2924123C/en active Active
-
2016
- 2016-03-09 IL IL24451316A patent/IL244513B/en active IP Right Grant
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2015088771A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR102047869B1 (en) | 2019-11-22 |
| JP2017502328A (en) | 2017-01-19 |
| CA2924123A1 (en) | 2015-06-18 |
| CN105612119B (en) | 2018-03-02 |
| US20150162479A1 (en) | 2015-06-11 |
| IL244513A0 (en) | 2016-04-21 |
| CA2924123C (en) | 2018-02-27 |
| CN105612119A (en) | 2016-05-25 |
| US9105800B2 (en) | 2015-08-11 |
| EP3041784B1 (en) | 2020-02-19 |
| JP6532465B2 (en) | 2019-06-19 |
| KR20160079028A (en) | 2016-07-05 |
| IL244513B (en) | 2019-10-31 |
| WO2015088771A1 (en) | 2015-06-18 |
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