EP2991187B1 - Mobiles endgerät mit multiport-ladungssteuerungsfunktion - Google Patents

Mobiles endgerät mit multiport-ladungssteuerungsfunktion Download PDF

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Publication number
EP2991187B1
EP2991187B1 EP13883060.9A EP13883060A EP2991187B1 EP 2991187 B1 EP2991187 B1 EP 2991187B1 EP 13883060 A EP13883060 A EP 13883060A EP 2991187 B1 EP2991187 B1 EP 2991187B1
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EP
European Patent Office
Prior art keywords
charging
resistor
cpu
transistor
usb
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EP13883060.9A
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English (en)
French (fr)
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EP2991187A4 (de
EP2991187A1 (de
Inventor
Shiqing Zhao
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Huizhou TCL Mobile Communication Co Ltd
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Huizhou TCL Mobile Communication Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H02J7/007182—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00045—Authentication, i.e. circuits for checking compatibility between one component, e.g. a battery or a battery charger, and another component, e.g. a power source

Definitions

  • the present invention relates to the field of charging technologies, and particularly to a mobile terminal with a multi-port charging control function.
  • USB universal serial bus
  • a current carried by a USB interface is designed according to a USB interface industry standard, and a nominal current (that is, charging current) is required to be 500mA, which is far from meeting the requirements for large battery capacity and a same or shorter charging time of the ever-growing mobile terminals. More and more mobile terminals require charging currents much higher than the current provided by a standard USB. Therefore, how to achieve large-current charging and stable power supply for smart terminals is worth studying and has great application value.
  • the first one is charging through a USB interface, which is only suitable for small-current charging, and the charging time will be prolonged if battery capacity of a mobile terminal is large.
  • the second one is charging by using a DC charging stand; DC charging stands on the market are non-standard, and need a special DC charging interface; the limitation to the type of the USB interface leads to an increase in the number of special accessories of the mobile terminal, thereby greatly increasing the cost, and resulting in poor user experience.
  • the third one is hybrid charging, that is, a USB interface is used for small-current charging, and a special DC charging interface is used for large-current charging; such a manner has high requirements for control over values of currents, combination of large and small currents, and compatibility of the USB interface, and has a high cost.
  • US 2008/0111522 A1 relates to a method and a system for charging an electronic device.
  • the method includes negotiating a first current supply from a first charging port.
  • the first charging port is one of a plurality of charging ports present on a current-supplying device.
  • the current-supplying device is connected to a charging device which, in turn, is connected to an electronic device, e.g., a mobile phone.
  • the electronic device can be charged by using the charging device, which acts as an interface between the current-supplying device and the electronic device.
  • Current negotiations take place between the electronic device and the current-supplying device.
  • a microcontroller of the charging device uses an extraction module to extract the first current supply from a first charging port of the current-supplying device.
  • the microcontroller can negotiate for a second current supply with the current-supply device.
  • the charging device include a laptop charger, a mobile phone charger, a rechargeable battery charger, and the like such that the charging device is a separate devices from the electronic device.
  • the method includes negotiating a second current supply from a second charging port, the second charging port is one of the plurality of charging ports.
  • the method includes combining the first current supply and the second current supply to provide a combined current supply for charging the battery of the electronic device.
  • US 2010/0090644 A1 relates to an apparatus includes a connector, for providing a physical connection to a USB device, a detection circuit, operable to detect attachment of a USB device; and a charging circuit, for charging a battery of a portable device using current drawn from a USB device, the charging circuit being operable, if it is detected that a USB device is attached, to generate a startup request signal.
  • the apparatus has a charging mode in which power is provided by the charging circuit to the battery, and a USB connection mode for providing a USB connection.
  • the apparatus also includes a control unit, operable in response to the start-up request signal to determine whether power supplied by the battery meets a predetermined criterion.
  • the control unit is also operable, if it is determined that the predetermined criterion is not met, to control the apparatus to be in the charging mode and prevent the apparatus from entering the USB connection mode and operable, if it is determined that predetermined criterion is met, to control the apparatus to enter the USB connection mode.
  • an objective of the present invention is to provide a mobile terminal with a multi-port charging control function, so as to solve the problems of long charging time of a battery and poor compatibility of a USB interface in the prior art.
  • a mobile terminal including: a battery; at least a first USB interface and a second USB interface; a central processing unit (CPU); a charging management chip; and a USB charging management module, where the USB charging management module is configured to output a corresponding detection voltage according to charger connection conditions of the USB interface, configured to turn on or off a charging channel of the corresponding USB interface according to an on/off command output by the CPU to generate a respective charging current, and configured to: when the charging channel is turned on, control a value of a charging current according to an adjustment signal sent by the CPU, combine the charging current, and transmit the combined charging current to the charging management chip; the USB charging management module comprising at least a first charger detection module and a second charger detection module configured to detect whether a charger is connected to a respective USB interface, and output the detection voltage to the CPU; the USB charging management module comprising at least a first charging current control module and a second charging current control module, configured to turn on or off the respective
  • the number of the charger detection modules, the number of the charging current control modules, and the number of the data processing modules are the same as the number of the USB interfaces.
  • the charger detection modules, the charging current control modules and the data processing modules are all connected to a respective USB interface and the CPU, and the charging current control modules are connected to the charging management chip through the current combiner.
  • the first charger detection module includes a first resistor, a second resistor, a third resistor and a first transistor; the first charging current control module includes a fourth resistor, a fifth resistor, a second transistor and a first capacitor; and the first data processing module includes a first common-mode suppression coil, a first TVS tube, a second TVS tube and a third TVS tube.
  • the base of the first transistor is connected to a power source end of the first USB interface and the emitter of the second transistor through the first resistor, the base of the first transistor is further grounded through the second resistor, the collector of the first transistor is connected to the CPU and is further connected to a power source end through the third resistor, and the emitter of the first transistor is grounded; and the emitter of the second transistor is connected to the power source end of the first USB interface, the emitter of the second transistor is grounded through the first capacitor, and the base of the second transistor is connected to the CPU through the fourth resistor.
  • a first end of the first common-mode suppression coil is connected to a positive data line end of the first USB interface and the anode of the third TVS tube
  • a second end of the first common-mode suppression coil is connected to the CPU
  • a third end of the first common-mode suppression coil is connected to a negative data line end of the first USB interface and the anode of the second TVS tube
  • a fourth end of the first common-mode suppression coil is connected to the CPU
  • the anode of the first TVS tube is connected to an identification end of the first USB interface and the CPU
  • the cathode of the first TVS tube, the cathode of the second TVS tube and the cathode of the third TVS tube are all grounded.
  • the first transistor is an NPN transistor.
  • the second charger detection module includes a sixth resistor, a seventh resistor, an eighth resistor and a third transistor;
  • the second charging current control module includes a ninth resistor, a tenth resistor, a fourth transistor and a second capacitor;
  • the second data processing module includes a second common-mode suppression coil, a fourth TVS tube, a fifth TVS tube and a sixth TVS tube.
  • the base of the third transistor is connected to a power source end of the second USB interface and the emitter of the fourth transistor through the sixth resistor, the base of the third transistor is further grounded through the seventh resistor, the collector of the third transistor is connected to the CPU and is further connected to a power source end through the eighth resistor, and the emitter of the third transistor is grounded; and the emitter of the fourth transistor is grounded through the second capacitor, and the base of the fourth transistor is connected to the CPU through the ninth resistor.
  • a first end of the second common-mode suppression coil is connected to a positive data line end of the second USB interface and the anode of the sixth TVS tube
  • a second end of the second common-mode suppression coil is connected to the CPU
  • a third end of the second common-mode suppression coil is connected to a negative data line end of the first USB interface and the anode of the fifth TVS tube
  • a fourth end of the second common-mode suppression coil is connected to the CPU
  • the anode of the fourth TVS tube is connected to an identification end of the second USB interface and the CPU
  • the cathode of the fourth TVS tube, the cathode of the fifth TVS tube and the cathode of the sixth TVS tube are all grounded.
  • the second transistor is a PNP transistor.
  • the current combiner includes an eleventh resistor; one end of the fifth resistor is connected to the CPU and the collector of the second transistor, and the other end of the fifth resistor is connected to the CPU and one end of the eleventh resistor; and one end of the tenth resistor is connected to the CPU and the collector of the fourth transistor, and the other end of the tenth resistor is connected to the CPU and one end of the eleventh resistor.
  • a USB charging management module detects charger connection conditions of a USB interface to output a corresponding detection voltage to a CPU so that the CPU identifies a charger connection state of the USB interface; the CPU outputs a corresponding on/off command to turn on/off a charging channel of the corresponding USB interface, and when the charging channel is turned on, controls a value of a charging current, combines the charging current, and transmits the combined charging current to a charging management chip to charge a battery.
  • a requirement for large-current charging is met by using multiple USB interfaces in parallel for charging, which greatly reduces charging time of the battery, is easy to operate, and has a low cost.
  • An existing mobile terminal is provided with multiple USB interfaces, and when a USB charger is connected to a USB interface, a VBUS end (power source end) of the USB interface generates a voltage of +5V, where a nominal current of 500mA.
  • a DM end of the USB interface is a positive data line end, a DP end is a negative data line end, an ID end is an identification end, and a GND end is a ground end.
  • the mobile terminal with a multi-port charging control function makes full use of the existing multiple USB interfaces for parallel charging, that is, during charging, the USB interfaces are independent of each other and are comprehensively managed by the CPU.
  • the CPU monitors a charging state of each USB interface separately, including USB charger connection detection, on/off of the charging channel, control over a value of a charging current, combination of multiple charging currents and the like.
  • the multiple USB interfaces are equivalent to a building-block charging interface, and the number of chargers connected to the USB interfaces can be arbitrarily increased or decreased.
  • FIG.1 is a structural block diagram of a mobile terminal with a multi-port charging control function.
  • the mobile terminal includes a USB interface 10, a USB charging management module 20, a CPU 30, a charging management chip 40 and a battery 50.
  • the battery 50 is connected to the USB charging management module 20 through the charging management chip 40, and both the USB interface 10 and the CPU 30 are connected to the USB charging management module 20.
  • the USB charging management module 20 outputs a corresponding detection voltage to the CPU 30 according to charger connection conditions of the USB interface.
  • the CPU 30 identifies the charger connection conditions of the USB interface according to the detection voltage and outputs a corresponding on/off command to the USB charging management module 20.
  • the USB charging management module 20 turns on/off a charging channel of the corresponding USB interface according to the on/off command, and when the charging channel is turned on, controls a value of a charging current according to an adjustment signal, combines the charging current, and then transmits the combined charging current to the charging management chip 40 to charge the battery 50.
  • the USB charging management module 20 includes a charger detection module 210, a charging current control module 220, a data processing module 230 and a current combiner 240.
  • the charger detection module 210, the charging current control module 220 and the data processing module 230 are all connected to the USB interface 10 and the CPU 30, and the charging current control module 220 is connected to the charging management chip 40 through the current combiner 240.
  • the charger detection module 210 detects whether a charger is connected to the USB interface 10 of the mobile terminal, and outputs the corresponding detection voltage to the CPU 30.
  • the charging current control module 220 turns on/off the charging channel of the corresponding USB interface 10 according to the on/off command transmitted by the CPU 30; when the charging channel is turned on, the CPU 30 acquires the value of the charging current and outputs a corresponding adjustment signal to the USB charging management module to adjust the value of the charging current.
  • the current combiner 240 combines the charging current output by the charging current control module 220 and then transmits the charging current to the charging management chip 40.
  • the data processing module 230 performs anti-interference and anti-static processing on USB data transmitted by the CPU.
  • FIG.2 is a circuit diagram of a USB charging management module in a mobile terminal with a multi-port charging control function.
  • the charger detection module 210 includes a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1; the base of the first transistor Q1 is connected to a VUSB end of the USB interface 10 through the first resistor R1, the base of the first transistor Q1 is further grounded through the second resistor R2, the collector of the first transistor Q1 is connected to the CPU 30 and is further connected to a power source end VCC through the third resistor R3, and the emitter of the first transistor Q1 is grounded.
  • the VUSB end is suspended, and a DC_DET signal output by the collector of the first transistor Q1 is pulled up to a high level by the third resistor R3.
  • the first transistor Q1 is an NPN transistor.
  • the CPU 30 When detecting that the DC_DET signal is at a high level, the CPU 30 identifies that no charger is connected to the USB interface; it is unnecessary to turn on the charging channel corresponding to the USB interface, and the CPU30 outputs an off command to the charging current control module 220.
  • the VUSB end When a charger is connected to the USB interface, the VUSB end outputs a nominal voltage of 5V to turn on the first transistor Q1, and the DC_DET signal output by the collector is pulled down from a high level to a low level.
  • the CPU 30 When detecting that the DC_DET signal is at a low level, the CPU 30 identifies that a charger is connected to the USB interface; at this time, it is necessary to turn on the charging channel corresponding to the USB interface for charging, and the CPU30 outputs an on command to the charging current control module 220.
  • the first resistor R1 is a current-limiting resistor
  • the second resistor R2 is a pull-down protection resistor, and the two are combined to protect the first transistor Q1 from being damaged by a large current.
  • the charging current control module 220 includes a fourth resistor R4, a fifth resistor R5, a second transistor Q2 and a first capacitor C1; the base of the second transistor Q2 is connected to the CPU 30 through the fourth resistor R4, and the emitter of the second transistor Q2 is connected to the VUSB end of the USB interface 10 and is further grounded through the first capacitor C1; one end of the fifth resistor R5 is connected to the CPU 30 and the collector of the second transistor Q2, and the other end of the fifth resistor R5 is connected to the CPU 30 and the current combiner 240.
  • the second transistor Q2 is a high-power PNP transistor.
  • the CPU 30 When identifying that a charger is connected to the USB interface 10, the CPU 30 outputs a low-level CURRENT_CTL signal which is input to the base of the second transistor Q2 through the fourth resistor R4, to turn on the second transistor Q2, and a current from the VUSB end of the USB interface 10 flows through the fifth resistor R5.
  • one end of the fifth resistor R5 outputs a CURRENT_P signal (that is, one charging signal, expressed in the form of a voltage value) to the CPU 30, and the other end of the fifth resistor R5 outputs a CURRENT_N signal (that is, another charging signal, expressed in the form of a voltage value) to the CPU 30.
  • a resistance value of the fifth resistor R5 is a known fixed value, and the CPU 30 can calculate the value of the charging current according to a voltage difference between the CURRENT_P signal and the CURRENT_N signal and the resistance value of the fifth resistor R5.
  • a charging current generated is 500mA, which is the nominal current, and in the subsequent charging process, the CPU 30 may output CURRENT_P signals at different levels according to the battery level, to adjust the turn-on degree of the second transistor Q2, thereby adjusting the value of the charging current, which prevents the battery from being damaged by an excessively large charging current when the battery is about to be fully charged, and can further ensure stability of the charging process.
  • the first capacitor C1 is used for energy storage and denoising during charging, to ensure stability of the charging current.
  • the data processing module 230 includes a common-mode suppression coil FB for anti-interference, and a first TVS tube T1, a second TVS tube T2 and a third TVS tube T3 for anti-static processing; a first end 1 of the common-mode suppression coil FB is connected to a DM end of the USB interface 10 and the anode of the third TVS tube T3; a second end 2 of the common-mode suppression coil FB is connected to the CPU 30, and is configured to transmit a USB_DM signal (positive data); a third end 3 of the common-mode suppression coil FB is connected to a DP end of the USB interface 10 and the anode of the second TVS tube T2; a fourth end 4 of the common-mode suppression coil FB is connected to the CPU 30, and is configured to transmit a USB_DP signal (negative data); the anode of the first TVS tube T1 is connected to an ID end of the USB interface 10 and the CPU 30, and is configured to transmit a USB_ID signal (identity authentication information); and the cath
  • the current combiner 240 includes a current combining resistor R11, one end of the current combining resistor R11 is connected to the other end of the fifth resistor R5 of the charging current control module 220, and the other end of the current combining resistor R11 is connected to the charging management chip 40. After flowing through the current combining resistor R11, charging currents output by the fifth resistor R5 form a total charging current POWER_SOURCE, which is transmitted to the charging management chip 40 for processing, and then used to charge the battery.
  • One USB interface 10 is adaptive to one charger detection module 210, one charging current control module 220 and one data processing module 230.
  • the current combiner 240 combines charging currents generated by multiple charging current control modules 220 to form an ultimate large total charging current, and then the battery 50 is charged by the charging management chip 40.
  • FIG.3 is a structural block diagram of a first preferred embodiment of a mobile terminal with a multi-port charging control function according to the present invention.
  • the number of USB interfaces is n (n is a positive integer), which are a first USB interface 10_1, a second USB interface 10_2..., and an n th USB interface 10_n, respectively.
  • the number of charger detection modules is n correspondingly, which are a first charger detection module 210_1, a second charger detection module 210_2..., and an n th charger detection module 210_n, respectively.
  • the number of charging current control modules is n correspondingly, which are a first charging current control module 220_1, a second charging current control module 220_2..., and an n th charging current control module 220_n, respectively.
  • the number of data processing module is n correspondingly, which are a first data processing module 230_1, a second data processing module 230_2..., and an n th data processing module 230_n, respectively.
  • the first charger detection module 210_1, the first charging current control module 220_1 and the first data processing module 230_1 are connected to the first USB interface 10_1 and the CPU 30.
  • the second charger detection module 210_2, the second charging current control module 220_2 and the second data processing module 230_2 are connected to the second USB interface 10_2 and the CPU 30.
  • the rest may be deduced by analogy, that is, the n th charger detection module 210_n, the n th charging current control module 220_n and the n th data processing module 230_n are connected to the n th USB interface 10_n and the CPU 30.
  • the first charging current control module 220_1, the second charging current control module 220_2..., and the n th charging current control module 220_n are connected to the current combiner 240.
  • circuit structures of the first USB interface 10_1, the second USB interface 10_2..., and the n th USB interface 10_n are the same as the circuit structure of the USB interface 10 in the implementation shown in FIG.2 .
  • Circuit structures of the first charger detection module 210_1, the second charger detection module 210_2..., and the n th charger detection module 210_n are the same as the circuit structure of the charger detection module 210 in the implementation shown in FIG.2 .
  • Circuit structures of the first charging current control module 220_1, the second charging current control module 220_2..., and the n th charging current control module 220_n are the same as the circuit structure of the charging current control module 220 in the implementation shown in FIG.2 .
  • Circuit structures of the first data processing module 230_1, the second data processing module 230_2..., and the n th data processing module 230_n are the same as the circuit structure of the data processing module 230 in the implementation shown in FIG.2 .
  • electronic devices are named differently to distinguish one from another, but connection relationships and working principles thereof are the same.
  • FIG.4 is a circuit diagram of a second preferred embodiment of a mobile terminal with a multi-port charging control function according to the present invention.
  • the number of USB interfaces is two, which are a first USB interface 10_1 and a second USB interface 10_2, respectively;
  • the charging management module 20 includes a first charger detection module 210_1, a second charger detection module 210_2, a first charging current management module 220_1, a second charging current management module 220_2, a first data processing module 230_1, a second data processing module 230_2 and a current combiner 240.
  • the first charger detection module 210_1, the first charging current control module 220_1 and the first data processing module 230_1 are connected to the first USB interface 10_1 and the CPU 30;
  • the second charger detection module 210_2, the second charging current control module 220_2 and the second data processing module 230_2 are connected to the second USB interface 10_2 and the CPU 30;
  • the first charging current control module 220_1 and the second charging current control module 220_2 are connected to the current combiner 240.
  • Circuitry of the first charger detection module 210_1 is the same as that of the charger detection module 210 in the USB charging management module in the implementation shown in FIG.2 , and includes a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1; circuitry of the first charging current control module 220_1 is the same as that of the charging current control module 220 in the USB charging management module in the implementation shown in FIG.2 , and includes a fourth resistor R4, a fifth resistor R5, a second transistor Q2 and a first capacitor C1; circuitry of the first data processing module 230_1 is the same as that of the data processing module 230 in the USB charging management module in the implementation shown in FIG.2 , and includes a first common-mode suppression coil FBI, a first TVS tube T1, a second TVS tube T2 and a third TVS tube T3; the second charger detection module 210_2 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and
  • the circuit structure of the first charger detection module 210_1 is the same as that of the second charger detection module 210_2; names of the electronic devices are modified correspondingly to distinguish one from another, but connection relationships between the electronic devices and the working principles thereof are the same.
  • the first resistor R1 and the sixth resistor R6 have different names, which are intended to distinguish electronic devices in two charger detection modules, but in fact, the first resistor R1 and the sixth resistor R6 are equivalent, both of which represent the first resistor R1 in the charger detection module 210 shown in FIG.2 .
  • Situations of other modules can be inferred in the same way.
  • the base of the first transistor Q1 is connected to a VUSB end of the first USB interface 10_1 and the emitter of the second transistor Q2 through the first resistor, the base of the first transistor Q1 is further grounded through the second resistor R2, the collector of the first transistor Q1 is connected to the CPU 30 and is further connected to a power source end VCC through the third resistor R3, and the emitter of the first transistor Q1 is grounded.
  • the first transistor Q1 is an NPN transistor, whose collector outputs a DC_DET1 signal to the CPU 30.
  • the emitter of the second transistor Q2 is grounded through the first capacitor C1, and the base of the second transistor Q2 is connected to the CPU 30 through the fourth resistor R4; one end of the fifth resistor R5 is connected to the CPU 30 and the collector of the second transistor Q2, and the other end of the fifth resistor R5 is connected to the CPU 30 and one end of the eleventh resistor R11.
  • the second transistor Q2 is a high-power PNP transistor. One end of the fifth resistor R5 outputs a CURRENT1_P signal to the CPU 30, and the other end of the fifth resistor R5 outputs a CURRENT1_N signal to the CPU 30.
  • a first end 1 of the first common-mode suppression coil FB1 is connected to a DM end of the first USB interface 10_1 and the anode of the third TVS tube T3, a second end 2 of the first common-mode suppression coil FB 1 is connected to the CPU 30, a third end 3 of the first common-mode suppression coil FB1 is connected to a DP end of the first USB interface 10_1 and the anode of the second TVS tube T2, and a fourth end 4 of the first common-mode suppression coil FB1 is connected to the CPU 30; the anode of the first TVS tube T1 is connected to an ID end of the first USB interface 10_1 and the CPU 30; and the cathode of the first TVS tube T1, the cathode of the second TVS tube T2 and the cathode of the third TVS tube T3 are all grounded.
  • a USB1_DM signal is transmitted between the second end 2 of the first common-mode suppression coil FB1 and the CPU 30, a USB1_DP signal is transmitted between the fourth end 4 of the first common-mode suppression coil FB1 and the CPU 30, and a USB1_ID is transmitted between the ID end of the first USB interface 10_1 and the CPU 30.
  • the base of the third transistor Q3 is connected to a VUSB end of the second USB interface 10_2 and the emitter of the fourth transistor Q4 through the sixth resistor R6, the base of the third transistor Q3 is further grounded through the seventh resistor R7, the collector of the third transistor Q3 is connected to the CPU 30 and is further connected to a power source end VCC through the eighth resistor R8, and the emitter of the third transistor Q3 is grounded.
  • the third transistor Q3 is an NPN transistor, whose collector outputs a DC_DET2 signal to the CPU 30.
  • the emitter of the fourth transistor Q4 is grounded through the second capacitor C2, and the base of the fourth transistor Q4 is connected to the CPU 30 through the ninth resistor R9; one end of the tenth resistor R10 is connected to the CPU 30 and the collector of the fourth transistor Q4, and the other end of the tenth resistor R10 is connected to the CPU 30 and one end of the eleventh resistor R11.
  • the fourth transistor Q4 is a high-power PNP transistor.
  • One end of the tenth resistor R10 outputs a CURRENT2_P signal to the CPU 30, and the other end of the tenth resistor RIO outputs a CURRENT2_N signal to the CPU 30.
  • a first end 1 of the second common-mode suppression coil FB2 is connected to a DM end of the second USB interface 10_2 and the anode of the sixth TVS tube T6, a second end 2 of the second common-mode suppression coil FB2 is connected to the CPU 30, a third end 3 of the second common-mode suppression coil FB2 is connected to a DP end of the second USB interface 10_2 and the anode of the fifth TVS tube T5, and a fourth end 4 of the second common-mode suppression coil FB2 is connected to the CPU 30; the anode of the fourth TVS tube T4 is connected to an ID end of the second USB interface 10_2 and the CPU 30; and the cathode of the fourth TVS tube T4, the cathode of the fifth TVS tube T5 and the cathode of the sixth TVS tube T6 are all grounded.
  • a USB2_DM signal is transmitted between the second end 2 of the second common-mode suppression coil FB2 and the CPU 30, a USB2_DP signal is transmitted between the fourth end 4 of the second common-mode suppression coil FB2 and the CPU 30, and a USB2_ID signal is transmitted between the ID end of the second USB interface 10_2 and the CPU 30.
  • the VUSB end of the first USB interface 10_1 and the VUSB end of the second USB interface 10_2 both output a voltage of 5V, to turn on the first transistor Q1 and the third transistor Q3 separately, and change the DC_DET1 signal and the DC_DET2 to be low-level signals, which are transmitted to the CPU 30.
  • the CPU 30 identifies that chargers are separately connected to the first USB interface 10_1 and the second USB interface 10_2, and at this time, the CPU 30 outputs a low-level CURRENT1_CTL which is input to the base of the second transistor Q2 through the fourth resistor R4, and a low-level CURRENT2_CTL which is input to the base of the fourth transistor Q4 through the ninth resistor R9.
  • the second transistor Q2 and the fourth transistor Q4 are both turned on; the VUSB end of the first USB interface 10_1 outputs a current flowing through the fifth resistor R5, thereby generating a charging current 1 flowing to one end of the current combining resistor R11; meanwhile, the VUSB end of the second USB interface 10_2 also outputs a current flowing through the tenth resistor R10, thereby generating a charging current 2 flowing to one end of the current combining resistor R11.
  • the current combining resistor R11 combines the charging current 1 and the charging current 2 which then flow out from the other end of the current combining resistor R11, to form a total charging current POWER_SOURCE to the charging management chip 40 to charge the battery 50.
  • the CPU 30 calculates the value of the charging current 1 according to a voltage difference between the CURRENT1_P signal output by one end of the fifth resistor R5 and the CURRENT1_N signal output by the other end of the fifth resistor R5, and a resistance value of the fifth resistor R5; likewise, the CPU 30 calculates the value of the charging current 2 according to a voltage difference between the CURRENT2_P signal output by one end of the tenth resistor R10 and the CURRENT2_N signal output by the other end of the tenth resistor R10 and a resistance value of the tenth resistor R10.
  • the charging current 1 and the charging current 2 are generally maintained at 500mA, in this way, the charging current 1 and the charging current 2 form a total charging current of 1000mA after being combined through the current combining resistor R11, so as to charge the battery 50, and charging time of a large-capacity battery is maintained or shortened by increasing a charging current.
  • the CPU 30 can further output a CURRENT1_CTL signal and a CURRENT2_CTL signal with corresponding level values to adjust the values of the charging current 1 and the charging current 2.
  • the CPU 30 can arbitrarily adjust a value of a charging current provided by any one or more USB interfaces.
  • each USB interface is independent, and can provide a nominal current of 500mA.
  • a charger can provide a nominal current when connected to any USB interface.
  • the total charging current is the sum of nominal currents of multiple USB interfaces to which chargers are connected, equivalent to parallel charging of the multiple USB interfaces; in this way, regardless of a type of a USB interface, charging can be achieved as long as a charger is connected to the USB interface, and large-current charging can be performed when multiple chargers are connected to USB interfaces, thereby improving compatibility of the USB interfaces.
  • the charger detection module detects whether a charger is connected, and outputs a detection result (that is, a low-level DC_DET signal) to notify the CPU when the charger is connected; the CPU identifies that the charger is connected to the USB interface, outputs an on command (that is, a low-level CURRENT_CTL signal) to turn on a charging channel in the charging current control module to generate a charging current; when chargers are connected to multiple USB interfaces, charging channels in multiple corresponding charging current control modules are turned on to generate multiple charging currents, and the charging currents enter the current combiner, and are combined to form a total charging current, which is transmitted to the charging management chip to charge the battery.
  • a requirement for large-current charging is achieved by using multiple USB interfaces in parallel for charging, which significantly reduces charging time of the battery, is easy to operate, and has a low cost.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Claims (12)

  1. Mobiles Endgerät, umfassend:
    - eine Batterie (50);
    - mindestens eine erste USB-Schnittstelle (10_1) und eine zweite USB-Schnittstelle (10_2);
    - eine Prozessoreinheit (30);
    - einen Ladeverwaltungschip (40); und
    - ein USB-Ladeverwaltungsmodul (20);
    - wobei das USB-Ladeverwaltungsmodul konfiguriert ist zum Ausgeben einer entsprechenden Erkennungsspannung gemäß den Ladegerätverbindungsbedingungen der USB-Schnittstelle, konfiguriert ist zum Ein- oder Ausschalten eines Ladekanals der entsprechenden USB-Schnittstelle gemäß einem Ein/Aus-Befehl, der von der Prozessoreinheit ausgegeben wird, um einen entsprechenden Ladestrom zu erzeugen, und konfiguriert ist, wenn der Ladekanal eingeschaltet ist, zum Steuern eines Werts eines Ladestroms gemäß einem Einstellsignal, das von der Prozessoreinheit gesendet wird, zum Kombinieren der Ladeströme und zum Übertragen der Ladeströme an den Ladeverwaltungschip;
    - wobei das USB-Ladeverwaltungsmodul (20) mindestens ein erstes Ladegeräteerkennungsmodul (210_1) und ein zweites Ladegeräteerkennungsmodul (210_2) umfasst, die konfiguriert sind zum Erkennen, ob ein Ladegerät an eine jeweilige USB-Schnittstelle (10_1, 10_2) angeschlossen ist, und zum Ausgeben der Erkennungsspannung an die Prozessoreinheit (30);
    - wobei das USB-Ladeverwaltungsmodul (20) mindestens ein erstes Ladestromsteuermodul (220_1) und ein zweites Ladestromsteuermodul (220_2) umfasst, die konfiguriert sind zum Ein- oder Ausschalten des jeweiligen Ladekanals gemäß dem Ein/Aus-Befehl, und die konfiguriert sind zum Steuern eines Werts des Ladestroms gemäß dem Einstellsignal;
    - wobei das USB-Ladeverwaltungsmodul (20) mindestens ein erstes Datenverarbeitungsmodul (230_1) und ein zweites Datenverarbeitungsmodul (230_2) umfasst, die konfiguriert sind zum Ausführen einer Antiinterferenz- und einer Antistatik-Verarbeitung an den USB-Daten, die von der Prozessoreinheit übertragen werden; und
    - wobei das USB-Ladeverwaltungsmodul (20) eine Stromkombiniervorrichtung (240) umfasst, das konfiguriert ist zum Kombinieren der Ladeströme und zum Übertragen der Ladeströme an den Ladeverwaltungschip (40);
    - wobei die Prozessoreinheit konfiguriert ist zum Identifizieren der Ladegerätverbindungsbedingungen der USB-Schnittstellen gemäß der Erkennungsspannung und zum Ausgeben des entsprechenden Ein/Aus-Befehls, und konfiguriert ist zum Erlangen des Werts der Ladeströme und zum Ausgeben des Einstellsignals an das USB-Ladeverwaltungsmodul;
    - wobei der Ladeverwaltungschip konfiguriert ist zum Übertragen des Ladestroms, der von dem USB-Ladeverwaltungsmodul an die Batterie ausgegeben wird, um die Batterie zu laden; und
    - wobei die Batterie durch den Ladeverwaltungschip mit dem USB-Ladeverwaltungsmodul verbunden ist, und sowohl die USB-Schnittstellen (10_1, 10_2) als auch die Prozessoreinheit mit dem USB-Ladeverwaltungsmodul verbunden sind;
    wobei
    - das erste Ladegeräteerkennungsmodul, das erste Ladestromsteuermodul und das erste Datenverarbeitungsmodul mit der ersten USB-Schnittstelle und der Prozessoreinheit verbunden sind;
    - das zweite Ladegeräteerkennungsmodul, das zweite Ladestromsteuermodul und das zweite Datenverarbeitungsmodul mit der zweiten USB-Schnittstelle und der Prozessoreinheit verbunden sind; und
    - das erste Ladestromsteuermodul und das zweite Ladestromsteuermodul mit der Stromkombiniervorrichtung verbunden sind.
  2. Mobilfunkendgerät nach Anspruch 1, wobei eine Anzahl von Ladegeräteerkennungsmodulen (210; 210_1, 210_2, 210_n), eine Anzahl von Ladestromsteuermodulen (220; 220_1, 220_2, 220_n) und eine Anzahl von Datenverarbeitungsmodulen (230; 230_1, 230_2, 230_n) gleich einer Anzahl von USB-Schnittstellen (10_1, 10_2) sind.
  3. Mobilfunkendgerät nach einem der vorhergehenden Ansprüche, wobei die Ladegeräteerkennungsmodule, die Ladestromsteuermodule und die Datenverarbeitungsmodule alle mit der jeweiligen USB-Schnittstelle und der Prozessoreinheit verbunden sind und wobei die Ladestromsteuermodule über die Stromkombiniervorrichtung mit dem Ladeverwaltungschip verbunden sind.
  4. Mobilfunkendgerät nach einem der vorhergehenden Ansprüche, wobei das erste Ladegeräteerkennungsmodul einen ersten Widerstand (R1), einen zweiten Widerstand (R2), einen dritten Widerstand (R3) und einen ersten Transistor (Q1) umfasst;
    wobei das erste Ladestromsteuermodul einen vierten Widerstand (R4), einen fünften Widerstand (R5), einen zweiten Transistor (Q2) und einen ersten Kondensator (Cl) umfasst; und
    wobei das erste Datenverarbeitungsmodul eine erste Common-Mode-Entstördrossel (FB1), eine erste Transientenspannungsentstör-, TVS-, Röhre (T1),
    eine zweite TVS-Röhre (T2) und eine dritte TVS-Röhre (T3) umfasst.
  5. Mobilfunkendgerät nach Anspruch 4, wobei die Basis des ersten Transistors mit einem Stromversorgungsquellenende (VUSB) der ersten USB-Schnittstelle und durch den ersten Widerstand mit dem Emitter des zweiten Transistors verbunden ist,
    wobei die Basis des ersten Transistors außerdem durch den zweiten Widerstand geerdet ist, wobei der Kollektor des ersten Transistors mit der Prozessoreinheit verbunden ist und außerdem durch den dritten Widerstand mit einem Stromversorgungsquellenende (VCC) verbunden ist, und wobei der Emitter des ersten Transistors geerdet ist; und
    wobei der Emitter des zweiten Transistors mit dem Stromversorgungsquellenende der ersten USB-Schnittstelle verbunden ist, wobei der Emitter des zweiten Transistors durch den ersten Kondensator geerdet ist, und wobei die Basis des zweiten Transistors durch den vierten Widerstand mit der Prozessoreinheit verbunden ist.
  6. Mobilfunkendgerät nach einem der Ansprüche 4 oder 5, wobei ein erstes Ende (1) der ersten Common-Mode-Entstördrossel mit einem positiven Datenleitungsende (DM) der ersten USB-Schnittstelle und der Anode der dritten TVS-Röhre verbunden ist, wobei ein zweites Ende (2) der ersten Common-Mode-Entstördrossel mit der Prozessoreinheit verbunden ist, wobei ein drittes Ende (3) der ersten Common-Mode-Entstördrossel mit einem negativen Datenleitungsende (DP) der ersten USB-Schnittstelle und der Anode der zweiten TVS-Röhre verbunden ist, und wobei ein viertes Ende der ersten Common-Mode-Entstördrossel mit der Prozessoreinheit verbunden ist; und
    wobei die Anode der ersten TVS-Röhre mit einem Identifizierungsende (ID) der ersten USB-Schnittstelle und der Prozessoreinheit verbunden ist; wobei die Kathode der ersten TVS-Röhre, die Kathode der zweiten TVS-Röhre und die Kathode der dritten TVS-Röhre alle geerdet sind.
  7. Mobilfunkendgerät nach einem der Ansprüche 4 bis 6, wobei der erste Transistor ein npn-Transistor ist.
  8. Mobilfunkendgerät nach einem der vorhergehenden Ansprüche, wobei das zweite Ladegeräteerkennungsmodul einen sechsten Widerstand (R6), einen siebten Widerstand (R7), einen achten Widerstand (R8) und einen dritten Transistor (Q3) umfasst;
    wobei das zweite Ladestromsteuermodul einen neunten Widerstand (R9), einen zehnten Widerstand (R10), einen vierten Transistor (Q4) und einen zweiten Kondensator (C2) umfasst; und
    wobei das zweite Datenverarbeitungsmodul eine zweite Common-Mode-Entstördrossel (FB2), eine vierte TVS-Röhre (T4), eine fünfte TVS-Röhre (T5) und eine sechste TVS-Röhre (T6) umfasst.
  9. Mobilfunkendgerät nach Anspruch 8, wobei die Basis des dritten Transistors mit einem
    Stromversorgungsquellenende der zweiten USB-Schnittstelle und durch den sechsten Widerstand mit dem Emitter des vierten Transistors verbunden ist, wobei die Basis des dritten Transistors außerdem durch den siebten Widerstand geerdet ist,
    wobei der Kollektor des dritten Transistors mit der Prozessoreinheit verbunden ist und außerdem durch den achten Widerstand mit einem Stromversorgungsquellenende verbunden ist, und wobei der Emitter des dritten Transistors geerdet ist; und
    wobei der Emitter des vierten Transistors durch den zweiten Kondensator geerdet ist, und wobei die Basis des vierten Transistors durch den neunten Widerstand mit der Prozessoreinheit verbunden ist.
  10. Mobilfunkendgerät nach einem der Ansprüche 8 oder 9, wobei ein erstes Ende der zweiten Common-Mode-Entstördrossel mit einem positiven Datenleitungsende der zweiten USB-Schnittstelle und der Anode der sechsten TVS-Röhre verbunden ist, wobei ein zweites Ende der zweiten Common-Mode-Entstördrossel mit der Prozessoreinheit verbunden ist, wobei ein drittes Ende der zweiten Common-Mode-Entstördrossel mit einem negativen Datenleitungsende der ersten USB-Schnittstelle und der Anode der fünften TVS-Röhre verbunden ist, und wobei ein viertes Ende der zweiten Common-Mode-Entstördrossel mit der Prozessoreinheit verbunden ist; und
    wobei die Anode der vierten TVS-Röhre mit einem Identifizierungsende der zweiten USB-Schnittstelle und der Prozessoreinheit verbunden ist; und
    wobei die Kathode der vierten TVS-Röhre, die Kathode der fünften TVS-Röhre und die Kathode der sechsten TVS-Röhre alle geerdet sind.
  11. Mobilfunkendgerät nach einem der Ansprüche 8 bis 10, wobei der zweite Transistor ein pnp-Transistor ist.
  12. Mobilfunkendgerät nach einem der vorhergehenden Ansprüche, wobei die Stromkombiniervorrichtung einen elften Widerstand (R11) umfasst;
    wobei ein Ende des fünften Widerstands mit der Prozessoreinheit und dem Kollektor des zweiten Transistors verbunden ist, und wobei das andere Ende des fünften Widerstands mit der Prozessoreinheit und einem Ende des elften Widerstands verbunden ist; und
    wobei ein Ende des zehnten Widerstands mit der Prozessoreinheit und dem Kollektor des vierten Transistors verbunden ist, und wobei das andere Ende des zehnten Widerstands mit der Prozessoreinheit und einem Ende des elften Widerstands verbunden ist.
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US9960617B2 (en) 2018-05-01
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EP2991187A4 (de) 2016-09-21
EP2991187A1 (de) 2016-03-02

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