EP2984572A1

EP2984572A1 - Malware-proof data processing system

Info

Publication number: EP2984572A1
Application number: EP14715865.3A
Authority: EP
Inventors: Friedhelm Becker
Original assignee: Individual
Current assignee: Individual
Priority date: 2013-04-09
Filing date: 2014-03-27
Publication date: 2016-02-17
Also published as: DE102013005971B3; WO2014166753A1; US20160070916A1; US9881169B2

Abstract

The invention relates to a data processing system, wherein there is a strict separation of processor tasks and data categories, wherein processor tasks are separated into software loading and initialization (loading processor (8)) and file editing (main processor (1)) and data categories are separated into address data (12), instructions (11), function-internal data (13), target data of the main processor (14), and target data of the loading processor (15). Thus, there is protection against malware regardless of the transfer medium or the type of malware, including against future malware, and without a loss of performance of the computer system.

Description

Malware secure data processing system

The present invention relates to a data processing system having the features of the preamble of claim 1.

Electronic data processing systems are complex structures for solving data processing tasks. They are composed of subsystems whose interaction enables the task to be fulfilled. Important subsystems are: a) the instrumental components: hardware, software, firmware (microprogramming), orgware (organizational knowledge) and b) the application side components: tasks, users,

Operation (operating) and system maintenance.

Conventional computer systems are based on the Von Neumann architecture principle.

The main idea of von Neumann hardware architecture is that one

there is shared memory for software and data, which allows the software to change itself. Five functional units are the

Underlying the architecture: a control unit, an arithmetic unit, a memory, an input unit and an output unit. The central unit is the main memory and the main processor, which contains the control and calculator. The main processor carries information from the

Main memory in its own registers and back via a bus system, which consists of a bidirectional instruction bus and a bidirectional operand bus. In fact, both buses carry information that is interpreted as instructions or operands depending on the bus considered. However, the transported data are determined by their respective address. Both buses usually have access to the same memory areas. Furthermore, in conventional computers

Stored instructions and operands without mutual separation, so that operands such as instructions can be transported on each of the two buses.

In this day and age, when the use of computers dominates everyday life in an omnipresent way, ensuring security in the use of computer systems is an essential consideration.

So-called malware can execute unwanted and potentially harmful functions within the computer system in the form of computer programs by the user. Malware benefits from the

Hardware architecture commercial computer in that they come in the form of operands or modified instructions in the memory areas and from there via the instruction bus to the processors in which they cause their harmful effect.

According to the state of the art, the protection of computer systems from malicious software takes place through the use of defensive software, such

Detects malware and handles it appropriately. This process has as its main disadvantage that it is the creations of the creators of

Malware always lags behind in time, since new malicious software must first be recognized in order to program an antidote, which will eventually be installed and integrated. Furthermore, this defensive software requires resources that are no longer available for the originally intended use of the computer.

From document DE 199 50 255 B4, an optimization of microprocessors is known, which makes it possible to improve the throughput of the CPU by improving the efficiency of the use of the buses. Data and instructions are handled separately during access as well as during storage. Hardware-assured security against malware is not disclosed.

US 7,000,092 B2 discloses a reference system for cooperation several processors. Again, a hardware-guaranteed security against malicious software is not provided.

From document US 8,117,642 B2 a hardware is known which distinguishes between a privileged and secure mode and a non-privileged, potentially unsafe mode, with instructions at the level of routines uniquely and firmly associated with these modes. However, there is no absolute protection for sensitive data when the processor is in potentially unsafe mode.

It is an object of the present invention to provide a data processing system such that the underlying hardware architecture is provided

Impact of malicious software protects.

This object is achieved by a data processing system having the features of claim 1.

Thereafter, a data processing system comprises at least one

Main processor, at least one permanent data storage and

at least one random access memory, wherein the at least one main processor is connected to at least one input / output hardware (interface), and wherein the at least one main processor communicates with the at least one

Main memory communicates via at least one instruction bus and via at least one operand bus and communicates bidirectionally separately with the at least one permanent data memory provided with at least one loading processor which communicates bidirectionally with at least one permanent software memory and at least one external software memory and which communicates with the at least one main memory via at least one instruction bus and at least one

Operand bus separated and independent of the at least one

Main processor communicates, wherein the communication between the at least one main processor and the at least one random access memory via the at least one instruction bus and the at least one

Operand bus takes place, the communication between the at least one loading processor and the at least one main memory via the at least one instruction bus and the at least one operand bus, both the communication between the at least one main processor and the at least one input / output hardware and the at least one permanent data memory as well as the communication between the at least one loading processor and the at least one external one

Software memory and the at least one permanent software storage are controlled by access attributes. Due to the presence of the main processor and the separate charging processor, the

Processor tasks strictly separated.

It is preferably provided that the data in the at least one main memory are categorized according to data categories, wherein in

Depending on the categories different access attributes are defined, namely main processor access attributes for the at least one main processor and load processor access attributes for the at least one loading processor, and wherein data of the same data categories are the same

Main processor access attributes for access by the at least one main processor and the same load processor access attributes for access by the at least one loading processor. Thus, the

Separation of the processor tasks at the level of the data continued, in which certain data categories are assigned to the different processor tasks with access attributes, the access attributes of

Main processor and load processor may be different to the same data category.

It is advantageous if at least one separate main memory is provided for each data category. The separation is thus also made physically, which further supports the strict separation.

The following data categories are preferably provided: address data, instructions, function-internal data, target data of the at least one

Main processors (main processor target data) and target data of the at least one loading processor (loading processor target data).

To protect the computer system from malware is the separation of data categories and processor tasks by main processor and processor

Load processor access attributes checked. It is preferred that the at least one main processor has no access to the at least one permanent software memory, access to the at least one

Has memory for instructions on the at least one instruction bus and this is limited to the type of access "access", has access to the at least one memory for address data on the at least one operand bus and this is limited to the type of access "access" access to the function-internal data about the at least one

Has operand bus and this is done in the access modes "Write" and / or "Read", and access to the main processor target data on the at least one operand bus and this in the access types

"Write" and / or "Read" is done, and no access to the

Charge processor target data of the at least one charging processor has.

Furthermore, it is preferred that the at least one loading processor has access to the at least one external software memory and that this is limited to the access mode "read" and has access to the at least one permanent software memory and this in the access modes

"Write" and / or "Read" takes place, access to the at least one

Has memory for instructions on the at least one operand bus and this is limited to the type of access "write" has access to the at least one memory for instructions on the at least one instruction bus and this is limited to the type of access "access" access to the at least one Memory for the

Ladeproktororzieldaten, address data and function-internal data on the at least one operand bus and this in the access types

"Write" and / or "Read" is done, and no access to the

Main processor target data of the at least one main processor.

In order to protect the computer system against the introduction of malware by media, it is advantageously provided that the data processing system comprises a media processor which communicates via at least one instruction bus and at least one operand bus in each case bidirectionally with at least one separate main memory for media data, wherein the media processor has its own has permanent media data storage with which it communicates bidirectionally, and where the Media processor with its own input / output hardware (interface) is connected. The bidirectional access of the main processor to the media data via the operand bus enables the computer system to securely execute software made available to media.

Regardless of the size of the computer system, the data processing system according to the invention is applicable. In this case, it is advantageous that in the presence of more than one main processor, the main processors can be used independently of one another, each main processor having a memory for main processor target data which is permanently assigned to it

communicates to which the other main processors have no access, and wherein all the main processors have an additional

shared memory for common target data for controlled data passing between the main processors. Through this

Arrangement can be realized, for example, a computer system with "red-black separation".

However, it may also be preferred that in the presence of more than one main processor, the main processors are used independently, all the main processors having common memory for main processor target data with access attributes "Write" and "Read". The shared memory for common target data for controlled data transfer does not exist here and is replaced by a shared memory for all main processor target data.

Furthermore, it is advantageously provided that an external reading device for reading software is provided in the main memory and that the reading device is controlled by the at least one charging processor, wherein the at least one charging processor with the external reading device for software forms an interface that physically so is set up that conventional

Data carriers for data carriers can not be operated so that inadvertent loading of software is prevented. An external reader may be desirable, for example, in organizations where the same computing equipment is required in terms of software. Furthermore, it is preferred that the loading processor in an external

Charger for loading software is arranged in the main memory. This arrangement allows the transfer of software from the charger directly to the memory for Direct Memory Access (DMA) software or similar methods. This is advantageous, for example, for computer systems with a low number of

Software loading operations in which only for this purpose, the external

Charger is connected to the computer system.

In the data processing system according to the invention, it may be preferable for the data categories to have functionally internal data (13) and

Loading processor target data (15) are assigned to the same physical memory.

It is advantageously provided a computer program that implements outputs of program generation tools, wherein the implementation is such that the data categories created and generated as data segments that are processable by the data processing systems of the invention.

Furthermore, a computer program implementing programs executing on the von Neumann architecture or the Harvard architecture is preferably provided, the conversion taking place in such a way that the data categories are created and generated as data segments which are generated by the

Data processing systems according to the invention can be processed.

Preferred embodiments of the invention are explained below with reference to the drawings. In the drawings are the same

Functional elements provided with the same reference numerals.

Show it :

1 shows a block diagram of a Von Neumann hardware architecture,

Fig. 2 is a block diagram of an inventive arrangement with

separate internal charging processor, 3 is a block diagram of the inventive arrangement with additional media processor,

Fig. 4 is a block diagram of an inventive arrangement with

external reader for software,

Fig. 5 is a block diagram of an inventive arrangement with

external charger,

Fig. 6 is a block diagram of an arrangement according to the invention with two independent main processors, each main processor communicating with dedicated main memory destination data memory and both

Main processors data on a common

Replace memory as well

7 shows a block diagram of an arrangement according to the invention with two independent main processors, wherein the

Major processors have shared memory for main processor target data.

Fig. 1 shows the prior art in the form of a block diagram. The illustrated von Neumann hardware architecture consists of a

Main processor 1, a random access memory 2, a permanent one

Data memory 3, an input / output hardware 4 and a bus system 50. In the bus system 50, a distinction is made between instruction bus 60, which transmits the instructions and operand bus 70, which transmits the operands. The main processor 1 communicates bidirectionally with the main memory 2 via the bus system 50. Furthermore, the main processor 1 has bidirectional access to the permanent data memory 3.

In the Fig. 2 is an embodiment of the invention

Data processing system shown. In addition to a main processor 1, which communicates bidirectionally with an input / output hardware 4 and a permanent data memory 3, there is a second processor, the loading processor 8. The loading processor 8 communicates bidirectionally with its own permanent memory 9 for storing software and its own external software memory 10. Both processors are connected via a respective bus system 50, 51 in conjunction with a main memory 2. The bus systems 50, 51 each comprise an instruction bus 60, 61 and a

Operand bus 70, 71 which the respective processor 1, 8 with the

Memory 2 connect. The memory 2 is divided into five physical memory units. In these are the following

Data categories stored: instructions 11, address data 12,

in-function data 13, destination data for the main processor 14 and destination data for the loading processor 15. The main processor 1 and the loading processor 8 have different access rights to the working storage units according to the data categories. In the following, the bus structure 50, 51 becomes closer with the definitions of the data categories and the access rights

described.

The first category of data is that of instructions 11. Instructions 11 are the smallest pieces of software to be executed by the processors. They are read-only accessible to all instructed processors via their instruction bus 60, 61. Only the loading processor 8 may access instructions 11 via its operand bus 71, which is a prerequisite for loading software. Instructions 11 are generated and loaded as part of the generation of software under quality and configuration control.

Another data category is that of the address data 12. Address data 12 serve to associate values with the addresses of the associated software functions. They are read-only accessible to all processors 1 dependent thereon via their operand bus 70. Only the loading processor 8 may write access to address data 12 via its operand bus 71, which is a prerequisite for loading software. Address data 12 are used in the generation of software under quality and

Configuration control generated and loaded.

Another data category is the function-internal data 13.

Functional data 13 are part of the software that controls the Functional sequence serve. They are accessible to read and write access for all processors 1, 8 dependent thereon via their operand bus 70, 71.

In-house data 13 are generated and loaded as part of the generation of software under quality and configuration control.

Another category is the target data for the main processor 14. This data is not part of the program function, but program functions affect that data. They are for the main processor 1 and additional

Processors write and read accessible via their operand bus 70. The loading processor 8 has no access - neither writing nor reading - to this target data 14. This prevents target data 14 can get in this way in memory areas, the instructions 11 or

Address data 12 are reserved.

Furthermore, the main memory 2, the category target data for the

Charging processor 15 on. Target data for the load processor 15 is data that has software functions that do not belong to the software function. They are writable and read accessible only for the loading processor 8 via its operand bus 71. The main processor 1 has no access to this target data 15.

The loading processor 8 is hierarchically subordinate to the main processor 1. Its instruction bus 61 and operand bus 71 are of those of the

Main processors 60, 70 separate and independent. He has to fulfill the following tasks:

- Copy software from external software memory 10 to

Permanent memory for software 9,

Copying software from the permanent software memory 9 into the main memory 2 for instructions 11, in-function data 13 and address data 12

- and possibly convert existing software structures to achieve compatibility with the system architecture.

The system environment determines the performance of the loading processor 8. For systems with a low number of software loads, eg. B.

Embedded systems, the load processor 8 may be an external component that is connected to the system only for this purpose.

The main processor 1 fulfills all other intended tasks of the

Computer. Its instruction bus 60 and operand bus 70 are separate and independent from those of the load processor 61, 71. He has no access to the permanent memory for software 9. Its access to the memory 2 for instructions 11 is limited to reading via the instruction bus 60. Its access to the working memory 2 for address data 12 is limited to the reading via the operand bus 70. Its access to the working memory 2 for its target data 14 is made write and read via the operand bus 70. It has no access to the target data of the loading processor 15th

The main processor 1 is not in the intended transfer of

software involved. But the software currently under development as a subject of software development belongs to the target data category.

During the execution of loading functions, concurrent accesses from the loading processor 8 and the main processor 1 to the working memory 2 for function-internal data 13 and address data 12 are possible. Due to the strict separation of data categories, this situation can not lead to the spread of malicious software. In addition, access to the same data is already prevented by assigning different addresses during software generation and loading.

In the permanent memory for target data 3 only data of the category target data for the main processor 1 are stored. Only the

Main processor 1 has access to this data. The loading processor 8 has no access to this data, neither writing nor reading.

In non-volatile memory for software 9 are data of the categories

Instructions 11, address data 12 and function-internal data 13 stored. The loading processor 8 can access this data in writing and reading. No other processor is allowed to access this memory. Access to this Memory 9 is exclusively related to installing and initializing software. The permanent software memory 9 is described solely for the purpose of software installation.

The embodiment shown in FIG. 3 shows the main component

Elements and their arrangement according to Figure 2. In addition, the structure has a permanent media data memory 16, a media data memory 17, a media data bus system with instruction and

Operand bus 62, 72, a dedicated input / output hardware 40 and a media processor 18 for the processing of data and for the execution of software that are made available via media. The media processor 18 communicates bi-directionally with the input / output hardware 40 and has no access to the other present memories 2, 3, 9. To the

Media data memory 17 has access to only the media processor associated media processor 18 and the main processor 1. Furthermore, only the media associated with the permanent media data store 16

Media processor 18 access. The computer system is thus able by means of a separate media processor 18 to securely execute the software made available by the media.

FIG. 4 essentially shows the block diagram from FIG. 2, wherein the external software memory has been replaced by an external software device 19. The interface to the external software carrier reader 19 is physically arranged so that conventional disk readers can not be operated thereby preventing inadvertent software loading. Applications of this invention are, for example, in embedded systems and in organizations where the same

Computer equipment in terms of software is required.

The embodiment of Figure 5 shows next to a main processor 1, which communicates bidirectionally with an input / output hardware 4 and a permanent data memory 3, a memory 2, via a

Bus system 50 is in communication with the main processor 1 and an external charger 20 for loading software. The bus system 50 includes for communication between the main processor 1 and memory 2 a Instruction bus 60 and an operand bus 70. The memory 2 is divided into four physical memory units. The following data categories are stored in these: instructions 11, address data 12,

function internal data 13 and target data for the main processor 14. The main processor 1 and the external charger 20 have different access rights to the data according to the data categories

Memory units. The external charger 20 exclusively accesses the instructions 11, address data 12 and function-internal data 13

writing to. The main processor 1 reads the instructions 11 via the instruction bus 60 and the address data 12 of the main memory 2 via the operand bus 70. Furthermore, the main processor 1 can write to and read the function-internal data 13 and the target data of the

Main processor 14 of the working memory 2 access.

The external charger 20 represents a separate processor for loading software, wherein the computer system thus equipped does not have its own loading processor and its associated memory. Thus, it does not have the ability to read software directly from external software storage, or to configure software during operation. For loading software, an external device is required in this embodiment, which physically via a corresponding

unmistakable interface features. Applications of this

Exemplary embodiments are, for example, systems whose software is not configured during operation.

The embodiment shown in FIG. 6 shows a first and a second main processor 1, 21, which function independently of each other and which each have a fixed set of associated functional elements. The respective main processor 1, 21 is bidirectionally connected to the respective input / output hardware 4, 22 and the respective permanent data memory 3, 23. Furthermore, each main processor 1, 21 has a

Bus system consisting of instruction and operand bus 60, 63, 70, 73 via which it communicates with the respective main memory 2, 24. The respective working memory 2, 24 is physically separated from each other in four

Shared memory areas. Depending on the access rights of the respective main processors 1, 21 and an existing loading processor 8 are the areas in instructions 11, 25, address data 12, 26,

function-internal data 13, 27 and target data of the respective main processor 14, 28 divided. The loading processor 8, which communicates bidirectionally with an external software memory 10 and a permanent software memory 9, has a bus system consisting of an instruction bus and an operand bus 61, 71. There is also additional memory for the target data of the

Charging processor 15 and provided for transfer data 29. The following explains the access rights of the functional elements. The respective main processor 1, 21 accesses via the respective instruction bus 60, 63 to the instructions 11, 25 and via the operand bus 70, 73 to the address data 12, 26 of the respective random access memory 2, 24 to read. Both read and write the access of the respective main processor 1, 21 takes place on the function-internal data 13, 27 and the target data of the respective main processor 14, 28 in the respective random access memory 2, 24. Bidirektional grab both main processors 1, 21 via their respective operand bus 70, 73 to the memory for transfer data 29 too. On the instructions 11 of the first main processor 1 and the instructions 25 of the second

Main processor 21 is writing from the loading processor 8 via the

Operand bus 71 accessed. The instructions 11 of the first

Main processors 1 are read by the instruction bus 61 of the loading processor 8. Via the operand bus 71 of the loading processor 8, the address data 12, 26 and the function-internal data 13, 27 of the respective main processor 1, 21 and target data of the loading processor 15 are bidirectionally accessed. This two-processor version allows, for example, the secure transfer of data between networks with different

Security rating. The computer systems usually have access to both networks, namely software that has been specially structured and extensively tested for this purpose in order to prevent unintentional or unauthorized data transfers. The same problem occurs in the

Control of effectors based on inputs from various sensors. This is next to the possible and by applying the

data processing system avoidable "infection" with malware among the subsystems in order to avoid situations with hardware To suppress means that can interfere with the driving algorithm.

These negative effects can be determined by the assignment of the sensor and

Effector functions each to avoid a separate processor, the respective processors have clearly defined and realized in the hardware access to their own and shared data.

FIG. 7 shows a further embodiment whose block diagram in FIG

Substantially corresponds to the figure 6. The difference lies in the fact that the memory for transfer data is omitted and only one common

Main memory for target data of the main processors 30 is present, to which both main processors 1, 21 bidirectionally access via their respective operand bus 70, 73. In this embodiment, a typical

Multi-processor application.

In another embodiment, not shown here, the

Target data for the load processor within the in-function data; In this case, the data category target data of the loading processor can be dispensed with.

The data processing system according to the invention prevented by the

Arrangement of functional elements (processors, main memory,

Permanent memory), that any malware through processors

can be executed. Underlying the principle of strict separation of data categories and processor tasks. The invention

Data processing system is applicable in principle to all sizes, from mainframes and multiprocessor systems down to mobile devices. It is understood that the inventive

Data processing system is not limited to the described computer components and number of processors. Depending on the given

System design, the number of processors and the design of additional computer components (eg graphics processors) are freely selectable.

It is due to the separate treatment of the data categories

required, the software for the invention

Adapt data processing system accordingly. reference numeral

main processor

random access memory

permanent data memory of the main processor

Input / output hardware of the main processor

charging processor

permanent software memory

external software memory

instructions

address data

internal functional data

Target data main processor

Target data loading processor

permanent media data store

Media data memory

media processor

External reader

External charger

Second main processor

Input / output hardware of the second main processor Permanent data memory of the second main processor Main memory of the second main processor

Instructions of the second main memory

Address data of the second main memory

in-memory data of second memory destination data main processor of second memory memory for transfer data

Target data Main processors of the first and second main I / O hardware of the media processor

Bus system of the main processor

Bus system of the charging processor Instruction bus of the main processor

Operand bus of the main processor

Instruction bus of the loading processor

Operand bus of the load processor

Instruction bus of the media processor Operand bus of the media processor

Instruction bus of the second main processor Operand bus of the second main processor

Claims

claims

A data processing system comprising at least one main processor (1), at least one permanent data memory (3) and at least one main memory (2), wherein the at least one main processor (1) is connected to at least one input / output hardware (interface) (4) is, and wherein the at least one main processor (1) with the

at least one main memory (2) via at least one

Instruction bus (60) and via at least one operand bus (70) communicates and communicates separately bidirectionally with the at least one permanent data memory (3), characterized

in that at least one charging processor (8) is provided, which communicates bidirectionally with at least one permanent software memory (9) and at least one external software memory (10) and which communicates with the at least one main memory (2) via at least one instruction bus (2). 61) and at least one

Operand bus (71) separately and independently of the at least one main processor (1) communicates, the communication between the at least one

Main processor (1) and the at least one main memory (2) via the at least one instruction bus (60) and the at least one operand bus (70), the communication between the at least one loading processor (8) and the at least one main memory (2) via the at least one instruction bus (61) and the at least one operand bus (71), both the communication between the at least one

Main processor (1) and the at least one input / output hardware (4) and the at least one permanent data memory (3) and the Communication between the at least one loading processor (8) and the at least one external software memory (10) and the at least one permanent software memory (9) via

Access attributes are controlled.

2. Data processing system according to claim 1, characterized in that data in the at least one random access memory (2) after

Data categories are categorized, depending on the categories different access attributes are defined, namely main processor access attributes for the at least one

Main processor (1) and loading processor access attributes for the at least one loading processor (8), and wherein data of the same

Data categories same main processor access attributes for access by the at least one main processor (1) and the same

Charge processor access attributes for access by the at least one loading processor (8).

3. Data processing system according to claim 2, characterized in that at least one separate main memory (11, 12, 13, 14, 15) is provided for each data category.

4. Data processing system according to one of the preceding claims, characterized in that the following data categories are provided:

- address data (12),

- instructions (11),

- functional internal data (13),

Target data of the at least one main processor

(Main processor target data) (14),

- Target data of at least one loading processor

(Loading processor target data) (15).

5. Data processing system according to one of the preceding claims, characterized in that the at least one main processor (1)

- no access to the at least one permanent software Memory (9) has,

Access to the at least one memory for instructions (11) via the at least one instruction bus (60) and this is limited to the type of access "read",

Access to the at least one main memory for address data (12) via the at least one operand bus (70) and this is limited to the type of access "read",

Access to the function-internal data (13) via the at least one

Operand bus (70) and this is done in the access modes "Write" and / or "Read", and

Access to the main processor target data (14) via the at least one

- Has no access to the loading processor target data (15) of the at least one loading processor (8).

6. Data processing system according to one of the preceding claims, characterized in that the at least one charging processor (8)

- Has access to the at least one external software memory (10) and this is limited to the type of access "read", and

- has access to the at least one permanent software memory (9) and this is done in the access modes "Write" and / or "Read",

- access to the at least one main memory for instructions (11) via the at least one operand bus (71) and this is limited to the access type "write",

Access to the at least one instruction memory (11) via the at least one instruction bus (61) and limited to the "read" access mode, Access to the at least one main memory for the

Loading processor target data (15), address data (12) and in-function data (13) via the at least one operand bus (71) and in the "write" and / or "read" access modes, and

- has no access to the main processor target data (14) of the at least one main processor (1).

7. Data processing system according to one of the preceding claims, characterized in that the data processing system comprises a media processor (18) having at least one

Instruction bus (62) and at least one operand bus (72) each bidirectional with at least one separate main memory for

Media data (17) communicates, wherein the media processor (18) has its own permanent media data memory (16) with which it communicates bidirectionally, and wherein the media processor (18) with its own input / output hardware (Interface) (40) is connected ,

8. Data processing system according to one of the preceding claims, characterized in that in the presence of more than one main processor (1), the main processors (1, 21) are independently used, each main processor (1, 21) with a dedicated memory for him Main processor target data (14, 28) to which the other main processors (21, 1) have no access, and wherein all the main processors (1, 21) have an additional common memory for common data transfer (29) between the

Main processors (1, 21).

9. Data processing system according to one of the preceding claims 1 to 7, characterized in that in the presence of more than one main processor (1), the main processors (1, 21) are used independently, wherein all the main processors (1, 21) via a common Memory for main processor target data (30) with the access attributes "Write" and "Read".

10. Data processing system according to one of the preceding claims, characterized in that an external reader (19) for reading software in the working memory (2) is provided and that the reading device (19) is controlled by the at least one charging processor (8), wherein the at least one loading processor (8) interfaces with the external software reader (19), which is physically arranged to provide conventional readers for

Disk can not be operated so that a

unintended loading of software is prevented.

11. Data processing system according to one of the preceding claims 1 to 9, characterized in that the loading processor (8) in an external charger (20) for loading software in the

Main memory (2) is arranged.

12. Data processing system according to one of the preceding claims 1 to 10, characterized in that the data categories

function internal data (13) and loading processor target data (15) are assigned to the same physical memory.

13. Computer program that issues from

Implementation of program generation tools, characterized in that the implementation is such that the data categories are created and generated as data segments that are processed by data processing systems according to claim 1 to 12.

14. Computer program implementing programs executable on von Neumann architecture and / or the Harvard architecture thereby

characterized in that the conversion takes place in such a way that the

Data categories are created and generated as data segments that are processable by data processing systems according to claim 1 to 12.

15. An external charger for loading software into the main memory for a data processing system according to claim 11.

16. An external reading device for reading software by the loading processor for a data processing system according to claim 10.