EP2965433A1 - Successive-approximation-register (sar) analog-to-digital converter (adc) attenuation capacitor calibration method and apparatus - Google Patents

Successive-approximation-register (sar) analog-to-digital converter (adc) attenuation capacitor calibration method and apparatus

Info

Publication number
EP2965433A1
EP2965433A1 EP14714025.5A EP14714025A EP2965433A1 EP 2965433 A1 EP2965433 A1 EP 2965433A1 EP 14714025 A EP14714025 A EP 14714025A EP 2965433 A1 EP2965433 A1 EP 2965433A1
Authority
EP
European Patent Office
Prior art keywords
capacitor
capacitors
sar
coupled
attenuation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14714025.5A
Other languages
German (de)
French (fr)
Other versions
EP2965433B1 (en
Inventor
Ajay Kumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of EP2965433A1 publication Critical patent/EP2965433A1/en
Application granted granted Critical
Publication of EP2965433B1 publication Critical patent/EP2965433B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1057—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
    • H03M1/1061—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values using digitally programmable trimming circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Definitions

  • the present disclosure relates to successive-approximation-register (SAR) analog-to- digital converters (ADCs), and, more particularly, to calibration of an attenuation capacitor in the SAR DAC.
  • SAR successive-approximation-register
  • ADCs analog-to- digital converters
  • Successive-approximation-register (SAR) analog-to-digital converters are frequently the architecture of choice for medium-to-high-resolution applications with medium to high sample rates.
  • Resolutions for SAR ADCs most commonly range from 8 to 16 bits, and they provide low power consumption as well as a small form factor.
  • This combination of features make these ADCs ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data signal acquisition.
  • the SAR ADC basically implements a binary search algorithm. Therefore, while the internal circuitry may be running at several megahertz (MHz), the ADC sample rate is a fraction of that number due to the successive-approximation algorithm.
  • An attenuation capacitor (Ca) may be used between two capacitive DACs inside of a SAR ADC to reduce the range of capacitance values required.
  • One side of the attenuation capacitor (Ca) is coupled to the most significant bit (msb) DAC (mDAC) and the other side of the attenuation capacitor (Ca) is coupled to a lower bit DAC (nDAC).
  • the absolute value of the attenuation capacitor (Ca) depends on the values of the unit capacitors in the DACs ratio between the bottom plate parasitic of the unit capacitor and the top-plate parasitic capacitance of the lower bit DAC capacitors.
  • Attenuation capacitor (Ca) capacitance It is critical to have the attenuation capacitor (Ca) capacitance manufactured to a tolerance of better than 0.25 percent accuracy with respect to the mDAC unit capacitor. Since the attenuation capacitor (Ca) depends on parasitic capacitance in an integrated circuit silicon die on which it is fabricated, this close accuracy has been achieved with prior technologies in two ways: (1) Silicon iteration based on measurement data to correct the parasitic capacitance value and then re-fabricate the silicon die of the SAR DAC ( Figure 1), and (2) use of a varactor (voltage variable capacitor) (Figure 2), that introduces its own variable parasitic capacitance with respect to process and temperature variations.
  • FIG. 1 depicted is a schematic diagram of a typical prior technology split capacitive SAR DAC having an attenuation capacitor (C A ) between an mDAC and an nDAC thereof.
  • C A attenuation capacitor
  • the value of C A with no parasitic capacitance present is:
  • ⁇ is a parasitic dependent factor.
  • a one percent (1%) error (1.6 fF) in C A results in about 0.3 DNL or about 3% error of 1 DNL.
  • the total expected routing capacitor 60fF.
  • C A may be calculated from the parasitic capacitance, but it is impossible to get the correct capacitance needed the first time.
  • FIG. 2 depicted is a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof and a voltage variable capacitor compensation circuit.
  • the prior technology method (2) using a fixed voltage reference (VREF), a compensation DAC (cDAC) 210 for controlling a voltage variable capacitor (varactor) 212 has a big capacitance variation across a range of process, voltage and temperature (PVT) conditions.
  • the varactor is added to correct the parasitic variations of the attenuation capacitor (Ca) but adds much bigger capacitance variation by itself, e.g., the varactor adds parasitic capacitance to the top-plate of the nDAC.
  • Use of the varactor 212 may result in performance variations and differential nonlinearity (DNL) sensitivity across a range PVT conditions.
  • DNL differential nonlinearity
  • an apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter may comprise: a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; an attenuation capacitor coupled between the mDAC and the nDAC; a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and a variable voltage reference may be coupled to the fixed value capacitor; wherein a voltage from the variable voltage reference may be adjusted to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
  • mDAC most significant bit digital-to-analog converter
  • nDAC lower bit digital-to-analog converter
  • a first plate of the correction capacitor may be coupled to the attenuation capacitor and a second plate of the correction capacitor may be coupled to the variable voltage reference.
  • the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal- insulator-metal (MIM) capacitors.
  • the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal- oxide-metal (MOM) capacitors.
  • adjustment of the variable voltage reference may be programmable.
  • the programmable variable voltage reference may be programmed from a successive approximation register (SAR).
  • the SAR controls which of the plurality of binary weighted first and second capacitors may be selected during an analog-to-digital conversion by the SAR DAC.
  • the programmable variable voltage reference may be programmed from the SAR for a plurality of different charges on the correction capacitor to compensate for a plurality of different capacitance value errors of the attenuation capacitor.
  • which one of the plurality of different charges on the correction capacitor may be programmed depends upon which ones of the plurality of binary weighted first and second capacitors may be selected by the SAR.
  • an apparatus for calibrating a successive- approximation register (SAR) analog-to-digital converter may comprise: a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; an attenuation capacitor coupled between the mDAC and the nDAC; a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and a calibration digital-to-analog converter (cDAC) coupled to the fixed value capacitor; wherein a voltage from the cDAC may be programmed to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
  • mDAC most significant bit digital-to-analog converter
  • nDAC lower bit digital-to-analog converter
  • cDAC calibration digital-to-analog converter
  • a first plate of the correction capacitor may be coupled to the attenuation capacitor and a second plate of the correction capacitor may be coupled to the cDAC.
  • the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal-insulator-metal (MIM) capacitors.
  • the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal-oxide-metal (MOM) capacitors.
  • the cDAC may be programmed from a successive approximation register (SAR).
  • the SAR controls which of the plurality of binary weighted first and second capacitors may be selected during an analog-to-digital conversion by the SAR DAC.
  • a voltage reference may be coupled to the cDAC.
  • the voltage reference may be programmable.
  • the programmable variable voltage reference may be programmed from the SAR.
  • the programmable variable voltage reference may be programmed from the SAR for a plurality of different charges on the correction capacitor.
  • which one of the plurality of different charges on the correction capacitor may be programmed depends upon which ones of the plurality of binary weighted first and second capacitors may be selected by the SAR.
  • a method for calibrating a successive- approximation register (SAR) analog-to-digital converter may comprise the steps of: providing a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; providing a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; providing an attenuation capacitor coupled between the mDAC and the nDAC; providing a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and varying a voltage on the correction capacitor to compensate for a capacitance value error of the attenuation capacitor.
  • the variable voltage may be from a variable voltage reference.
  • the variable voltage may be from a calibration digital-to-analog converter (cDAC).
  • Figure 1 illustrates a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof;
  • FIG. 2 illustrates a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof and a voltage variable capacitor compensation circuit; and
  • Figure 3 illustrates a schematic diagram of a split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof, and a fixed capacitance and a variable reference voltage, according to a specific example embodiment of this disclosure.
  • Ca attenuation capacitor
  • the error in the attenuation capacitor (Ca) may be calibrated out using a variable voltage reference and a fixed value correction capacitor, thereby adding another unit element to the nDAC.
  • the nDAC elements are either a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor, wherein these types of capacitors have fixed capacitance values and the parasitic capacitance is on the bottom plates thereof.
  • another calibration DAC may be coupled to the negative side of the unit element added to the nDAC.
  • the cDAC may either have the same number of elements as the nDAC or may be shorter.
  • the DNL error of an nDAC is prominent in the first few MSB elements. Therefore, having a 2 to 3 bit deep calibration cDAC will be sufficient to correct for the error in the attenuation capacitor (Ca).
  • the cDAC receives the same controlled signal and is structured in a similar fashion as the nDAC. Therefore, when the elements of the nDAC transfer the charge to the top plate of the nDAC, the elements of the cDAC will do the same. Hence, the charge transfer for an i th bit element will be: nDACi * Vref + cDACi * Vref var.
  • FIG. 3 depicted is a schematic diagram of a split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof, and a fixed capacitance and a variable voltage reference, according to a specific example embodiment of this disclosure.
  • a fixed value capacitor 320 may be coupled between a top plate of an attenuation capacitor (Ca) 322 and a variable voltage reference 316.
  • variable voltage reference 316 may vary the charge on the fixed value capacitor 320 and thereby compensate for error(s) in the attenuation capacitor (Ca) 322.
  • the calibration DAC (cDAC) 318 may be used in conjunction with or substituted for the variable voltage reference 316, and may be programmed for different charge compensation values from the SAR logic 324 during the iterative SAR DAC capacitive switching process.
  • variable voltage reference 316 and/or a calibration DAC (cDAC) 318 may be used, according to a specific example embodiment of this disclosure.
  • C A 160.89 fF
  • VREFM variable reference voltage
  • a 4 bit cDAC may be controlled from the same code as the nDAC [6:3], and an error of up to ⁇ 0.3% (programmable) may be correctable when using a 0.02 percent step size.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Power Engineering (AREA)

Abstract

A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.

Description

SUCCESSIVE-APPROXIMATION-REGISTER (SAR)
ANALOG-TO-DIGITAL CONVERTER (ADC) ATTENUATION CAPACITOR
CALIBRATION METHOD AND APPARATUS RELATED PATENT APPLICATION
This application claims priority to commonly owned U.S. Provisional Patent Application Number 61/775,326; filed March 8, 2013; which is hereby incorporated by reference herein for all purposes.
TECHNICAL FIELD The present disclosure relates to successive-approximation-register (SAR) analog-to- digital converters (ADCs), and, more particularly, to calibration of an attenuation capacitor in the SAR DAC.
BACKGROUND
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications with medium to high sample rates. Resolutions for SAR ADCs most commonly range from 8 to 16 bits, and they provide low power consumption as well as a small form factor. This combination of features make these ADCs ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data signal acquisition. As the name implies, the SAR ADC basically implements a binary search algorithm. Therefore, while the internal circuitry may be running at several megahertz (MHz), the ADC sample rate is a fraction of that number due to the successive-approximation algorithm.
An attenuation capacitor (Ca) may be used between two capacitive DACs inside of a SAR ADC to reduce the range of capacitance values required. One side of the attenuation capacitor (Ca) is coupled to the most significant bit (msb) DAC (mDAC) and the other side of the attenuation capacitor (Ca) is coupled to a lower bit DAC (nDAC). The absolute value of the attenuation capacitor (Ca) depends on the values of the unit capacitors in the DACs ratio between the bottom plate parasitic of the unit capacitor and the top-plate parasitic capacitance of the lower bit DAC capacitors. It is critical to have the attenuation capacitor (Ca) capacitance manufactured to a tolerance of better than 0.25 percent accuracy with respect to the mDAC unit capacitor. Since the attenuation capacitor (Ca) depends on parasitic capacitance in an integrated circuit silicon die on which it is fabricated, this close accuracy has been achieved with prior technologies in two ways: (1) Silicon iteration based on measurement data to correct the parasitic capacitance value and then re-fabricate the silicon die of the SAR DAC (Figure 1), and (2) use of a varactor (voltage variable capacitor) (Figure 2), that introduces its own variable parasitic capacitance with respect to process and temperature variations.
Referring to Figure 1, depicted is a schematic diagram of a typical prior technology split capacitive SAR DAC having an attenuation capacitor (CA) between an mDAC and an nDAC thereof. A problem exists for fine tuning of the attenuation capacitor (CA) of a SAR DAC using the silicon iteration based process prior technology method (1). The value of CA with no parasitic capacitance present is:
Where a is the ratio between unit capacitors of mDAC and nDAC. The value of CA with parasitic capacitance present is:
C =- 2^- C
4 2Ν λ - α 11
Where λ is a parasitic dependent factor. For example, a 5C-5C-2R implementation of the SAR DAC may have parasitic top-plate routing and a bottom plate of CA, wherein CA is approximately 107.204% of Cu, for Cu = 150 femtofarads (fF) and CA = 160.81F. A one percent (1%) error (1.6 fF) in CA results in about 0.3 DNL or about 3% error of 1 DNL. The total expected routing capacitor = 60fF. CA may be calculated from the parasitic capacitance, but it is impossible to get the correct capacitance needed the first time.
Referring to Figure 2, depicted is a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof and a voltage variable capacitor compensation circuit. The prior technology method (2) using a fixed voltage reference (VREF), a compensation DAC (cDAC) 210 for controlling a voltage variable capacitor (varactor) 212 has a big capacitance variation across a range of process, voltage and temperature (PVT) conditions. The varactor is added to correct the parasitic variations of the attenuation capacitor (Ca) but adds much bigger capacitance variation by itself, e.g., the varactor adds parasitic capacitance to the top-plate of the nDAC. Use of the varactor 212 may result in performance variations and differential nonlinearity (DNL) sensitivity across a range PVT conditions.
SUMMARY
Therefore, a need exists for a way to more easily calibrate an attenuation capacitor in a SAR DAC, and that this calibration remains stable across a wide range of process, voltage and temperature (PVT) conditions.
According to an embodiment, an apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter (ADC) may comprise: a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; an attenuation capacitor coupled between the mDAC and the nDAC; a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and a variable voltage reference may be coupled to the fixed value capacitor; wherein a voltage from the variable voltage reference may be adjusted to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
According to a further embodiment, a first plate of the correction capacitor may be coupled to the attenuation capacitor and a second plate of the correction capacitor may be coupled to the variable voltage reference. According to a further embodiment, the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal- insulator-metal (MIM) capacitors. According to a further embodiment, the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal- oxide-metal (MOM) capacitors. According to a further embodiment, adjustment of the variable voltage reference may be programmable. According to a further embodiment, the programmable variable voltage reference may be programmed from a successive approximation register (SAR). According to a further embodiment, the SAR controls which of the plurality of binary weighted first and second capacitors may be selected during an analog-to-digital conversion by the SAR DAC. According to a further embodiment, the programmable variable voltage reference may be programmed from the SAR for a plurality of different charges on the correction capacitor to compensate for a plurality of different capacitance value errors of the attenuation capacitor. According to a further embodiment, which one of the plurality of different charges on the correction capacitor may be programmed depends upon which ones of the plurality of binary weighted first and second capacitors may be selected by the SAR.
According to another embodiment, an apparatus for calibrating a successive- approximation register (SAR) analog-to-digital converter (DAC) may comprise: a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; an attenuation capacitor coupled between the mDAC and the nDAC; a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and a calibration digital-to-analog converter (cDAC) coupled to the fixed value capacitor; wherein a voltage from the cDAC may be programmed to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
According to a further embodiment, a first plate of the correction capacitor may be coupled to the attenuation capacitor and a second plate of the correction capacitor may be coupled to the cDAC. According to a further embodiment, the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal-insulator-metal (MIM) capacitors. According to a further embodiment, the correction capacitor and the plurality of binary weighted second capacitors may be fixed value metal-oxide-metal (MOM) capacitors. According to a further embodiment, the cDAC may be programmed from a successive approximation register (SAR). According to a further embodiment, the SAR controls which of the plurality of binary weighted first and second capacitors may be selected during an analog-to-digital conversion by the SAR DAC. According to a further embodiment, a voltage reference may be coupled to the cDAC. According to a further embodiment, the voltage reference may be programmable. According to a further embodiment, the programmable variable voltage reference may be programmed from the SAR. According to a further embodiment, the programmable variable voltage reference may be programmed from the SAR for a plurality of different charges on the correction capacitor. According to a further embodiment, which one of the plurality of different charges on the correction capacitor may be programmed depends upon which ones of the plurality of binary weighted first and second capacitors may be selected by the SAR. According to yet another embodiment, a method for calibrating a successive- approximation register (SAR) analog-to-digital converter (DAC) may comprise the steps of: providing a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors; providing a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors; providing an attenuation capacitor coupled between the mDAC and the nDAC; providing a correction capacitor having a fixed capacitance value, wherein the correction capacitor may be coupled to the attenuation capacitor; and varying a voltage on the correction capacitor to compensate for a capacitance value error of the attenuation capacitor. According to a further embodiment of the method, the variable voltage may be from a variable voltage reference. According to a further embodiment of the method, the variable voltage may be from a calibration digital-to-analog converter (cDAC).
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
Figure 1 illustrates a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof;
Figure 2 illustrates a schematic diagram of a typical prior technology split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof and a voltage variable capacitor compensation circuit; and
Figure 3 illustrates a schematic diagram of a split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof, and a fixed capacitance and a variable reference voltage, according to a specific example embodiment of this disclosure.
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
DETAILED DESCRIPTION
According to various embodiments, the error in the attenuation capacitor (Ca) may be calibrated out using a variable voltage reference and a fixed value correction capacitor, thereby adding another unit element to the nDAC. An advantage is that the nDAC elements are either a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor, wherein these types of capacitors have fixed capacitance values and the parasitic capacitance is on the bottom plates thereof. In addition to adding another unit element to the nDAC another calibration DAC (cDAC) may be coupled to the negative side of the unit element added to the nDAC. The cDAC may either have the same number of elements as the nDAC or may be shorter. The DNL error of an nDAC is prominent in the first few MSB elements. Therefore, having a 2 to 3 bit deep calibration cDAC will be sufficient to correct for the error in the attenuation capacitor (Ca). The cDAC receives the same controlled signal and is structured in a similar fashion as the nDAC. Therefore, when the elements of the nDAC transfer the charge to the top plate of the nDAC, the elements of the cDAC will do the same. Hence, the charge transfer for an ith bit element will be: nDACi * Vref + cDACi * Vref var.
By calibrating the reference voltage, Vrefjvar, going only to the cDAC, a correction may be made for the error in the attenuation capacitor (Ca).
According to various embodiments, for correct SAR operation, the change
"sum of (nDACi * Vref + cDACi * Vref_var)"
will result in a least significant bit (LSB) charge change in the mDAC. Therefore, by using a fixed capacitance and a variable reference voltage, calibration of a SAR DAC will be more robust and will have very little variation due to PVT.
Referring now to the drawings, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. Referring to Figure 3, depicted is a schematic diagram of a split capacitive DAC having an attenuation capacitor (Ca) between an mDAC and an nDAC thereof, and a fixed capacitance and a variable voltage reference, according to a specific example embodiment of this disclosure. A fixed value capacitor 320 may be coupled between a top plate of an attenuation capacitor (Ca) 322 and a variable voltage reference 316. The variable voltage reference 316 may vary the charge on the fixed value capacitor 320 and thereby compensate for error(s) in the attenuation capacitor (Ca) 322. The calibration DAC (cDAC) 318 may be used in conjunction with or substituted for the variable voltage reference 316, and may be programmed for different charge compensation values from the SAR logic 324 during the iterative SAR DAC capacitive switching process.
For example, a variable voltage reference 316 and/or a calibration DAC (cDAC) 318 may be used, according to a specific example embodiment of this disclosure. For example: When CA = 160.89 fF, it has to be accurate down to 1 fF. By using, for example but not limited to, a fixed MOM capacitor and a variable reference voltage, VREFM, a 4 bit cDAC may be controlled from the same code as the nDAC [6:3], and an error of up to ± 0.3% (programmable) may be correctable when using a 0.02 percent step size.
CA_err DN L Vea l
1 0.296006 4.736102
2 0.592485 9.479768
3 0.889438 14.231
0.1 0.029579 0.47327
0.2 0.059164 0.946616
0.3 0.088752 1.420037
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.

Claims

CLAIMS What is claimed is:
1. An apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
an attenuation capacitor coupled between the mDAC and the nDAC;
a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
a variable voltage reference is coupled to the fixed value capacitor;
wherein a voltage from the variable voltage reference is adjusted to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
2. The apparatus according to claim 1 , wherein a first plate of the correction capacitor is coupled to the attenuation capacitor and a second plate of the correction capacitor is coupled to the variable voltage reference.
3. The apparatus according to claim 1 , wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-insulator-metal (MIM) capacitors.
4. The apparatus according to claim 1, wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-oxide-metal (MOM) capacitors.
5. The apparatus according to claim 1 , wherein adjustment of the variable voltage reference is programmable.
6. The apparatus according to claim 5, wherein the programmable variable voltage reference is programmed from a successive approximation register (SAR).
7. The apparatus according to claim 6, wherein the SAR controls which of the plurality of binary weighted first and second capacitors are selected during an analog-to- digital conversion by the SAR DAC.
8. The apparatus according to claim 5, wherein the programmable variable voltage reference is programmed from the SAR for a plurality of different charges on the correction capacitor to compensate for a plurality of different capacitance value errors of the attenuation capacitor.
9. The apparatus according to claim 8, wherein which one of the plurality of different charges on the correction capacitor is programmed depends upon which ones of the plurality of binary weighted first and second capacitors are selected by the SAR.
10. An apparatus for calibrating a successive-approximation register (SAR) analog-to-digital converter (DAC), comprising:
a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
an attenuation capacitor coupled between the mDAC and the nDAC;
a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
a calibration digital-to-analog converter (cDAC) coupled to the fixed value capacitor;
wherein a voltage from the cDAC is programmed to vary a charge on the correction capacitor for compensating a capacitance value error of the attenuation capacitor.
1 1. The apparatus according to claim 10, wherein a first plate of the correction capacitor is coupled to the attenuation capacitor and a second plate of the correction capacitor is coupled to the cDAC.
12. The apparatus according to claim 10, wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-insulator-metal (M1M) capacitors.
13. The apparatus according to claim 10, wherein the correction capacitor and the plurality of binary weighted second capacitors are fixed value metal-oxide-metal (MOM) capacitors.
14. The apparatus according to claim 10, wherein the cDAC is programmed from a successive approximation register (SAR).
15. The apparatus according to claim 14, wherein the SAR controls which of the plurality of binary weighted first and second capacitors are selected during an analog-to- digital conversion by the SAR DAC.
16. The apparatus according to claim 14, further comprising a voltage reference coupled to the cDAC.
17. The apparatus according to claim 16, wherein the voltage reference is programmable.
18. The apparatus according to claim 17, wherein the programmable variable voltage reference is programmed from the SAR.
19. The apparatus according to claim 18, wherein the programmable variable voltage reference is programmed from the SAR for a plurality of different charges on the correction capacitor.
20. The apparatus according to claim 19, wherein which one of the plurality of different charges on the correction capacitor is programmed depends upon which ones of the plurality of binary weighted first and second capacitors are selected by the SAR.
21. A method for calibrating a successive- approximation register (SAR) analog- to-digital converter (DAC), said method comprising the steps of:
providing a most significant bit digital-to-analog converter (mDAC) comprising a plurality of binary weighted first capacitors;
providing a lower bit digital-to-analog converter (nDAC) comprising a plurality of binary weighted second capacitors;
providing an attenuation capacitor coupled between the mDAC and the nDAC; providing a correction capacitor having a fixed capacitance value, wherein the correction capacitor is coupled to the attenuation capacitor; and
varying a voltage on the correction capacitor to compensate for a capacitance value error of the attenuation capacitor.
22. The method according to claim 21, wherein the variable voltage is from a variable voltage reference.
23. The method according to claim 21, wherein the variable voltage is from a calibration digital-to-analog converter (cDAC).
EP14714025.5A 2013-03-08 2014-03-06 Successive-approximation-register (sar) analog-to-digital converter (adc) attenuation capacitor calibration method and apparatus Active EP2965433B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361775326P 2013-03-08 2013-03-08
US14/197,951 US8981973B2 (en) 2013-03-08 2014-03-05 Successive-approximation-register (SAR) analog-to-digital converter (ADC) attenuation capacitor calibration method and apparatus
PCT/US2014/021008 WO2014138336A1 (en) 2013-03-08 2014-03-06 Successive-approximation-register (sar) analog-to-digital converter (adc) attenuation capacitor calibration method and apparatus

Publications (2)

Publication Number Publication Date
EP2965433A1 true EP2965433A1 (en) 2016-01-13
EP2965433B1 EP2965433B1 (en) 2020-09-09

Family

ID=51487193

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14714025.5A Active EP2965433B1 (en) 2013-03-08 2014-03-06 Successive-approximation-register (sar) analog-to-digital converter (adc) attenuation capacitor calibration method and apparatus

Country Status (6)

Country Link
US (1) US8981973B2 (en)
EP (1) EP2965433B1 (en)
KR (1) KR20150126597A (en)
CN (1) CN104956593A (en)
TW (1) TWI619352B (en)
WO (1) WO2014138336A1 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103583002A (en) * 2011-05-10 2014-02-12 松下电器产业株式会社 Successive approximation type A/D converter
GB201403082D0 (en) * 2014-02-21 2014-04-09 Ibm Analog-digital converter
US10205462B2 (en) * 2014-12-17 2019-02-12 Analog Devices, Inc. SAR ADCs with dedicated reference capacitor for each bit capacitor
US9287891B1 (en) * 2015-01-20 2016-03-15 Mediatek Inc. Successive approximation register analog to digital converters
US9722624B2 (en) * 2015-04-20 2017-08-01 Samsung Electronics Co., Ltd Semiconductor device comprising successive approximation register analog to digital converter with variable sampling capacitor
TWI568192B (en) * 2015-05-13 2017-01-21 矽創電子股份有限公司 Analog-to-Digital Converting Device, Related Calibration Method and Calibration Module
US9432044B1 (en) * 2015-12-18 2016-08-30 Texas Instruments Incorporated Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter
KR101726754B1 (en) * 2016-03-08 2017-04-14 중앙대학교 산학협력단 Successive approximation register analog to digital converter
TWI591969B (en) 2016-04-15 2017-07-11 瑞昱半導體股份有限公司 Calibration circuit and calibration method for DAC
CN107306135B (en) * 2016-04-22 2020-03-10 瑞昱半导体股份有限公司 Correction circuit and correction method for digital-to-analog converter
US10236903B2 (en) * 2016-05-27 2019-03-19 Mediatek Inc. Charge compensation circuit and analog-to-digital converter with the same
US10256831B2 (en) * 2016-09-21 2019-04-09 Analog Devices Global Method and apparatus to reduce effect of dielectric absorption in SAR ADC
KR102654276B1 (en) 2017-02-13 2024-04-04 에스케이하이닉스 주식회사 Analog to digital converter and semiconductor apparatus using the same
CN107037387B (en) * 2017-06-06 2023-09-29 中国电子技术标准化研究院 Program-controlled high-voltage source
TWI638528B (en) * 2017-08-29 2018-10-11 瑞昱半導體股份有限公司 Data converter and impedance matching control method thereof
US10404264B2 (en) 2017-09-11 2019-09-03 Analog Devices, Inc. Method of performing analog-to-digital conversion
US10305452B2 (en) * 2017-09-28 2019-05-28 Microchip Technology Incorporated Five-level switched-capacitance DAC using bootstrapped switches
US10038453B1 (en) * 2017-10-25 2018-07-31 Texas Instruments Incorporated Capacitor calibration
US10581443B2 (en) * 2017-10-30 2020-03-03 Microchip Technology Incorporated Method and apparatus for offset correction in SAR ADC with reduced capacitor array DAC
US10866269B2 (en) * 2017-11-16 2020-12-15 Microchip Technology Incorporated Fast frequency calculator
TWI665875B (en) * 2018-02-13 2019-07-11 Nuvoton Technology Corporation Digital background calibration circuit
US11070222B2 (en) * 2018-03-19 2021-07-20 Telefonaktiebolaget Lm Ericsson (Publ) Successive-approximation analog-to-digital converter
KR102090205B1 (en) * 2018-10-29 2020-03-17 서강대학교산학협력단 Analog-to-digital converter using separated DAC based switching
US10505559B1 (en) * 2018-11-27 2019-12-10 Ipgreat Incorporated Process, voltage and temperature optimized asynchronous SAR ADC
US10523228B1 (en) * 2018-12-18 2019-12-31 Ipgreat Incorporated Method of capacitive DAC calibration for SAR ADC
CN110266312B (en) * 2019-05-30 2022-09-13 福建工程学院 DAC (digital-to-analog converter) switching method applied to SAR ADC (synthetic aperture radar)
CN110323334B (en) * 2019-07-09 2023-03-24 四川中微芯成科技有限公司 Structure and method for using parasitic capacitor as ADC capacitor
WO2021040029A1 (en) * 2019-08-29 2021-03-04 ヌヴォトンテクノロジージャパン株式会社 Semiconductor circuit
WO2021137686A1 (en) * 2019-12-31 2021-07-08 Mimos Berhad Interfacing circuit and analog to digital converter for battery monitoring applications and a method thereof
KR102878959B1 (en) 2020-09-08 2025-10-29 삼성전자주식회사 Analog digital converter and method for analog to digital converting in the analog digital converter
GB2605466A (en) * 2021-06-21 2022-10-05 Nordic Semiconductor Asa Error-feedback SAR-ADC
CN114928357B (en) * 2022-05-07 2025-05-16 芯海科技（深圳）股份有限公司 Analog-to-digital converter, integrated circuit, electronic device and calibration method
CN117040532A (en) * 2023-08-02 2023-11-10 电子科技大学 Weight error calibration method applied to segmented successive approximation analog-to-digital converter

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE109325T1 (en) * 1988-09-30 1994-08-15 Siemens Ag SELF-CALIBRATION A/D AND D/A CONVERTER.
US6707403B1 (en) * 2002-11-12 2004-03-16 Analog Devices, Inc. Analog to digital converter with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital converter
WO2007041378A1 (en) * 2005-09-30 2007-04-12 Cirrus Logic, Inc. Calibration of a redundant number system successive approximation analog-to-digital converter
DE102006015762B4 (en) * 2006-04-04 2013-05-08 Austriamicrosystems Ag Analog-to-digital converter arrangement and method
JP4977570B2 (en) * 2007-10-03 2012-07-18 株式会社日立製作所 DIGITAL CALIBRATION TYPE ANALOG / DIGITAL CONVERTER AND RADIO RECEIVING CIRCUIT AND RADIO TRANSMITTING / RECEIVER CIRCUIT USING THE SAME
JP5417346B2 (en) 2008-02-28 2014-02-12 ペレグリン セミコンダクター コーポレーション Method and apparatus for use in digitally tuning a capacitor in an integrated circuit element
JP5447011B2 (en) 2010-03-05 2014-03-19 富士通株式会社 A / D conversion apparatus and A / D conversion method
JP5427663B2 (en) 2010-03-24 2014-02-26 スパンション エルエルシー A / D converter
US8446304B2 (en) * 2010-06-30 2013-05-21 University Of Limerick Digital background calibration system and method for successive approximation (SAR) analogue to digital converter
US8587463B2 (en) * 2010-08-16 2013-11-19 The Regents Of The University Of California Signal statistics and compression-based analog-to-digital converters
US8963286B2 (en) * 2011-05-09 2015-02-24 Marvell International Ltd. Finger metal oxide metal capacitor structures
DE102011110115B4 (en) * 2011-08-15 2015-02-26 Texas Instruments Deutschland Gmbh Apparatus and method for measuring the DNL of a SAR ADC

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2014138336A1 *

Also Published As

Publication number Publication date
TWI619352B (en) 2018-03-21
WO2014138336A1 (en) 2014-09-12
EP2965433B1 (en) 2020-09-09
CN104956593A (en) 2015-09-30
KR20150126597A (en) 2015-11-12
US8981973B2 (en) 2015-03-17
TW201448479A (en) 2014-12-16
US20140253351A1 (en) 2014-09-11

Similar Documents

Publication Publication Date Title
US8981973B2 (en) Successive-approximation-register (SAR) analog-to-digital converter (ADC) attenuation capacitor calibration method and apparatus
US12224763B2 (en) Calibration method of capacitor array type successive approximation register analog-to-digital converter
CN107346975B (en) SAR type ADC's high accuracy calibrating device
CN114124094B (en) Analog-to-digital converter and weight capacitance calibration method
WO2017106831A1 (en) Mismatch correction of attenuation capacitor in a sar adc
CN103873059A (en) Digital calibration method for high-precision SAR ADC (successive approximation register analog to digital converter)
CN112383308A (en) Method for calibrating successive approximation type analog-digital converter based on LMS algorithm
CN105959006A (en) Successive approximation type analog-to-digital converter calibration circuit
CN110086468A (en) A kind of weight calibration method of nonbinary gradual approaching A/D converter
CN114614821B (en) SAR ADC offset error correction method and circuit based on differential structure
CN114172513B (en) Successive approximation analog-to-digital converter sectional calibration method
CN119727722B (en) Capacitive mismatch foreground calibration method suitable for SAR ADC
RU2335844C2 (en) Analog-to-digital converter and method of calibration thereof
Lopez-Angulo et al. Calibration of capacitor mismatch and static comparator offset in SAR ADC with digital redundancy
CN115733490A (en) Self-calibrating digital-to-analog converter
CN115940949B (en) Split capacitor structure successive approximation analog-to-digital converter calibration circuit and method
US11476858B2 (en) Advanced successive approximation register analog-to-digital converter and corresponding method
CN114788179A (en) Successive approximation analog-to-digital converter and mismatch voltage detection method
Li et al. Calibration for split capacitor DAC in SAR ADC
US20230318615A1 (en) Oversampled analog to digital converter
CN119382698A (en) Low leakage switched capacitor SAR ADC circuit
KR102075653B1 (en) Analogue-to-digital converter based on integer-based split capacitors
EP3360255B1 (en) Calibratable data converter
Sun et al. Analysis and Design of a 14-bit SAR ADC using self-calibration DAC
Oko-Odion et al. Compact Hybrid Current Source-Capacitor Dacs With Time and Computationally Efficient Digital Calibration for Enhanced Linearity

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20151005

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20190906

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20200330

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1312836

Country of ref document: AT

Kind code of ref document: T

Effective date: 20200915

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602014069953

Country of ref document: DE

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201210

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201209

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201209

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1312836

Country of ref document: AT

Kind code of ref document: T

Effective date: 20200909

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210111

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210109

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602014069953

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20210610

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20210306

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20210331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210331

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210331

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210306

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210306

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210306

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20140306

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230528

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200909

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20260219

Year of fee payment: 13