EP2548125A4 - Communication and process sequencing architecture, system, and method for hardware-in-the-loop simulation - Google Patents

Communication and process sequencing architecture, system, and method for hardware-in-the-loop simulation

Info

Publication number
EP2548125A4
EP2548125A4 EP10848084.9A EP10848084A EP2548125A4 EP 2548125 A4 EP2548125 A4 EP 2548125A4 EP 10848084 A EP10848084 A EP 10848084A EP 2548125 A4 EP2548125 A4 EP 2548125A4
Authority
EP
European Patent Office
Prior art keywords
target
host
side communication
communication loop
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10848084.9A
Other languages
German (de)
French (fr)
Other versions
EP2548125A1 (en
Inventor
Krisada Sangpetchsong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thailand Research Fund
Original Assignee
Thailand Research Fund
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thailand Research Fund filed Critical Thailand Research Fund
Publication of EP2548125A1 publication Critical patent/EP2548125A1/en
Publication of EP2548125A4 publication Critical patent/EP2548125A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/23—Pc programming
    • G05B2219/23446—HIL hardware in the loop, simulates equipment to which a control module is fixed

Abstract

An embedded system simulation architecture includes a target system and a host system providing a graphical simulation environment. The target system includes a transmission module and a reception module operating in a recurrent target-side communication loop. The host system includes a transmission module and a reception module operating in a recurrent host-side communication loop. The host-side communication loop is synchronized to the target-side communication loop by way of packet reception from the target system. Absent such packet reception, the host system remains in a host-side wait state. The target-side communication loop can be synchronized to the host-side communication loop by way of packet reception from the host system. Absent such packet reception, the target system can remain in a target-side wait state. The host system can include a trigger module configured to send a dummy packet to the target system to initiate simulation operations in response to user input.
EP10848084.9A 2010-03-17 2010-03-17 Communication and process sequencing architecture, system, and method for hardware-in-the-loop simulation Withdrawn EP2548125A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/TH2010/000010 WO2011115590A1 (en) 2010-03-17 2010-03-17 Communication and process sequencing architecture, system, and method for hardware-in-the-loop simulation

Publications (2)

Publication Number Publication Date
EP2548125A1 EP2548125A1 (en) 2013-01-23
EP2548125A4 true EP2548125A4 (en) 2013-12-25

Family

ID=44649482

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10848084.9A Withdrawn EP2548125A4 (en) 2010-03-17 2010-03-17 Communication and process sequencing architecture, system, and method for hardware-in-the-loop simulation

Country Status (2)

Country Link
EP (1) EP2548125A4 (en)
WO (1) WO2011115590A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103514337B (en) * 2013-10-25 2016-09-14 北京经纬恒润科技有限公司 A kind of analogue system and method
US11010510B2 (en) 2019-04-30 2021-05-18 Disney Enterprises, Inc. Soft-real-time hub providing data transport for processor-in-the-loop (PIL) simulations
CN114615356B (en) * 2022-03-07 2023-08-04 中国科学院紫金山天文台 Device and method for debugging telescope imaging system by adopting simulator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040221251A1 (en) * 2003-05-01 2004-11-04 Ali Bozkaya Distributed infiniband verification protocol

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070025399A1 (en) * 2002-01-24 2007-02-01 Radioframe Networks, Inc. Method and apparatus for frequency and timing distribution through a packet-based network
WO2004072745A1 (en) * 2003-02-12 2004-08-26 Kabushiki Kaisha Yaskawa Denki Control device and control method capable of external synchronization
US7532637B2 (en) * 2004-03-11 2009-05-12 Omron Corporation Synchronous controller
WO2007032756A1 (en) * 2005-09-09 2007-03-22 Sensormatic Electronics Corporation Eas system providing synchronized transmission
US8762762B2 (en) * 2006-02-15 2014-06-24 Chronologic Pty Ltd Distributed synchronization and timing system for generating local clock signal based on a desired clock signal embedded in USB data stream
US8239158B2 (en) * 2008-08-04 2012-08-07 National Instruments Corporation Synchronizing a loop performed by a measurement device with a measurement and control loop performed by a processor of a host computer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040221251A1 (en) * 2003-05-01 2004-11-04 Ali Bozkaya Distributed infiniband verification protocol

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ALEXANDER BEHRENS ET AL: "MATLAB Meets LEGO Mindstormsâ A Freshman Introduction Course Into Practical Engineering", IEEE TRANSACTIONS ON EDUCATION, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 53, no. 2, 18 August 2009 (2009-08-18), pages 306 - 317, XP011295123, ISSN: 0018-9359 *
MCNINCH ET AL: "AN EXPERIMENTAL MOBILE ROBOT PLATFORM FOR AUTONOMOUS SYSTEMS RESEARCH AND EDUCATION", ROBOTICS AND APPLICATIONS - IASTED INTERNATIONAL CONFERENCE,, 1 January 2009 (2009-01-01), pages 412 - 418, XP009174228 *
See also references of WO2011115590A1 *

Also Published As

Publication number Publication date
EP2548125A1 (en) 2013-01-23
WO2011115590A1 (en) 2011-09-22

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Legal Events

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DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20131125

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 9/44 20060101ALI20131119BHEP

Ipc: G06F 17/50 20060101AFI20131119BHEP

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