EP2532005A1 - Dispositif de mémoire à semi-conducteurs comportant un transistor à corps électriquement flottant, dispositif de mémoire à semi-conducteurs ayant une fonction volatile et non volatile, et procédé de fonctionnement associé - Google Patents

Dispositif de mémoire à semi-conducteurs comportant un transistor à corps électriquement flottant, dispositif de mémoire à semi-conducteurs ayant une fonction volatile et non volatile, et procédé de fonctionnement associé

Info

Publication number
EP2532005A1
EP2532005A1 EP11740503A EP11740503A EP2532005A1 EP 2532005 A1 EP2532005 A1 EP 2532005A1 EP 11740503 A EP11740503 A EP 11740503A EP 11740503 A EP11740503 A EP 11740503A EP 2532005 A1 EP2532005 A1 EP 2532005A1
Authority
EP
European Patent Office
Prior art keywords
region
memory cell
cell
floating body
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP11740503A
Other languages
German (de)
English (en)
Other versions
EP2532005A4 (fr
Inventor
Yuniarto Widjaja
Zvi Or-Bach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zeno Semiconductor Inc
Original Assignee
Zeno Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/797,320 external-priority patent/US8130548B2/en
Priority claimed from US12/797,334 external-priority patent/US8130547B2/en
Priority claimed from US12/897,516 external-priority patent/US8547756B2/en
Priority claimed from US12/897,528 external-priority patent/US8514622B2/en
Priority claimed from US12/897,538 external-priority patent/US8264875B2/en
Application filed by Zeno Semiconductor Inc filed Critical Zeno Semiconductor Inc
Publication of EP2532005A1 publication Critical patent/EP2532005A1/fr
Publication of EP2532005A4 publication Critical patent/EP2532005A4/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells

Definitions

  • the present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device having an electrically floating body transistor and a semiconductor memory device having both volatile and non-volatile functionality.
  • SRAM Static and Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • ZENO-012WO widely used in many applications.
  • SRAM typically consists of six transistors and hence has a large cell size.
  • DRAM unlike DRAM, it does not require periodic refresh operations to maintain its memory state.
  • Conventional DRAM cells consist of a one-transistor and one-capacitor (IT/IC) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance value.
  • DRAM based on the electrically floating body effect has been proposed (see for example "A Capacitor-less IT-DRAM Cell", S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and "Memory Design Using One-Transistor Gain Cell on SOI", T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002) .
  • Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size.
  • such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell.
  • unlike SRAM such DRAM memory cell still requires refresh operation, since the stored charge leaks over time.
  • a conventional 1T/1C DRAM refresh operation involves first reading the state of the memory cell, followed by re-writing the memory cell with the same data.
  • This read-then-write refresh requires two operations: read and write.
  • the memory cell cannot be accessed while being refreshed.
  • An "automatic refresh” method" which does not require first reading the memory cell state, has been described in Fazan et al., U.S. Patent No. 7,170,807. However, such operation still interrupts access to the memory cells being refreshed.
  • Non-volatile memory devices such as flash erasable programmable read only memory (Flash EPROM) devices, retain stored data even in the absence of power supplied thereto.
  • Flash EPROM flash erasable programmable read only memory
  • non-volatile memory devices typically operate more slowly than volatile memory devices .
  • Flash memory device typically employs a floating gate polysihcon as the nonvolatile data storage. This introduces additional process steps from the standard complementary metal -oxide-semiconductor (CMOS) process.
  • CMOS complementary metal -oxide-semiconductor
  • US 2010/0172184 "Asymmetric Single Poly NMOS Non-volatile Memory Cell” to Roizin et al. (“Roizin”) describes a method of forming a single poly non-volatile memory device. Similar to many non-volatile memory devices, it operates more slowly than volatile memory devices. In addition, non-volatile memory devices can only perform limited number of cycles, often referred to as endurance cycle limitation.
  • a universal type memory device that includes the advantages of both volatile and non-volatile memory devices, i.e., fast operation on par with volatile memories, while having the ability to retain stored data when power is discontinued to the memory device. It would further be desirable to provide such a universal type memory device having a size that is not prohibitively larger than comparable volatile or non-volatile devices and which has comparable storage capacity to the same.
  • a method of maintaining a state of a memory cell without interrupting access to the memory cell including: applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
  • the applying comprises applying the back bias to a terminal of the cell that is not used for address selection of the cell.
  • the back bias is applied as a constant positive voltage bias.
  • the back bias is applied as a periodic pulse of positive voltage.
  • a maximum potential that can be stored in the floating body is increased by the application of back bias to the cell, resulting in a relatively larger memory window.
  • the application of back bias performs a holding operation on the cell
  • the method further comprises simultaneously performing a read operation on the cell at the same time that the holding operation is being performed.
  • the cell is a multi-level cell, wherein the floating body is configured to indicate more than one state by storing multi-bits, and the method further includes monitoring cell current of the cell to determine a state of the cell.
  • a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells wherein each memory cell has a floating body region for storing data; the method including: performing a holding operation on at least all of the cells not aligned in a row or column of a selected cell; and accessing the selected cell and performing a read or write operation on the selected cell while performing the hold operation on the at least all of the cells not aligned in a row or column of the selected cell.
  • the performance of a holding operation comprises performing the holding operation on all of the cells and the performing a read or write operation comprises performing a read operation on the selected cell.
  • the holding operation is performed by applying back bias to a terminal not used for memory address selection.
  • the terminal is segmented to allow independent control of the applied back bias to a selected portion of the memory array.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell, and the performing a read or write operation comprises performing a write "0" operation on the selected cell, wherein a write "0" operation is also performed on all of the cells sharing a common source line terminal with the selected cell during the performing a write'O" operation.
  • an individual bit write "0" operation is performed, wherein the performing a holding operation comprises performing the holding operation on all of the cells except for the selected cell, while the performing a read or write operation comprises performing a write "0" operation on the selected cell.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a write "1" operation on the selected cell.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multilevel write operation on the selected cell, using an alternating write and verify algorithm.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multilevel write operation on the selected cell, wherein the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current through the selected cell; and removing the ramped voltage applied once the change in cell current reaches a predetermined value.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a multilevel write operation on the selected cell, wherein the multi-level write operation includes: ramping a current applied to the selected cell to perform the write Atty. Docket: ZENO-012WO operation; reading the state of the selected cell by monitoring a change in voltage across a bit line and a source line of the selected cell; and removing the ramped current applied once the change in cell voltage reaches a predetermined value.
  • the multi-level write operation permits bit-level selection of a bit portion of memory of the selected cell.
  • the performance of a holding operation comprises performing the holding operation on all of the cells except for the selected cell while the performing a read or write operation comprises performing a single- level or multi-level write operation on the selected cell, wherein the single-level and each level of the multi-level write operation includes: ramping a voltage applied to the selected cell to perform the write operation; reading the state of the selected cell by monitoring a change in current toward an addressable terminal of the selected cell; and verifying a state of the write operation using a reference memory cell.
  • the method further includes configuring a state of the reference memory cell using a write-then-verify operation, prior to performing the write operation.
  • configuring a state of the reference memory cell comprises configuring the state upon power up of the memory array.
  • a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells wherein each memory cell has a floating body region for storing data; and wherein the method includes: refreshing a state of at least one of the memory cells; and accessing at least one other of the memory cells, wherein access of the at least one other of the memory cells in not interrupted by the refreshing, and wherein the refreshing is performed without alternating read and write operations.
  • At least one of the memory cells is a multi-level memory cell.
  • a method of operating a memory array having rows and columns of memory cells assembled into an array of the memory cells wherein each memory cell has a floating body region Atty. Docket: ZENO-012WO for storing data; and wherein the method includes: accessing a selected memory cell from the memory cells; and performing a simultaneous write and verify operation on the selected memory cell without performing an alternating write and read operation.
  • the selected memory cell is a multi-level memory cell.
  • a verification portion of the write and verify operation is performed by sensing a current change in the column direction of the array in a column that the selected cell is connected to.
  • a verification portion of the write and verify operation is performed by sensing a current change in the row direction of the array in a row that the selected cell is connected to.
  • a write portion of the write and verify operation employs use of a drain or gate voltage ramp.
  • a write portion of the write and verify operation employs use of a drain current ramp.
  • an integrated circuit in one aspect of the present invention, includes a link or string of semiconductor memory cells, wherein each memory cell comprises a floating body region for storing data; and the link or string comprises at least one contact configured to electrically connect the memory cells to at least one control line, wherein the number of contacts is the same as or less than the number of the memory cells.
  • the number of contacts is less than the number of memory cells.
  • the semiconductor memory cells are connected in series and form the string.
  • the semiconductor memory cells are connected in parallel and form the link.
  • the integrated circuit is fabricated on a silicon-on- insulator (SOI) substrate.
  • SOI silicon-on- insulator
  • the integrated circuit is fabricated on a bulk silicon substrate. Atty. Docket: ZENO-012WO
  • the number of contacts is two, and the number of semiconductor memory cells is greater than two.
  • the memory cells further comprise first and second conductive regions interfacing with the floating body region.
  • the first and second conductive regions are shared by adjacent ones of the memory cells for each the memory cell having the adjacent memory cells.
  • each memory cell further comprises first, second, and third conductive regions interfacing with the floating body region.
  • each memory cell further comprises a gate insulated from the floating body region.
  • At least one of the memory cells is a contactless memory cell.
  • a majority of the memory cells are contactless memory cells.
  • the memory cells store multi-bit data.
  • an integrated circuit in another aspect of the present invention, includes a plurality of contactless semiconductor memory cells, each semiconductor memory cell including: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating body region.
  • the contactless memory cells are connected in series.
  • the contactless memory cells are connected in parallel.
  • the integrated circuit comprises at least one semiconductor memory cell having at least one contact, a total number of the contacts being less than a total number of memory cells that includes a total number of the memory cells having at least one contact and a total number of the contactless memory cells.
  • an integrated circuit in another aspect of the present invention, includes: a plurality of semiconductor memory cells connected in series, each semiconductor memory cell comprising: a floating body region for storing data; Atty. Docket: ZENO-012WO first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate and the floating body region.
  • At least one of the semiconductor memory cells is a contactless semiconductor memory cell.
  • the at least one contactless semiconductor memory cell comprises a third conductive region interfacing with the floating body region.
  • an integrated circuit in another aspect of the present invention, includes a plurality of semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; a conductive region interfacing with the floating body region; a gate above a surface of the floating body region; and an insulating region insulating the gate from the floating substrate region; wherein at least one of the semiconductor memory cells is a contactless semiconductor memory cell.
  • a majority of the semiconductor memory cells are contactless semiconductor memory cells.
  • the integrated circuit comprises a number of contacts, the number being less than or equal to a number of the memory cells.
  • the memory cells each further comprise a second conductive region interfacing with the floating body region.
  • the memory cells each further comprise second and third conductive regions interfacing with the floating body region.
  • an integrated circuit in another aspect of the present invention, includes a plurality of contactless semiconductor memory cells connected in parallel, each semiconductor memory cell comprising: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; and an insulating region insulating the gate and the floating body region.
  • an integrated circuit in another aspect of the present invention, includes: a memory string or link comprising a set of contactless semiconductor memory cells; and a first contact contacting a first additional semiconductor Atty. Docket: ZENO-012WO memory cell; wherein the contactless semiconductor memory cells are accessible via the first contact.
  • the integrated circuit further includes a second contact contacting a second additional semiconductor memory cell; wherein the contactless semiconductor memory cells are accessible via the second contact.
  • the contactless semiconductor memory cells and the additional semiconductor memory cell are connected in series.
  • the memory string or link comprises a first memory string or link and the set comprises a first set
  • the integrated circuit further comprising: a second memory string or link comprising a second set of contactless semiconductor memory cells; and a second contact contacting a second additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the second contact.
  • the memory string or link comprises a first memory string and the set comprises a first set
  • the integrated circuit further comprising: a second memory string comprising a second set of contactless semiconductor memory cells; a third contact contacting a third additional semiconductor memory cell; and a fourth contact contacting a fourth additional semiconductor memory cell; wherein the second set of contactless semiconductor memory cells are accessible via the third and fourth contacts; wherein the first set of contactless semiconductor memory cells, the first additional semiconductor memory cell and the second additional semiconductor memory cell are connected in series, and wherein the second set of contactless semiconductor memory cells, the third additional semiconductor memory cell and the fourth additional semiconductor memory cell are connected in series in the second string.
  • the integrated circuit further includes a first terminal connected to the first contact and the third contact; a second terminal connected to the second contact; and a third terminal connected to the fourth contact.
  • the semiconductor memory cells comprise substantially planar semiconductor memory cells.
  • the semiconductor memory cells comprise fin-type, three-dimensional semiconductor memory cells. Atty. Docket: ZENO-012WO
  • the first set of contactless semiconductor memory cells are aligned side-by side of the second set of contactless semiconductor memory cells;
  • the first string comprises a first set of insulation portions that insulate adjacent memory cells in the first string, and a second set of insulation portions that insulate the memory cells in the first string from adjacent memory cells in the second string;
  • the second string comprises a third set of insulation portions that insulate adjacent memory cells in the second string, and a fourth set of insulation portions that insulate the memory cells in the second string from adjacent memory cells in the first string.
  • the first and second contacts are located at first and second ends of the memory string.
  • each semiconductor memory cell comprises: a floating body region for storing data; first and second conductive regions interfacing with the floating body region; a gate above a surface of the floating region; an insulating region insulating the gate from the floating body region; and a word line terminal electrically connected to the gate.
  • an integrated circuit in another aspect of the present invention includes a plurality of floating body memory cells which are linked either in series or in parallel. The connections between the memory cells are made to reduce the number of contacts for the overall circuit. Because several memory cells are connected either in series or in parallel, a compact memory array is provided.
  • a semiconductor memory cell includes: a substrate having a first conductivity type; a substrate terminal connected to the substrate; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; one of a bit line terminal and a source line terminal connected to the first region; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; the other of the bit line Atty.
  • ZENO-012WO terminal and the source line terminal connected to the second region; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, wherein the first and second storage locations are each configured to receive transfer of data stored by the volatile memory; and a control gate positioned above the trapping layer.
  • the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type; and a buried well terminal connected to the buried layer.
  • the floating body is completely bounded by the top surface, the first and second regions and the buried layer.
  • the first conductivity type is "p" type and the second conductivity type is " " type.
  • the semiconductor memory cell further comprises insulating layers bounding the side surfaces of the substrate.
  • the cell functions as a multi-level cell.
  • At least one of the first and second storage locations is configured so that more than one bit of data can be stored in the at least one of the first and second storage locations, respectively.
  • the floating body is configured so that more than one bit of data can be stored therein.
  • a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a trapping layer having first and second storage locations for storing data as non-volatile memory including:
  • the method further includes shutting down the
  • memory cell device wherein the memory cell device, upon the shutting down, operates as a flash, erasable, programmable read-only memory.
  • the method further includes restoring power to the memory cell, wherein upon the restoring power, carrying out a restore process wherein content of the non-volatile memory is loaded into the volatile memory.
  • a method of operating a memory cell device includes: providing a memory cell device having a plurality of memory cells, each the memory cell having a floating body for storing data as volatile memory and a trapping layer for storing data as non-volatile memory; and operating at least one of the memory cells as a volatile memory cell, independently of the non-volatile memory of the respective memory cell.
  • the operating comprises applying a voltage to a region at a surface of the cell adj acent to a non-volatile storage location of the non-volatile memory.
  • the applying a voltage comprises applying a positive voltage and the floating body of the cell has a p-type conductivity type.
  • the operating comprises operating the volatile
  • memory to perform at least one of a reading operation, a writing operation, and or a holding operation.
  • the method further includes performing a reset operation to initialize a state of the non-volatile memory.
  • the method further includes performing a shadowing operation to load a content of the volatile memory into the non-volatile memory.
  • a semiconductor memory cell in another aspect of the present invention, includes a floating body region for storing data as volatile memory; and a trapping layer for storing data as non-volatile memory; wherein the data stored as volatile memory and the data stored as non-volatile memory are independent of one another, as the floating body region can be operated independently of the trapping layer and the trapping layer can be operated independently of the floating body region.
  • ZENO-012WO ZENO-012WO
  • the floating body region has a first conductivity type and is bounded by a buried layer have a second conductivity type different from the first conductivity type.
  • the first conductivity type is "p" type and the second conductivity type is " " type.
  • the floating body region is bounded by a buried insulator.
  • the floating body region is formed in a substrate, the cell further comprises insulating layers bounding side surfaces of the substrate.
  • the cell functions as a multi -level cell.
  • the trapping layer comprises first and second storage locations, the first and second storage locations each being configured to store data independently of the other, as non-volatile memory.
  • a single polysilicon floating gate semiconductor memory cell includes: a substrate; a floating body region exposed at a surface of the substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating the floating body region from the single polysilicon floating gate; and first and second regions exposed at the surface at locations other than where the floating body region is exposed; wherein the floating gate is configured to receive transfer of data stored by the volatile memory.
  • the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
  • one of the first and second regions at the surface has a higher coupling to the floating gate relative to coupling of the other of the first and second regions to the floating gate.
  • the cell includes a buried layer at a bottom
  • the floating body is bounded by the surface, the first and second regions and the buried layer.
  • insulating layers bound side surfaces of the substrate.
  • a buried insulator layer is buried in a bottom portion of the substrate
  • the floating body is bounded by the surface, the first and second regions and the buried insulator layer.
  • the floating gate overlies an area of the floating body exposed at the surface, and a gap is located between the area overlaid and one of the first and second regions.
  • a select gate is positioned adj acent to the single polysilicon floating gate.
  • the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
  • the select gate overlaps the floating gate.
  • a semiconductor memory cell in another aspect of the present invention, includes: a substrate; a floating body region configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adj acent the substrate and a control gate adj acent the floating gate such that the floating gate is positioned between the control gate and the substrate; and a select gate positioned adjacent the substrate and the floating gate.
  • the floating body is exposed at a surface of the substrate, and the cell further includes: first and second regions each exposed at the surface at locations other than where the floating body region is exposed; wherein the first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
  • first and second regions are asymmetric, wherein a first area defines an area over which the first region is exposed at the surface and a second area defines an area over which the second region is exposed at the surface, and wherein the first area is unequal to the second area.
  • one of the first and second regions at the surface has a higher coupling to the floating gate relative to couphng of the other of the first and second regions to the floating gate.
  • a buried layer is buried in a bottom portion of the substrate, the buried layer having a conductivity type different from a conductivity type of the floating body region.
  • the floating body is bounded by the surface, the first and second regions and the buried layer.
  • insulating layers bound side surfaces of the substrate.
  • a buried insulator layer is buried in a bottom portion of the substrate.
  • the floating body is bounded by the surface, the first and second regions and the buried insulator layer.
  • a single polysilicon floating gate semiconductor memory cell includes: a substrate; a floating body region for storing data as volatile memory, and a single polysilicon floating gate for storing data as non-volatile memory; wherein the floating body region stores the data stored as volatile memory independently of the data stored as non-volatile memory, and the single polysilicon floating gate stores the data stored as volatile memory independently of the data stored as volatile memory.
  • the floating body region has a first conductivity type and is bounded by a buried layer having a second conductivity type different from the first conductivity type.
  • the floating body region is bounded a buried insulator.
  • the first conductivity type is "p" type and the second conductivity type is " " type.
  • insulating layers bound side surfaces of the substrate.
  • a method of operating a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, and a floating gate for storing data as non- Atty. Docket: ZENO-012WO volatile memory is provided, including: operating the memory cell as a volatile memory cell when power is supplied to the memory cell; upon discontinuation of power to the memory cell, resetting non-volatile memory of the memory cell to a predetermined state; and performing a shadowing operation wherein content of the volatile memory cell is loaded into the non-volatile memory.
  • the method further includes shutting down the memory cell device, wherein the memory cell device, upon the shutting down, operates as a flash, erasable, programmable read-only memory.
  • the method further includes restoring power to the memory cell, wherein upon the restoring power, carrying out a restore process wherein content of the non-volatile memory is loaded into the volatile memory.
  • a method of operating a memory cell device includes : providing a memory cell device having a plurality of memory cells each having a floating body for storing data as volatile memory, a floating gate for storing data as non-volatile memory, and a control gate; and operating the memory cell as a volatile memory cell independent of the nonvolatile memory data.
  • the method further includes applying a voltage to the control gate to invert a channel region underneath the floating gate, regardless of charge stored in the floating gate.
  • the method further includes applying a positive voltage to a region of the substrate coupled to the floating gate, and wherein the floating body has a "p" type conductivity type.
  • the operation the memory cell as a volatile memory comprises performing at least one of reading, writing, and holding operations.
  • the method further includes performing a reset operation to initialize a state of the non-volatile memory.
  • the method further includes performing a
  • Fig. 1 is a schematic illustration of a memory cell according to an embodiment of the present invention.
  • Fig. 2 schematically illustrates multiple cells joined in an array to make a memory device according to an embodiment of the present invention..
  • FIG. 3 schematically illustrates n-p-n bipolar devices that are inherently formed in a memory cell according to an embodiment of the present invention.
  • Fig. 4A illustrates segmenting of substrate terminals in an array according to an embodiment of the present invention.
  • Fig. 4B schematically illustrates multiplexers used to determine the biases applied to segmented substrate terminals according to an embodiment of the present invention.
  • Fig. 4C schematically illustrates use of a voltage generator circuitries to input positive bias to the multiplexers according to an embodiment of the present invention.
  • Fig. 5 graphically illustrates that the maximum charge stored in a floating body of a memory cell can be increased by applying a positive bias to the substrate terminal according to an embodiment of the present invention.
  • Fig. 6A graphs floating body potential as a function of floating body current and substrate potential according to an embodiment of the present invention.
  • Fig. 6B graphs floating body potential as a function of floating body current and buried well potential according to an embodiment of the present invention.
  • Fig. 7 shows bias conditions for a selected memory cell and unselected memory cells in a memory array according to an embodiment of the present invention.
  • FIG. 8A illustrates an unselected memory cell sharing the same row as a selected memory cell during a read operation of the selected memory cell according to an embodiment of the present invention.
  • Fig. 8B illustrates the states of the n-p-n bipolar devices of the unselected memory cell of Fig. 8A during the read operation of the selected memory cell according to the embodiment of Fig. 8A.
  • Fig. 8C illustrates an unselected memory cell sharing the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment of Fig. 8A.
  • Fig. 8D illustrates the states of the n-p-n bipolar devices of the unselected memory cell of Fig. 8C during the read operation of the selected memory cell according to the embodiment of Fig. 8A.
  • Fig. 8E illustrates an unselected memory cell that shares neither the same row nor the same column as a selected memory cell during a read operation of the selected memory cell according to the embodiment of Fig. 8A.
  • Fig. 8F illustrates the states of the n-p-n bipolar devices of the unselected memory cell of Fig. 8E during the read operation of the selected memory cell according to the embodiment of Fig. 8A.
  • Fig. 9 is a schematic illustration of a write "0" operation to a memory cell according to an embodiment of the present invention.
  • Fig. 10 shows an example of bias conditions for a selected memory cell and unselected memory cells during a write "0" operation in a memory array according to an embodiment of the present invention.
  • Fig. 11A illustrates an example of bias conditions on unselected memory cells during a write "0" operation according to an embodiment of the present invention.
  • Fig. 11B shows an equivalent circuit diagram for the cell of Fig. 1 1A illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 12 shows bias conditions for selected and unselected memory cells of a memory array during a write "0" operation according to an embodiment of the present invention.
  • Fig. 13A illustrates an example of bias conditions on a selected memory cell during a write "0" operation according to an embodiment of the present invention.
  • Fig. 13B shows an equivalent circuit diagram for the cell of Fig. 13A illustrating the intrinsic n-p-n bipolar devices. Atty. Docket: ZENO-012WO
  • Fig. 13C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write "0" operation of the selected memory cell, according to the embodiment of Fig. 13 A.
  • Fig. 13D shows an equivalent circuit diagram for the cell of Fig. 13C illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 13E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write "0" operation of the selected memory cell, according to the embodiment of
  • Fig. 13F shows an equivalent circuit diagram for the cell of Fig. 13E illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 13G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write "0" operation of the selected memory cell, according to the embodiment of Fig. 13A.
  • Fig. 13H shows an equivalent circuit diagram for the cell of Fig. 13G illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 14 illustrates an example of bias conditions of a selected memory cell and unselected memory cells in an array under a band-to-band tunneling write "1" operation of the selected cell according to an embodiment of the present invention.
  • Fig. 15A illustrates an example of bias conditions on the selected memory cell of Fig. 14.
  • Fig. 15B shows an equivalent circuit diagram for the cell of Fig. 15A illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 15C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write
  • FIG. 15D shows an equivalent circuit diagram for the cell of Fig. 15C illustrating the intrinsic n-p-n bipolar devices. Atty. Docket: ZENO-012WO
  • Fig. 15E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write "1" operation of the selected memory cell, according to the embodiment of Fig. 15 A.
  • Fig. 15F shows an equivalent circuit diagram for the cell of Fig. 15E illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 15G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write "1" operation of the selected memory cell, according to the embodiment of Fig. 15A.
  • Fig. 15H shows an equivalent circuit diagram for the cell of Fig. 15G illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 16A shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to an embodiment of the present invention.
  • Fig. 16B shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.
  • Fig. 16C shows a reference generator circuit which serves to generate the initial cumulative cell current of the memory cells sharing the same source line being written, according to another embodiment of the present invention.
  • Fig. 17 graphically illustrates that the potential of the floating body of a memory cell will increase over time as bias conditions are applied that will result in hole injection to the floating body, according to an embodiment of the present invention.
  • Fig. 18A schematically illustrates reference generator circuitry and read circuitry connected to a memory array according to an embodiment of the present invention.
  • Fig. 18B shows a schematic of a voltage sensing circuitry configured to measure the voltage across the source line and the bit line terminals of a memory cell according to an embodiment of the present invention.
  • Fig. 19 illustrates bias conditions on a selected cell and unselected cells of an array during a read operation on the selected cell according to an embodiment of the present invention.
  • Fig. 20 illustrates bias conditions on a selected cell and unselected cells of an array during a write "0" operation on the selected cell according to an embodiment of the present invention.
  • Fig. 21 illustrates bias conditions on a selected cell and unselected cells of an array during a write "0" operation on the selected cell according to another embodiment of the present invention.
  • Fig. 22 illustrates bias conditions on a selected cell and unselected cells of an array during a band-to-band tunnehng write "1" operation on the selected cell according to another embodiment of the present invention.
  • FIG. 23A is a schematic illustration of a memory cell according to another embodiment of the present invention.
  • FIG. 23B is a schematic illustration of a memory cell according to another embodiment of the present invention showing contacts to the buried well and substrate regions.
  • Fig. 24 schematically illustrates an array of memory cells of the type illustrated in Fig. 23.
  • Fig. 25 schematically illustrates n-p-n bipolar devices inherent in the cell of Fig. 23.
  • Fig. 26 illustrates an example of bias conditions on an array during performance of a read operation on a selected cell according to an embodiment of the present invention.
  • Fig. 27 illustrates bias conditions on a selected cell and unselected cells of an array during a write "0" operation on the selected cell according to an embodiment of the present invention.
  • Fig. 28A illustrates an example of bias conditions on the selected memory cell of Fig. 27.
  • Fig. 28B shows an equivalent circuit diagram for the cell of Fig. 28A illustrating the intrinsic n-p-n bipolar devices.
  • FIG. 28C illustrates an example of bias conditions on unselected memory cells sharing the same row as a selected memory cell in an array during a write Atty. Docket: ZENO-012WO
  • Fig. 28D shows an equivalent circuit diagram for the cell of Fig. 28C illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 28E illustrates an example of bias conditions on unselected memory cells sharing the same column as a selected memory cell in an array during a write "0" operation of the selected memory cell, according to the embodiment of
  • Fig. 28F shows an equivalent circuit diagram for the cell of Fig. 28E illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 28G illustrates an example of bias conditions on unselected memory cells that share neither the same row nor the same column as a selected memory cell in an array during a write "0" operation of the selected memory cell, according to the embodiment of Fig. 27.
  • Fig. 28H shows an equivalent circuit diagram for the cell of Fig. 28G illustrating the intrinsic n-p-n bipolar devices.
  • Fig. 29 illustrates an example of bias conditions applied to a selected memory cell under a band-to-band tunneling write "1" operation according to an embodiment of the present invention.
  • Fig. 30 is a schematic illustration of a memory cell according to another embodiment of the present invention.
  • Fig. 31 is a schematic illustration of a memory cell according to another embodiment of the present invention.
  • Fig. 32 is a schematic illustration of a memory cell according to another embodiment of the present invention.
  • Fig. 33 is a schematic illustration of a memory cell according to another embodiment of the present invention.
  • Fig. 34 is a top view, schematic illustration of a memory cell of Figs. 30 and 32.
  • FIGs. 35A through 35E illustrate an array and details of a first exemplary memory cell according to the present invention.
  • Figs. 36A through 36U illustrate a method of manufacturing a memory cell according to the present invention.
  • Figs. 37A through 37C illustrate a method of maintaining the state of a memory cell according to the present invention.
  • Figs. 38A through 38D illustrate methods of mamtaining the state of the data stored in an array of memory cells according to the present invention.
  • Fig. 39 is a graph of the floating body voltage in a memory cell
  • Fig. 40 is a graph of current-voltage curves of a memory cell according to the present invention.
  • Fig. 41 illustrates a read operation performed on an array of memory cells according to the present invention.
  • Figs. 42A through 42H illustrate the operation of four representative memory cells of the array of Fig. 41.
  • Figs. 43A and 43B illustrates the operation of selected memory cells according to the present invention during a first type of write logic-0 operation.
  • Fig. 44 illustrates an array of memory cells according to the present invention during the first type of write logic-0 operation of Fig. 43.
  • Fig. 45 illustrates the operation of unselected memory cells according to the present invention of the array of Fig. 46 during a second type of write logic-0 operation.
  • Fig. 46 illustrates an array of memory cells according to the present invention during a second type of write logic-0 operation.
  • Fig. 47 illustrates an array of memory cells according to the present invention during a third type of write logic-0 operation.
  • Figs. 48A through 48H illustrate the operation of four representative memory cells of the array of Fig. 47 during the third type of logic operation.
  • Fig. 49 illustrates an array of memory cells according to the present invention during a first type of write logic- 1 operation.
  • FIGs. 50A through 50H illustrate the operation of four representative memory cells of the array of Fig. 15 during the first type of write logic- 1 operation.
  • Fig. 51 illustrates an array of memory cells according to the present invention during a second type of write logic- 1 operation.
  • Figs. 52A through 52H illustrate the operation of four representative memory cells of the array of Fig. 51 during the second type of write logic- 1 operation.
  • Figs. 53A through 53D illustrate a second exemplary memory cell
  • Figs. 54A through 54H illustrate performing operations on an array of the memory cell of Figs. 53A through 53D.
  • Figs. 55A through 55F illustrate multilevel operations on a memory cell according to the present invention.
  • Fig. 56 illustrates an alternate memory cell according to the present invention.
  • Fig. 57 illustrates a top view of the memory cell of Fig. 56.
  • Fig. 58A illustrates another alternate memory cell according to the
  • Fig 58B illustrates an array of the memory cell of Fig. 58A.
  • FIGs. 59A through 59F illustrate a third exemplary memory cell
  • Figs. 60A through 60F illustrate an alternate physical embodiment of the memory cell of Figs. 59A through 59F.
  • Fig. 61A illustrates an array of the memory cell of the embodiments of
  • Fig. 61B illustrates a circuit schematic of an individual cell of the
  • Fig. 62 illustrates a hold operation performed on the array of Fig. 61A.
  • Fig. 63 illustrates a read operation performed on the array of Fig. 61A.
  • Figs. 64A through 64P illustrate the operation of eight representative memory cells of the array of Fig. 63.
  • Fig. 65 illustrates a two row write logic-0 operation on the memory array of Fig. 61 A.
  • Figs. 66A and 66B illustrate the operation of unselected memory cells in
  • Fig. 67 illustrates a single column write logic-0 operation on the memory array of Fig. 61A.
  • Fig. 68 illustrates a single memory cell write logic-0 operation on the memory array of Fig. 61A.
  • Figs. 69A through 69P illustrate the operation of eight representative memory cells of the array of Fig. 68.
  • Fig. 70 illustrates a single memory cell write logic-1 operation on the memory array of Fig. 61A.
  • Figs. 71 A through 71P illustrate the operation of eight representative memory cells of the array of Fig. 70.
  • Fig. 72 illustrates an alternate single memory cell write logic-1 operation on the memory array of Fig. 61A.
  • Figs. 73A through 73B illustrates a possible write disturb condition resulting from the single memory cell write logic-1 operation of Fig. 72.
  • Fig. 74 illustrates another alternate single memory cell write logic-1 operation on the memory array of Fig. 61A.
  • Figs. 75A and 75B illustrates additional alternate methods of
  • Figs. 76A through 76AA illustrate a method of manufacturing the
  • FIGs. 77A through 77F illustrate a fourth exemplary memory cell
  • Figs. 78A and 78B illustrate different holding operations on a memory array of the memory cells of Figs. 77A through 77F.
  • Figs. 79 and 80A through 80H illustrate a read operation on a memory array of the memory cells of Figs. 77A through 77F.
  • Fig. 81 illustrates a single memory cell write logic-0 operation on the memory array of Fig. 77F.
  • Figs. 82A through 82B illustrate the operation of the unselected memory cells of the array of Fig. 81.
  • Fig. 83 illustrates a single memory cell write logic-0 operation on the memory array of Fig. 77F. Atty. Docket: ZENO-012WO
  • Figs. 84A through 84H illustrate the operation of four representative memory cells of the array of Fig. 83.
  • Figs. 85A through 85F illustrate a fifth exemplary memoiy cell according to the present invention.
  • Fig. 86 illustrates the hold operation when using memoiy cells of the present invention in SCR mode.
  • Fig. 87 illustrates the single cell read operation when using memoiy cells of the present invention in SCR mode.
  • Fig. 88 illustrates the single cell write logic- 1 operation when using
  • Fig. 89 illustrates the single cell write logic-0 operation when using
  • Figs. 90A through 90C illustrate standard MOSFET transistors of the prior art.
  • Fig. 91 schematically illustrates a memoiy cell in accordance with an embodiment of the present invention.
  • Fig. 92A schematically illustrates a memoiy array having a plurality of memoiy cells according to an embodiment of the present invention.
  • Fig. 92B schematically illustrates a memoiy array having a plurality of memoiy cells , with read circuitry connected thereto that can be used to determine data states, according to an embodiment of the present invention
  • Fig. 93 shows exemplary bias conditions for reading a selected memoiy cell, as wells as bias conditions of unselected memoiy cells in a memoiy array according to an embodiment of the present invention.
  • Fig. 94A shows exemplary bias conditions for reading a selected memoiy cell according to an embodiment of the present invention.
  • Figs. 94B-94D illustrate bias conditions on unselected memoiy cells during the exemplary read operation described with regard to Fig. 93, according to an embodiment of the present invention.
  • FIG. 95 schematically illustrates and example of a write "0" operation of a cell according to an embodiment of the present invention.
  • Figs. 96A-96B show an example of bias conditions of selected and unselected memory cells during a write "0" operation according to an embodiment of the present invention.
  • Fig. 97 illustrates bias conditions for cells in an array during a write "0" operation in which all memory cells sharing the same BL terminal are written into state “0" according to an embodiment of the present invention.
  • Fig. 98 illustrates bias conditions for selected and unselected memory cells of a memory array for a write "0" operation according to an alternative embodiment of the present invention.
  • Fig. 99A illustrates bias conditions of the selected memory cell under the write "0" operation described with regard to the example of Fig. 98.
  • Figs. 99B-99D illustrate examples of bias conditions on the unselected memory cells during write "0" operations described with regard to the example shown in Fig. 98.
  • Figs. 100 and 101A illustrate an example of the bias conditions of a selected memory cell under a write "1" operation using band-to-band tunneling according to an embodiment of the present invention.
  • Figs. 101B-101D show examples of bias conditions of the unselected memory cells during write "1" operations of the type described with regard to
  • Fig. 102 schematically illustrates bias conditions on memory cells during a write "1" operation using impact ionization according to and embodiment of the present invention.
  • Figs. 103A-103D and 104 illustrate an example of the bias conditions of the selected memory cell 750 under a write "1" operation using an impact ionization write “1" operation according to an embodiment of the present invention.
  • Fig. 105 illustrates a prior art arrangement in which adjacent memory cells share common contacts.
  • FIG. 106A shows a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.
  • Fig. 106B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.
  • Fig. 107 shows an equivalent circuit representation of the memory array of Fig. 106B.
  • Figs. 108 and 109A-109B illustrate bias conditions during a read operation according to an embodiment of the present invention.
  • Figs. 110-11 1 illustrate bias conditions during a write "0" operation according to an embodiment of the present invention.
  • Figs. 112A-112B illustrate bias conditions during a write "0" operation that allows for individual bit writing according to an embodiment of the present invention.
  • Figs. 1 13A-1 13B illustrate bias conditions during a band-to-band tunneling write "1" operation according to an embodiment of the present invention.
  • Figs. 114A-1 14B illustrate bias conditions during an impact ionization write "1" operation according to an embodiment of the present invention.
  • Fig. 115A schematically illustrates a fin-type, three-dimensional memory cell according to an embodiment of the present invention.
  • Fig. 115B schematically illustrates a fin-type, three-dimensional memory cell according to another embodiment of the present invention.
  • Fig. 1 16A shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell of Fig. 23 when the floating body region is positively charged and a positive bias voltage is applied to the buried well region according to an embodiment of the present invention.
  • Fig. 1 16B shows an energy band diagram of the intrinsic n-p-n bipolar device of the cell of Fig. 23 when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region according to an embodiment of the present invention.
  • Fig. 117 schematically illustrates bias conditions on memory cells during a read operation of a selected memory cell according to an embodiment of the present invention. Atty. Docket: ZENO-012WO
  • Fig. 118 schematically illustrates bias conditions on memory cells during a write "0" operation according to an embodiment of the present invention.
  • Fig. 119 schematically illustrates bias conditions on memory cells during a write "0" operation according to another embodiment of the present invention.
  • Fig. 120A schematically illustrates an example of bias conditions of a selected memory cell under a band-to-band tunneling write "1" operation according to an embodiment of the present invention.
  • Fig. 120B shows bias conditions of selected and unselected memory cells
  • Fig. 121A shows a cross -sectional schematic illustration of a memory string according to an embodiment of the present invention.
  • Fig. 121B shows a top view schematic illustration of a memory cell array including two strings of memory cells between the SL terminal and BL terminal according to an embodiment of the present invention.
  • Fig. 121C shows an equivalent circuit representation of a memory array that includes strings shown in Fig. 121B as well as additional strings, in accordance with an embodiment of the present invention.
  • Fig. 122 shows bias conditions on a memory string during a read operation according to an embodiment of the present invention.
  • Fig. 123A illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a read operation according to an embodiment of the present invention.
  • Fig. 123B illustrates the array of Fig. 123A with read circuitry attached to measure or sense the current flow from the BL terminal to the SL terminal in regard to the selected cell, according to an embodiment of the present invention.
  • Fig. 124 shows bias conditions on a memory string during a write "0" operation according to an embodiment of the present invention.
  • Fig. 125 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write "0" operation according to an embodiment of the present invention.
  • Fig. 126 shows bias conditions on a memory string during a write "0" operation that allows for individual bit writing according to an embodiment of the present invention.
  • Fig. 127 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a write "0" operation that allows for individual bit writing according to an embodiment of the present invention.
  • Fig. 128 shows bias conditions on a memory string during a band-to- band tunneling write "1" operation according to an embodiment of the present invention.
  • Fig. 129 illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during a band-to-band tunneling write "1" operation according to an embodiment of the present invention.
  • Fig. 130A shows bias conditions on a memory string during an impact ionization write "1" operation according to an embodiment of the present invention.
  • Fig. 130B illustrates bias conditions on a selected memory cell as well as unselected memory cells in the same and in other strings, during an impact ionization write "1" operation according to an embodiment of the present invention.
  • Fig. 131 A schematically illustrates a top view of two strings of memory cells in a memory array according to an embodiment of the present invention.
  • Fig. 131B is a cross -sectional view of a string from the array illustrated in Fig. 131 A.
  • Figs. 132A-132U illustrates various stages during manufacture of a memory array according to an embodiment of the present invention.
  • Fig. 133 schematically illustrates a link of memory cells connected in parallel according to an embodiment of the present invention.
  • Fig. 134A schematically illustrates a top view of a memory cell of the link of Fig. 133.
  • Fig. 134B is a sectional view of the memory cell of Fig. 48A taken along line l-r of Fig. 134A. Atty. Docket: ZENO-012WO
  • Fig. 134C is a sectional view of the memory cell of Fig. 48A taken along line ll-ir of Fig. 134A.
  • Fig. 135 shows an equivalent circuit representation of a memory array that includes the link of Fig. 133, according to an embodiment of the present invention.
  • Fig. 136 is a schematic illustration of an equivalent circuit of a memory array of hnks in which a read operation is being performed on a selected memory cell of one of the hnks according to an embodiment of the present invention.
  • Fig. 137 schematically illustrates the selected memory cell of the array represented in Fig. 135 and bias conditions thereon during the read operation.
  • Fig. 138 is a schematic illustration of an equivalent circuit of a memory array in which a write "0" operation is being performed on a selected link of the array according to an embodiment of the present invention.
  • Fig. 139 schematically illustrates a memory cell of the link represented in Fig. 138 that is having a write "0" operation performed thereon according to an embodiment of the present invention.
  • Fig. 140 is a schematic illustration of an equivalent circuit of a memory array in which a write "0" operation is being performed according to an alternative embodiment of the present invention.
  • Fig. 141 schematically illustrates a memory cell of the array represented in Fig. 140 that is having a write "0" operation performed thereon according to the alternative embodiment described with regard to Fig. 140.
  • Fig. 142 is a schematic illustration of an equivalent circuit of a memory array in which a write "1" operation is being performed by impact ionization according to an embodiment of the present invention.
  • Fig. 143 schematically illustrates a selected memory cell of the array of
  • Fig. 144 schematically illustrates a link according to another embodiment of the present invention.
  • FIG. 145A schematically illustrates a top view of a memory cell of the memory array of Fig. 144. Atty. Docket: ZENO-012WO
  • Fig. 145B is a sectional view of the memory cell of Fig. 145A taken along line ⁇ - ⁇ of Fig. 145A.
  • Fig. 145C is a sectional view of the memory cell of Fig. 145A taken along line ⁇ - ⁇ of Fig. 145A.
  • Fig. 146 shows an equivalent circuit representation of a memory array of links, including the link of Fig. 144.
  • Fig. 147 is a schematic illustration of an equivalent circuit of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.
  • Fig. 148 schematically illustrates the selected memory cell of the array represented in Fig. 147 and bias conditions thereon during the read operation.
  • Fig. 149 is a schematic illustration of an equivalent circuit of a memory array in which a write "0" operation is being performed according to an embodiment of the present invention.
  • Fig. 150 schematically illustrates a memory cell of the array represented in Fig. 149 that is having a write "0" operation performed thereon according to an embodiment of the present invention.
  • Fig. 151 is a schematic illustration of an equivalent circuit of a memory array in which a write "0" operation is being performed according to an alternative embodiment of the present invention that allows for individual bit writing.
  • Fig. 152 schematically illustrates a selected memory cell of the array represented in Fig. 151 that is being written to by the write "0" operation according to the alternative embodiment described with regard to Fig. 151.
  • Fig. 153 is a schematic illustration of an equivalent circuit of a memory array in which a write "1" operation is being performed by impact ionization according to an embodiment of the present invention.
  • Fig. 154 schematically illustrates a selected memory cell of the array of
  • Fig. 155 is a schematic illustration of an equivalent circuit of a memory array in which a write "1" operation is being performed by impact ionization according to an embodiment of the present invention.
  • Fig. 156 schematically illustrates a selected memory cell of the array of
  • Fig. 157 shows a memory array where adjacent regions are connected a common BL terminal through a conductive region according to an alternative embodiment of the present invention.
  • Fig. 158A shows a memory array according to another embodiment of the present invention.
  • Fig. 158B shows, in isolation, a memory cell from the memory array of
  • Figs. 158C and 158D show sectional views of the memory cell of Fig.
  • Fig. 159 is an equivalent circuit representation of a memory array of the type shown in Fig. 158A according to an embodiment of the present invention.
  • Fig. 160A shows an equivalent circuit representation of the memory cell of Figs. 158B-158D according to an embodiment of the present invention.
  • Fig. 160B shows an energy band diagram of the intrinsic n-p-n bipolar device of Fig. 160A when the floating body region is positively charged and a positive bias voltage is applied to the buried well region, according to an embodiment of the present invention.
  • Fig. 160C shows an energy band diagram of the intrinsic n-p-n bipolar device 30 of Fig. 160A when the floating body region is neutrally charged and a bias voltage is applied to the buried well region, according to an embodiment of the present invention.
  • Fig. 161 is a schematic illustration of a memory array in which a read operation is being performed on a selected memory cell according to an embodiment of the present invention.
  • Fig. 162 is a schematic illustration of the selected memory cell in Fig.
  • Fig. 163 is a schematic illustration of a memory array in which a write
  • Fig. 164 schematically illustrates a memory cell of the array represented in Fig. 163 that is having a write "0" operation performed thereon according to an embodiment of the present invention.
  • Fig. 165 is a schematic illustration of a memory array in which a write
  • Fig. 166 schematically illustrates a memory cell of the array represented in Fig. 165 that is having a write "0" operation performed thereon according to the alternative embodiment described with regard to Fig. 165.
  • Fig. 167 is a schematic illustration of a memory array in which a write
  • Fig. 168 schematically illustrates a selected memory cell of the array of
  • Fig. 169 is a schematic illustration of a memory array in which a write
  • Fig. 170 schematically illustrates a selected memory cell of the array of
  • Fig. 169 on which the write "1" operation is being performed, and the bias conditions thereon.
  • Fig. 171 is a flow chart illustrating the operation of a memory cell
  • Fig. 172 is a flow chart illustrating operation of a memory cell according to another embodiment of the present invention.
  • Fig. 173A is a cross-section, schematic illustration of a memory cell according to an embodiment of the present invention.
  • Fig. 173B shows an exemplary array of memory cells arranged in rows and columns according to an embodiment of the present invention.
  • FIG. 173C shows an array architecture of a memory cell device according to another embodiment of the present invention. Atty. Docket: ZENO-012WO
  • Fig. 174 illustrates an operating condition for a write state "1" operation that can be carried out on a memory cell according to an embodiment of the present invention.
  • Fig. 175 illustrates an operating condition for a write state "0" operation that can be carried out on a memory cell according to an embodiment of the present invention.
  • Fig. 176 illustrates a read operation that can be carried out on a memory cell according to an embodiment of the present invention
  • Fig. 177 illustrates a holding or refresh operation that can be carried out on a memory cell according to an embodiment of the present invention
  • Figs. 178A-178B illustrate shadowing operations that can be carried out according to an embodiment of the present invention.
  • Figs. 179A-179B illustrate restore operations that can be carried out according to an embodiment of the present invention.
  • Fig. 180 illustrates resetting the trapping layer(s) of a memory cell to a predetermined state, according to an embodiment of the present invention.
  • Fig. 181A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.
  • Fig. 181B shows an array architecture of a memory cell device according to an embodiment of the present invention.
  • Figs. 182-183 illustrate cross -sectional schematic illustrations of fin-type semiconductor memory cell devices according to embodiments of the present invention
  • Fig. 184 illustrates a top view of a fin-type semiconductor memory cell device according to the embodiment shown in Fig. 182.
  • Fig. 185A illustrates states of a bi-level memory cell.
  • Fig. 185B illustrates states of a multi-level memory cell.
  • Figs. 186A through 186E illustrate an array and details of a first
  • Fig. 187 is a flowchart illustrating operation of a memory device
  • Fig. 188 illustrates a holding operation performed on an array of memory cells according to the present invention. Atty. Docket: ZENO-012WO
  • Figs. 189A and 189B illustrate the energy band diagram of a memory device according to the present invention during holding operation.
  • Figs. 190A and 190B illustrate read operations performed on an array of memory cells according to the present invention.
  • Figs. 191A and 191B illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
  • Figs. 192A and 192B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
  • Figs. 193A through 193C illustrate a shadowing operation performed on an array of memory cells according to the present invention.
  • Figs. 194A through 194C illustrate a restore operation performed on an array of memory cells according to the present invention.
  • Fig. 195 illustrates a reset operation performed on an array of memory cells according to the present invention.
  • Figs. 196A through 196R illustrate a method of manufacturing a memory cell according to the present invention.
  • FIGs. 197A through 197R illustrate an alternative method of
  • Fig. 198 illustrates a cross-sectional view of an alternative memory
  • Figs. 199A and 199B illustrate a shadowing operation performed on an array of memory cells according to the present invention.
  • Figs. 200A through 200C illustrate a restore operation performed on an array of memory cells according to the present invention.
  • Fig. 201 illustrates a reset operation performed on an array of memory cells according to the present invention.
  • Figs. 202A and 202B illustrate cross-sectional views of alternative
  • Fig. 203 illustrates an equivalent circuit representation of memory
  • Fig. 204 illustrates an exemplary array of memory devices according to the present invention. Atty. Docket: ZENO-012WO
  • Fig. 205 illustrates a holding operation performed on an array of memory cells according to the present invention.
  • Fig. 206 illustrates a read operation performed on an array of memory cells according to the present invention.
  • Figs. 207A through 207C illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
  • Figs. 208A and 208B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
  • FIGs. 209, 210A through 210B illustrate a shadowing operation
  • Figs. 21 1, 212A through 212B illustrate a restore operation performed on an array of memory cells according to the present invention.
  • Figs. 213A and 213B illustrate reset operations performed on an array of memory cells according to the present invention.
  • Figs. 214 and 215 illustrate cross-sectional views of alternative memory devices according to the present invention.
  • Fig. 216 illustrates an equivalent circuit representation of memory
  • Fig. 217 illustrates an exemplary array of memory devices according to the present invention.
  • Fig. 218 illustrates a holding operation performed on an array of memory cells according to the present invention.
  • Fig. 219 illustrates a read operation performed on an array of memory cells according to the present invention.
  • Figs. 220A, 220B, and 221 illustrate write logic-0 operations performed on an array of memory cells according to the present invention.
  • Figs. 222A and 222B illustrate write logic-1 operations performed on an array of memory cells according to the present invention.
  • Figs. 223A and 223B illustrate a shadowing operation performed on an array of memory cells according to the present invention.
  • Fig. 224 illustrates a restore operation performed on an array of memory cells according to the present invention. Atty. Docket: ZENO-012WO
  • Figs. 225A and 225B illustrate reset operations performed on an array of memory cells according to the present invention.
  • Fig. 226 is a flowchart illustrating an alternative operation of a memory device according to the present invention.
  • Fig. 227 illustrates a read operation performed on an array of memory cells according to the present invention.
  • Fig. 228 illustrates a write logic-1 operation performed on an array of memory cells according to the present invention.
  • Figs. 229A through 229C illustrate cross sectional views of alternative memory devices according to the present invention, fabricated on silicon-on- insulator (SOI) substrate.
  • SOI silicon-on- insulator
  • Figs. 230A through 230E illustrate cross-sectional views and top view of alternative memory devices according to the present invention, comprising of fin structures .
  • a “holding operation”, “standby operation” or “holding/standby operation”, as used herein, refers to a process of sustaining a state of a memory cell by maintaining the stored charge. Maintenance of the stored charge may be facilitated by applying a back bias to the cell in a manner described herein.
  • a "a multi-level write operation” refers to a process that includes an ability to write more than more than two different states into a memory cell to store more than one bit per cell.
  • a "write-then-verify" "write and verify” or “alternating write and verify” algorithm or operation refers to a process where alternating write and read operations to a memory cell are employed to verify whether a desired memory state of the memory cell has been achieved during the write operation. Atty. Docket: ZENO-012WO
  • a "read verify operation” refers to a process where a read operation is performed to verify whether a desired memory state of a memory cell has been achieved.
  • a "read while programming" operation refers to a process where simultaneous write and read operations can be performed to write a memory cell state.
  • a “back bias terminal” refers to a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor.
  • a back bias terminal is also commonly referred to as a "back gate terminal”.
  • the back bias terminal refers to the substrate terminal or the buried well terminal, depending upon the embodiment being described.
  • back bias refers to a voltage applied to a back bias terminal.
  • a "memory cell” as used herein, refers to a semiconductor memory cell comprising an electrically floating body as the data storage element.
  • a "contactless memory cell” as used herein, refers to a memory cell which does not have a contact (or contacts) forming a direct connection(s) to a control line (or control lines). Contactless memory cells are typically connected in series when formed in a string or in parallel when formed in a link.
  • a "memory string” or “string” as used herein, refers to a set of interconnected memory cells connected in series, where conductive regions at the surfaces of adjacent memory cells are shared or electrically connected. In a series connection, the same current flows through each of the memory cells.
  • a 'link refers to a set of interconnected memory cells connected in parallel, where conductive regions at the surfaces of adjacent memory cells are electrically connected. In a parallel connection, the voltage drop across each of the memory cells is the same.
  • a "memory array” or “memory cell array” as used herein, refers to a plurality of memory cells typically arranged in rows and columns. The plurality of memory cells may further be connected in strings or links within the memory array.
  • shadowing refers to a process of copying the contents of volatile memory to non-volatile memory.
  • Restore refers to a process of copying the contents of non-volatile memory to volatile memory.
  • Reset refers to a process of setting non-volatile memory to a predetermined state.
  • Periodent data as used herein, is referred to data that typically will not be changed during the operation of a system employing a memory cell device as described herein, and thus can be stored indefinitely in non-volatile memory. Examples of such "permanent data” include, but are not limited to program files, application files, music files, video files, operating systems, etc.
  • single polysilicon flash memory refers to a non-volatile
  • CMOS complementary metal oxide semiconductor
  • stacked gate flash memory refers to a non-volatile memory cell that has multiple polysilicon layers/gates, for example where a second polysilicon gate (e.g., a control gate) is stacked above a polysilicon floating gate used to store the non-volatile data (see for example Fig. 4.6 on p.197 in
  • Such stacked gate memory cells typically require dual (or more) polysilicon layer processing, where the first polysilicon layer (e.g. floating gate) is deposited and formed, followed by the formation of a second polysilicon (e.g. control gate) layer.
  • first polysilicon layer e.g. floating gate
  • second polysilicon e.g. control gate
  • the cell 50 includes a substrate 12 of a first conductivity type, such as n-type conductivity type, for example.
  • Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • the substrate 12 has a surface 14.
  • a first region 16 having a first Atty. Docket: ZENO-012WO conductivity type, such as n-type, for example, is provided in substrate 12 and which is exposed at surface 14.
  • a second region 18 having the first conductivity type is also provided in substrate 12, which is exposed at surface 14 and which is spaced apart from the first region 16.
  • First and second regions 16 and 18 are formed by an implantation process formed on the material making up substrate 12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process can be used to form first and second regions 16 and 18.
  • the floating body region 24 can be formed by an implantation process formed on the material making up substrate 12, or can be grown epitaxially.
  • Insulating layers 26 e.g. shallow trench isolation (STI)
  • Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined in an array 80 to make a memory device as illustrated in Fig. 2.
  • a gate 60 is positioned in between the regions 16 and 18, and above the surface 14.
  • the gate 60 is insulated from surface 14 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides .
  • Cell 50 further includes word line (WL) terminal 70 electrically connected to gate 60, source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18 (connected to 18 as shown, but could, alternatively, be connected to 16 when 72 is connected to 18), and substrate terminal 78 electrically connected to substrate 12.
  • WL word line
  • SL source line
  • BL bit line
  • substrate terminal 78 electrically connected to substrate 12.
  • contact to substrate region 12 could be made through a region having a first conductivity type, which is electrically connected to substrate region 12 (not shown).
  • the memory cell 50 has a p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type, as noted above.
  • a memory cell 50 has been described for example in "Scaled lT-Bulk Devices Built with CMOS 90nm Technology for Low-cost eDRAM Applications", R. Ranica, et al., pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
  • the memory cell states are represented by the charge in the floating body 24. If cell 50 has holes stored in the floating body region 24, then the memory cell 50 will have a lower threshold voltage (gate voltage where transistor is turned on) compared to when cell 50 does not store holes in floating body region 24.
  • the positive charge stored in the floating body region 24 will decrease over time due to the p-n diode leakage formed by floating body 24 and regions 16, 18, and substrate 12 and due to charge recombination.
  • a unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells 50 of the array 80.
  • the holding operation can be performed by applying a positive back bias to the substrate terminal 78 while grounding terminal 72 and/or terminal 74.
  • the positive back bias apphed to the substrate terminal will maintain the state of the memory cells 50 that it is connected to.
  • the holding operation is relatively independent of the voltage apphed to terminal 70. As shown in Fig.
  • n-p-n bipolar devices 30a and 30b formed by substrate region 12, floating body 24, and SL and BL regions 16, 18. If floating body 24 is positively charged (i.e. in a state "1"), the bipolar transistor 30a formed by SL region 16, floating body 24, and substrate region 12 and bipolar transistor 30b formed by BL region 18, floating body 24, and substrate region 12 will be turned on.
  • a fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state "1" data.
  • the efficiency of the holding operation can be enhanced by designing the bipolar device formed by substrate 12, floating region 24, and regions 16, 18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the Atty. Docket: ZENO-012WO collector current flowing out of substrate terminal 78 to the base current flowing into the floating region 24.
  • the holding operation can be performed in mass, parallel manner as the substrate terminal 78 (e.g., 78a, 78b, 78n) is typically shared by all the cells 50 in the memory array 80.
  • the substrate terminal 78 can also be segmented to allow independent control of the applied bias on the selected portion of the memory array as shown in Fig. 4A, where substrate terminal 78a, 78b is shown segmented from substrate terminal 78m, 78 ⁇ , for example. Also, because substrate terminal 78 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.
  • a periodic pulse of positive voltage can be applied to substrate terminal 78, as opposed to applying a constant positive bias, in order to reduce the power consumption of the memory cell 50.
  • the state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78).
  • Fig. 4B further shows multiplexers 40 that determine the bias applied to substrate terminal 78 where the control signal could be the clock signal 42 or as will be described later, determined by different operating modes.
  • the positive input signals could be the power supply voltage Vcc (Fig. 4B) or a different positive bias could be generated by voltage generator circuitry 44 (see Fig. 4C).
  • the holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24.
  • the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage VEB as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than VFB-
  • the bipolar action results in a hole current flowmg into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18.
  • the maximum charge VMC stored in Atty. Docket: ZENO-012WO floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in Fig. 5.
  • the increase in the maximum charge stored in the floating body 24 results in a larger memory window.
  • the holding/standby operation can also be used for multi-bit operations in memory cell 50.
  • a multi-level operation is typically used. This is done by dividing the overall memory window into different levels.
  • the different memory states are represented by different charges in the floating body 24, as described for example in "The Multistable Charge- Controlled Memory Effect in SOI Transistors at Low Temperatures", Tack et al, pp. 1373- 1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 and US 7,542,345 "Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same", each of which is hereby incorporated herein, in its entirety, by reference thereto.
  • the floating body 24 since the state with zero charge in the floating body 24 is the most stable state, the floating body 24 will, over time, lose its charge until it reaches the most stable state.
  • the difference of charge representing different states is smaller than that for a single-level operation.
  • a multi-level memory cell is more sensitive to charge loss, as less charge loss is required to change states.
  • Fig. 6 shows the floating body 24 relative net current for different floating body 24 potentials as a function of the voltage applied to substrate terminal 78 with BL, SL, and WL terminals 72, 74, and 70, grounded. " When zero voltage is applied to substrate terminal 78, no bipolar current is flowing into the floating body 24 and as a result, the stored charge will leak over time. " When a positive voltage is applied to substrate terminal 78, hole current will flow into floating body 24 and balance the junction leakage current to regions 16 and 18. The junction leakage current is determined by the potential difference between the floating body 24 and regions 16 and 18, while the bipolar current flowing into floating body 24 is determined by both the substrate terminal 78 potential and the floating body 24 potential. As indicated in Fig.
  • bias condition for the holding operation is hereby provided: zero voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, and a positive voltage is applied to the substrate terminal 78.
  • about 0.0 volts is applied to terminal 72
  • about 0.0 volts is applied to terminal 74
  • about 0.0 volts is applied to terminal 70
  • about +1.2 volts is applied to terminal 78.
  • these voltage levels may vary.
  • the charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 50. If cell 50 is in a state "1" having holes in the floating body region 24, then the memory cell will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to if cell 50 is in a state "0" having no holes in floating body region 24.
  • a sensing circuit read circuitry 90 typically connected to BL terminal 74 of memory array 80 e.g., see read circuitry 90 in Fig. 18A can then be used to determine the data state of the memory cell.
  • Examples of the read operation is described in "A Design of a Capacitorless IT-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and Highspeed Embedded Memory", and Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003 and US 7,301,803 "Bipolar reading technique for a memory cell having an electrically floating body transistor", both of which are hereby incorporated herein, in their entireties, by reference thereto.
  • An example of a sensing circuit is described in "An 18.5ns 128Mb SOI DRAM with a Floating body Cell", Ohsawa et al., pp. 458-459, 609, IEEE International Solid-State Circuits Conference, 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
  • the read operation can be performed by applying the following bias condition: a positive voltage is applied to the substrate terminal 78, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to Atty. Docket: ZENO-012WO the selected BL terminal 74 is applied to the selected WL terminal 70. The unselected BL terminals will remain at zero voltage and the unselected WL terminals will remain at zero or negative voltage. In one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to the selected terminal 74, about +1.2 volts is applied to the selected terminal 70, and about +1.2 volts is applied to terminal 78.
  • Fig. 7 shows the bias conditions for the selected memory cell 50a and unselected memory cells 50b, 50c, and 50d in memory array 80. However, these voltage levels may vary.
  • the unselected memory cells 50 during read operations are shown in Figs. 8A, 8C and 8E, with illustration of the states of the n-p-n bipolar devices 30a, 30b inherent in the cells 50 of Figs. 8A, 8C and 8E in Figs. 8B, 8D and 8F, respectively.
  • the bias conditions for memory cells 50 sharing the same row (e.g. memory cell 50b) and those sharing the same column (e.g. memory cell 50c) as the selected memory cell 50a are shown in Figs. 8A-8B and Figs. 8C-8D, respectively, while the bias condition for memory cells 50 not sharing the same row or the same column as the selected memory cell 50 (e.g. memory cell 50d) is shown in Figs. 8E-8F.
  • both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (Figs. 8A-8B). As can be seen, these cells will be at holding mode, with memory cells in state “1" and will maintain the charge in floating body 24 because the intrinsic n-p-n bipolar devices 30a, 30b will generate hole current to replenish the charge in floating body 24; while memory cells 50 in state "0" will remain in the neutral state.
  • both the SL terminal 72 and BL terminal 74 are at about Atty. Docket: ZENO-012WO
  • the holding operation does not interrupt the read operation of the memory cells 50.
  • the unselected memory cells 50 during a read operation will remain in a holding operation.
  • Fig. 10 shows an example of bias conditions for the selected and unselected memory cells 50 during a write "0" operation in memory array 80.
  • the negative bias applied to SL terminal 72 causes large potential difference between floating body 24 and region 16.
  • the hole current generated by the intrinsic n-p-n bipolar devices 30a, 30b will not be sufficient to compensate for the forward bias current of p-n diode formed by floating body 24 and junction 16.
  • FIG. l lA-1 IB An example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30a, 30b of unselected memory cells 50 during write "0" operations are illustrated in Figs. l lA-1 IB. Since the write "0" operation only involves applying a negative voltage to the SL terminal 72, the bias conditions for all the unselected cells are the same. As can be seen, Atty. Docket: ZENO-012WO the unselected memory cells will be in a holding operation, with both BL and SL terminals at about 0.0 volts. The positive back bias apphed to the substrate terminal 78 employed for the holding operation does not interrupt the write "0" operation of the selected memory cells. Furthermore, the unselected memory cells remain in the holding operation.
  • the write "0" operation referred to above has a drawback in that all memory cells 50 sharing the same SL terminal will be written to simultaneously and as a result, this does not allow individual bit writing, i.e., writing to a single cell 50 memory bit.
  • write "0" is first performed on all the memory cells, followed by write "1" operations on a selected bit or selected bits.
  • An alternative write "0" operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, and zero or positive voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage apphed to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage apphed to the BL terminal 74, the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24.
  • the apphed potential can be optimized as follows: if the floating body 24 potential of state "1" is referred to as VFBI, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VEB I 2 while -VEBI/2 is apphed to BL terminal 74. A positive voltage can be apphed to SL terminal 72 to further reduce the undesired write "0" disturb on other memory cells 50 in the memory array. The unselected cells will remain at holding state, i.e. zero or negative voltage apphed to WL terminal 70 and zero voltage apphed to BL terminal 74.
  • the following bias conditions are apphed to the selected memory cell 50a: a potential of about 0.0 volts is applied to terminal 72, a potential of about -0.2 volts is apphed to terminal 74, a potential of about +0.5 volts is apphed to terminal 70, and about +1.2 volts is applied to terminal 78; while about 0.0 volts is apphed to terminal 72, about 0.0 Atty. Docket: ZENO-012WO volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78 of the unselected memory cells.
  • Fig. 12 shows the bias conditions for the selected and unselected memory cells in memory array 80. However, these voltage levels may vary.
  • the unselected memory cells 50 during write "0" operations are shown in Figs. 13C-13H.
  • the bias conditions for memory cells sharing the same row e.g. memory cell 50b
  • the bias conditions for memory cells sharing the same column e.g. memory cell 50c
  • the bias conditions for memory cells not sharing the same row or the same column e.g. memory cell 50d
  • the bias conditions for memory cells not sharing the same row or the same column e.g. memory cell 50d
  • both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (Figs. 13C and 13D).
  • the floating body 24 potential of these cells will also increase due to capacitive coupling from the WL terminal 70.
  • the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 and junctions 16 and 18 is greater than the base hole current generated by the n-p-n bipolar device 30 formed by substrate 12, floating body 24, and junctions 16 and 18.
  • the floating body 24 potential will return to the initial state "1" equihbrium potential.
  • the hole current of the n-p-n bipolar device 30b formed by substrate 12, floating body 24, and region 18 will also increase as a result of the increase in potential difference between the substrate 12 and region 18 (the collector and emitter terminals, respectively).
  • the floating body 24 of memory cells in state “1” will also remain positively charged (i.e., in state "1").
  • both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see Figs. 13G and 13H). These cells will thus be in a holding mode and continue a holding operation, with memory cells in state “1" maintaining the charge in floating body 24 because the intrinsic n-p-n bipolar device 30 will generate hole current to replenish the charge in floating body 24; while memory cells in state "0" will remain in the neutral state.
  • the present invention provides for a write "0" operation that allows for bit selection.
  • the positive bias applied to the substrate terminal 78 of the memory cells 50 is necessary to maintain the states of the unselected cells 50, especially those sharing the same row and column as the selected cells 50, as Atty. Docket: ZENO-012WO the bias conditions can potentially alter the states of the memory cells 50 without the intrinsic bipolar devices 30a, 30b (formed by substrate 12, floating body 24, and regions 16, 18, respectively) re-establishing the equilibrium condition. Also, the positive bias applied to the substrate terminal 78 employed for the holding operation does not interrupt the write "0" operation of the selected memory cell(s).
  • a write "1" operation can be performed on memory cell 50 through impact ionization or band-to-band tunneling mechanism, as described for example in "A Design of a Capacitorless IT-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory", Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
  • GIDL Gate-Induced Drain Leakage
  • FIG. 14 and Figs. 15A-15B An example of the bias condition of the selected memory cell 50 under band-to-band tunneling write "1" operation is illustrated in Fig. 14 and Figs. 15A-15B.
  • the negative bias applied to the WL terminal 70 and the positive bias applied to the BL terminal 74 results in hole injection to the floating body 24 of the selected memory cell 50.
  • the positive bias applied to the substrate terminal 78 maintains the resulting positive charge on the floating body 24 as discussed above.
  • the unselected cells 50 remain at the holding mode, with zero or negative voltage applied to the unselected WL terminal 70 and zero voltage is applied to the unselected BL terminal 74 to maintain the holding operation (holding mode).
  • the following bias conditions are applied to the selected memory cell 50a: a potential of about 0.0 volts is applied to terminal 72, a potential of about + 1.2 volts is applied to terminal 74, a potential of about -1.2 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78; and the following bias conditions are applied to the unselected memory cells 50: about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, and about +1.2 volts is applied to terminal 78.
  • Fig. 14 shows the bias conditions for the selected and unselected memory cells in memory array 80. However, these voltage levels may vary. Atty. Docket: ZENO-012WO
  • Figs. 15C-15H The unselected memory cells during write "1" operations are shown in Figs. 15C-15H.
  • the bias conditions for memory cells sharing the same row e.g. memory cell 50b
  • the bias conditions for memory cells sharing the same column as the selected memory cell 50a e.g. memory cell 50c
  • Figs. 15E-15F The bias conditions for memory cells 50 not sharing the same row or the same column as the selected memory cell 50a (e.g. memory cell 50d) are shown in Figs. 15G-15H.
  • both the SL terminal 72 and BL terminal 74 are at about 0.0 volts, with the WL terminal 70 at zero or negative voltage (Figs. 15C-15D). Comparing with the holding operation bias condition, it can be seen that cells sharing the same row (i.e. the same WL terminal 70) are in holding mode. As a result, the states of these memory cells will remain unchanged.
  • both the SL terminal 72 and BL terminal 74 are at about 0.0 volts (see Figs. 15G-15H). As can be seen, these cells will be in a holding operation (holding mode), where memory cells in state “1" will maintain the charge in floating body 24 because the intrinsic n-p-n bipolar devices 30a, 30b will generate hole current to replenish the charge in floating body 24; while memory cells in state "0" will remain in the neutral state.
  • a multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 50, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 50, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
  • a positive voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, a negative voltage is applied to WL terminal 70, and a positive voltage is applied to the substrate terminal 78.
  • Positive voltages of different amplitude are applied to BL terminal 74 to write different states to floating body 24. This results in different floating body potentials 24 corresponding to the different positive voltages or the number of positive voltage pulses that have been applied to BL terminal 74.
  • substrate terminal 78 By applying positive voltage to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24.
  • the write operation is performed by applying the following bias condition: a potential of about 0.0 volts is applied to terminal 72, a potential of about -1.2 volts is applied to terminal 70, and about + 1.2 volts is applied to terminal 78, while the potential applied to BL terminal 74 is incrementally raised. For example, in one non- limiting embodiment 25 millivolts is initially applied to BL terminal 74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e., cell current corresponding to whichever of 00, 01, 10 or 1 1 is desired is achieved), then the multi write operation is commenced.
  • the desired state i.e., cell current corresponding to whichever of 00, 01, 10 or 1 1 is desired is achieved
  • the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved. However, the voltage levels described may vary. The write operation is followed by a read operation to verify the memory state. Atty. Docket: ZENO-012WO
  • the write-then-verify algorithm is inherently slow since it requires multiple write and read operations.
  • the present invention provides a multi-level write operation that can be performed without alternate write and read operations. This is accomplished by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a positive voltage to WL terminal 70, and a positive voltage to substrate terminal 78 of the selected memory cells.
  • the unselected memory cells will remain in holding mode, with zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74. These bias conditions will result in a hole injection to the floating body 24 through impact ionization mechanism.
  • the state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 (Figs.
  • the cell current measured in the source line direction is a cumulative cell current of all memory cells 50 which share the same source line 72 (see Figs. 16A-16C). As a result, only one memory cell 50 sharing the same source line 72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selected memory cell 50.
  • the potential of the floating body 24 increases over time as these bias conditions result in hole injection to floating body 24 through an impact ionization mechanism.
  • the voltage applied to BL terminal 74 can be removed.
  • the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
  • Figs. 16A-16C also show a reference generator circuit 92, which serves to generate the initial cumulative cell current of the memory cells 50 sharing the same source line 72 being written.
  • the cumulative charge of the initial state for all memory cells 50 sharing the same source line 72 can be stored in a capacitor 94 (see Fig. 16B).
  • Transistor 96 is turned on when charge is to be written into or read from capacitor 94.
  • a reference cell 50R (Fig. 16C) similar to a memory cell 50 can also be used to store the initial state. Atty. Docket: ZENO-012WO
  • a write operation is performed on the reference cell 50R using the cumulative cell current from the source Hne 72.
  • Transistor 96 is turned on when a write operation is to be performed on the reference cell 50R.
  • a positive bias is also applied to the substrate of the reference cell to maintain its state.
  • the size of the reference cell 50R needs to be configured such that it is able to store the maximum cumulative charge of all the memory cells 50, i.e. when all of the memory cells 50 sharing the same source Hne 72 are positively charged.
  • a multi-level write operation using an impact ionization mechanism can be performed by ramping the write current appHed to BL terminal 74 instead of ramping the BL terminal 74 voltage.
  • a multi-level write operation can be performed through a band-to-band tunneHng mechamsm by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a negative voltage to WL terminal 70, and zero or positive voltage to substrate terminal 78 of the selected memory cells 50.
  • the unselected memory cells 50 wiU remain in holding mode, with zero or negative voltage appHed to WL terminal 70 and zero voltage appHed to BL terminal 74.
  • multiple BL terminals 74 can be simultaneously selected to write multiple ceUs in paraHel. The potential of the floating body 24 of the selected memory cell(s) 50 will increase as a result of the band-to-band tunneling mechamsm.
  • the state of the selected memory cell(s) 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory ceU, the voltage applied to BL terminal 74 can be removed. If positive voltage is appHed to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
  • the multi-level write operation using band-to-band tunneHng mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage appHed to BL terminal 74.
  • a read while programming operation can be performed by monitoring the change in cell current in the bit line direction through a reading circuitry 90 coupled to the bit line 74 as shown in Fig. 18A.
  • Reference cells 50R representing different memory states are used to verify the state of the write operation
  • the reference cells 50R can be configured through a write-then-verify operation for example when the memory device is first powered up.
  • the resulting cell current of the memory cell 50 being written is compared to the reference cell 50R current by means of the read circuitry 90.
  • the reference cell 50R is also being biased at the same bias conditions applied to the selected memory cell 50 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of the reference cell 50R.
  • the voltage at the bit line 74 can be sensed instead of the cell current.
  • the bit line voltage can be sensed for example using a voltage sensing circuitry (see Fig. 18B) as described in "VLSI Design of Non-Volatile Memories", Campardo G. et al., 2005, which is hereby incorporated herein, in its entirety, by reference thereto.
  • the bias conditions described above are applied both to the selected memory cell 50 and to the "01" reference cell 50R: zero voltage is applied to the source line terminal 72, a positive voltage is applied to the substrate terminal 78, a positive voltage is applied to the WL terminal 70 (for the impact ionization mechanism), while the BL terminal 74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of the reference cell 50R does not change. Atty. Docket: ZENO-012WO
  • a periodic pulse of positive voltage can be applied to substrate terminal 78, as opposed to applying a constant positive bias, to reduce the power consumption of the memory cell 50.
  • the memory cell 50 operations during the period where the substrate terminal 78 is being grounded are now briefly described. During the period when the substrate terminal 78 is grounded, the memory cells 50 connected to a ground substrate terminal 78 are no longer in holding mode. Therefore the period during which the substrate terminal is grounded must be shorter than the charge retention time period of the floating body, to prevent the state of the floating body from changing when the substrate terminal is grounded.
  • the charge lifetime (i.e., charge retention time period) of the floating body 24 without use of a holding mode has been shown to be on the order of milliseconds, for example, see "A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16- nm Technology Node and Beyond", Ban et al., pp. 92-92, Symposium on VLSI Technology, 2008, which is hereby incorporated herein, in its entirety, by reference thereto.
  • the state of the memory cell 50 can be maintained by refreshing the charge stored in floating body 24 during the period over which the positive voltage pulse is applied to the back bias terminal (i.e., substrate terminal 78).
  • a read operation can be performed by applying the following bias conditions: zero voltage is applied to the substrate terminal 78, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70.
  • the unselected BL terminals 74 will remain at zero voltage and the unselected WL terminals 70 will remain at zero or negative voltage.
  • a positive voltage can Atty. Docket: ZENO-012WO be applied to the unselected substrate terminals 78.
  • about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to the selected terminal 74, about +1.2 volts is applied to the selected terminal 70, and about 0.0 volts is applied to terminal 78.
  • the unselected terminals 74 remain at 0.0 volts and the unselected terminals 70 remain at 0.0 volts.
  • the unselected terminals 78 (in the case where the substrate terminals 78 are segmented as in Figs. 4A and 4B) can remain at +1.2 volts (see Fig. 19).
  • the read operation is carried out over a time period on the order of nanoseconds, it is of a much shorter duration than the charge lifetime (charge retention time period) of the floating body 24 unassisted by a holding operation. Accordingly, the performance of a read operation does not affect the states of the memory cells connected to the terminal 78 as it is momentarily (on the order of nanoseconds) grounded.
  • a write "0" operation of the cell 50 can be performed by applying the following bias conditions: a negative bias is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, and zero voltage is applied to substrate terminal 78.
  • the SL terminal 72 for the unselected cells will remain grounded. If the substrate terminals 78 are segmented (as for example shown in Figs. 4A-4C), a positive voltage can be applied to the unselected substrate terminals 78. Under these conditions, the p-n junction between 24 and 16 is forward-biased, evacuating any holes from the floating body 24. In one particular non-limiting embodiment, about -2.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 70, and about 0.0 volts is applied to terminal 78.
  • the unselected terminals 78 (in the case where the substrate terminals 78 are segmented as in Figs. 4A and 4B) can remain at +1.2 volts. With the substrate terminal 78 being grounded, there is no bipolar hole current flowing to the floating body 24. As a result, the write "0" operation will also require less time. Because the write "0" operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floating body 24, unassisted by a holding operation. Accordingly, the write "0" operation does not affect the states of the unselected memory cells 50 connected to the terminal 78 being momentarily grounded to perform the write "0" operation.
  • the bias conditions applied to the Atty. Docket: ZENO-012WO memory array 80 are shown in Fig. 20. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • FIG. 21 An example of the bias conditions for an alternative write "0" operation which allows for individual bit write is shown in Fig. 21.
  • the following conditions are applied to selected memory cell 50: a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, and zero voltage to substrate terminal 78.
  • the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70.
  • the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24.
  • the applied potential can be optimized as follows: if the floating body 24 potential of state “1" is referred to as VFBI, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V BI/2 while -VFBI/2 is applied to BL terminal 74. A positive voltage can be applied to SL terminal 72 to further reduce the undesired write "0" disturb on other memory cells 50 in the memory array that do not share the same common SL terminal 72 as the selected memory cell. The unselected cells will remain at holding state, i.e.
  • the write "0" operation is brief, occurring over a time period on the order of nanoseconds, it is of much shorter duration than the charge retention time period of the floating body 24, unassisted by a holding operation. Accordingly, the write "0" operation does not affect the states of the unselected memory cells 50 connected to the terminal 78 being momentarily grounded to perform the write "0" operation.
  • a potential of about 0.0 volts is applied to terminal 72a, a potential of about -0.2 volts is Atty.
  • ZENO-012WO applied to terminal 74a, a potential of about +0.5 volts is applied to terminal 70a, and about 0.0 volts is applied to terminal 78a; while about 0.0 volts is applied to terminal 72n and the other SL terminals not connected to the selected cell 50a, about 0.0 volts is applied to terminal 74n and the other BL terminals not connected to the selected cell 50a, about 0.0 volts is applied to terminal 70n and the other WL terminals not connected to the selected cell 50a, and about +1.2 volts is applied to terminal 78n and the other substrate terminals not connected to the selected cell 50a.
  • these voltage levels may vary.
  • FIG. 22 An example of the bias conditions applied to the memory array 80 under a band-to-band tunneling write "1" operation to cell 50a is shown in Fig. 22, where a negative bias is applied to WL terminal 70a, a positive bias is applied to BL terminal 74a, zero voltage is applied to SL terminal 72a, and zero voltage is applied to substrate terminal 78a.
  • the negative bias applied to the WL terminal 70a and the positive bias applied to the BL terminal 74a will result in hole injection to the floating body 24 of the selected memory cell 50a.
  • the unselected cells 50 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminals 70 ( in this case, terminal 70n and any other WL terminal 70 not connected to selected cell 50a) and zero voltage is applied to the unselected BL terminals 74 ( in this case, terminals 74b, 74n and any other BL terminal 74 not connected to selected cell 50a) and positive voltage applied to unselected substrate terminals 78 (in the case the substrate terminals 78 are segmented as for example shown in Figs. 4A and 4B; and, in Fig. 22, to terminals 78n and any other substrate terminals 78 not connected to selected cell 50a).
  • the following bias conditions are applied to the selected memory cell 50a: a potential of about 0.0 volts is applied to terminal 72a, a potential of about +1.2 volts is applied to terminal 74a, a potential of about -1.2 volts is applied to terminal 70a, and about 0.0 volts is applied to terminal 78a; while about 0.0 volts is applied to the unselected terminals 72 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals 74 (defined in the preceding paragraph), about 0.0 volts is applied to unselected terminals 70 (defined in the preceding paragraph), and about +1.2 volts is applied to unselected substrate terminals 78 Atty. Docket: ZENO-012WO
  • Fig. 23A shows another embodiment of a memory cell 150 according to the present invention.
  • the cell 150 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example.
  • Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • the substrate 12 has a surface 14.
  • a first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and is exposed at surface 14.
  • a second region 18 having the second conductivity type is also provided in substrate 12, and is also exposed at surface 14. Second region 18 is spaced apart from the first region 16, as shown.
  • First and second regions 16 and 18 may be formed by an implantation process on the material making up substrate 12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process may be used to form first and second regions 16 and 18.
  • a buried layer 22 of the second conductivity type is also provided in the substrate 12, buried in the substrate 12, as shown. Buried layer 22 may also be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially.
  • a floating body region 24 of the substrate 12 having a first conductivity type, such as a p-type conductivity type, is bounded by surface, first and second regions 16,18, insulating layers 26 and buried layer 22.
  • Insulating layers 26 e.g., shallow trench isolation (STI)
  • STI shallow trench isolation
  • Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined in an array 180 to make a memory device as illustrated in Fig. 24.
  • a gate 60 is positioned in between the regions 16 and 18, and above the surface 14.
  • the gate 60 is insulated from surface 14 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides . Atty. Docket: ZENO-012WO
  • Cell 150 further includes word line (WL) terminal 70 electrically connected to gate 60, source line (SL) terminal 72 electrically connected to one of regions 16 and 18 (connected to 16 as shown, but could, alternatively, be connected to 18), bit line (BL) terminal 74 electrically connected to the other of regions 16 and 18, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to substrate 12 at a location beneath buried layer 22.
  • WL word line
  • SL source line
  • BL bit line
  • BW buried well
  • Contact to buried well region 22 could be made through region 20 having a second conductivity type, which is electrically connected to buried well region 22, while contact to substrate region 12 could be made through region 28 having a first conductivity type, which is electrically connected to substrate region 12, as shown in Fig. 23B
  • the memory cell 150 may be provided with p- type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type.
  • n-p-n bipolar devices 130a, 130b formed by buried well region 22, floating body 24, and SL and BL regions 16, 18.
  • the memory cell operations will be described as follows. As will be seen, the operation principles of this embodiment of the memory cell 150 will follow the descriptions above, where the bias applied on the n-type substrate terminal 78 for the above described memory cell 50 is now applied to the n-type buried well terminal 76 of cell 150.
  • the p-type substrate 12 of the current embodiment of the memory cell 150 will be grounded, reverse biasing the p-n junction between substrate 12 and buried well layer 22, thereby preventing any leakage current between substrate 12 and buried well layer 22.
  • a holding operation can be performed by applying a positive back bias to the BW terminal 76 while grounding terminal 72 and/or terminal 74. If floating body 24 is positively charged (i.e. in a state "1"), the bipolar transistor formed by SL region 16, floating body 24, and buried well region 22 and bipolar transistor formed by BL region 18, floating body 24, and buried well region 22 will be turned on.
  • a fraction of the bipolar transistor current will then flow into floating region 24 (usually referred to as the base current) and maintain the state "1" Atty. Docket: ZENO-012WO data.
  • the efficiency of the holding operation can be enhanced by designing the bipolar devices 130a, 130b formed by buried well layer 22, floating region 24, and regions 16/18 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of BW terminal 76 to the base current flowing into the floating region 24.
  • the holding operation can be performed in mass, parallel manner as the BW terminal 76 (functioning as back bias terminal) is typically shared by all the cells 150 in the memory array 180, or at least by multiple cells 150 in a segment of the array 180.
  • the BW terminal 76 can also be segmented to allow independent control of the applied bias on a selected portion of the memory array 180. Also, because BW terminal 76 is not used for memory address selection, no memory cell access interruption occurs due to the holding operation.
  • An example of the bias conditions applied to cell 150 to carry out a holding operation includes: zero voltage is applied to BL terminal 74, zero voltage is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, a positive voltage is applied to the BW terminal 76, and zero voltage is applied to substrate terminal 78.
  • about 0.0 volts is applied to terminal 72
  • about 0.0 volts is applied to terminal 74
  • about 0.0 volts is applied to terminal 70
  • +1.2 volts is applied to terminal 76
  • about 0.0 volts is applied to terminal 78.
  • these voltage levels may vary.
  • a read operation can be performed on cell 150 by applying the following bias conditions: a positive voltage is applied to the BW terminal 76, zero voltage is applied to SL terminal 72, a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70, while zero voltage is applied to substrate terminal 78.
  • the unselected BL terminals 74 e.g., 74b, 74n
  • the unselected WL terminals 70 e.g., 70n and any other WL Atty.
  • ZENO-012WO terminals 70 not connected to selected cell 150a will remain at zero or negative voltage.
  • about 0.0 volts is applied to terminal 72
  • about +0.4 volts is applied to the selected terminal 74a
  • about +1.2 volts is applied to the selected terminal 70a
  • about +1.2 volts is applied to terminal 76
  • about 0.0 volts is applied to terminal 78, as illustrated in Fig. 26.
  • the unselected terminals 74 remain at 0.0 volts and the unselected terminal 70 remain at 0.0 volts as illustrated in Fig. 26.
  • these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
  • the unselected memory cells 150b, 150c and 150d
  • the holding operation does not interrupt the read operation of the selected memory cell 150a.
  • a negative bias is applied to SL terminal 72, zero or negative voltage is applied to WL terminal 70, zero or positive voltage is applied to BW terminal 76, and zero voltage is applied to substrate terminal 78.
  • the SL terminal 72 for the unselected cells 150 that are not commonly connected to the selected cell 150a will remain grounded. Under these conditions, the p-n junctions (junction between 24 and 16 and between 24 and 18) are forward-biased, evacuating any holes from the floating body 24. In one particular non-limiting embodiment, about -2.0 volts is applied to terminal 72, about -1.2 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78. However, these voltage levels may vary, while mamtaining the relative relationships between the charges applied, as described above.
  • the holding operation does not interrupt the write "0" operation of the memory cells. Furthermore, the unselected memory cells will remain in holding operation during a write "0" operation.
  • An alternative write "0" operation which, unlike the previous write "0" operation described above, allows for individual bit write, can be performed by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, zero or positive voltage to BW terminal 76, and zero voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70.
  • the applied bias to selected WL terminal 70 and selected BL terminal 74 can potentially affect the states of the unselected memory cells 150 sharing the same WL or BL terminal as the selected memory cell 150.
  • the applied potential can be optimized as follows: If the floating body 24 potential of state "1" is referred to as VFBI, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VFBI/2 while -VFB I/2 is applied to BL terminal 74.
  • a positive voltage can be applied to SL terminal 72 to further reduce the undesired write "0" disturb on other memory cells 150 in the memory array.
  • the unselected cells will remain at holding state, i.e. zero or negative voltage applied to WL terminal 70 and zero voltage applied to BL terminal 74.
  • the unselected cells 150 not sharing the same WL or BL terminal as the selected cell Atty. Docket: ZENO-012WO
  • a potential of about 0.0 volts is applied to terminal 72, a potential of about -0.2 volts is applied to terminal 74, a potential of about +0.5 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78.
  • about 0.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about 0.0 volts is applied to terminal 70, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78.
  • Fig. 27 shows the bias conditions for the selected and unselected memory cells 150 in memory array 180. However, these voltage levels may vary.
  • FIGs. 28A-28B An example of the bias conditions applied to a selected memory cell 150 during a write "0" operation is illustrated in Figs. 28A-28B.
  • FIGs. 28C-28H An example of the bias conditions applied to the unselected memory cells 150 during write "0" operations are shown in Figs. 28C-28H.
  • the bias conditions for unselected memory cells 150 sharing the same row as selected memory cell 150a are shown in Figs. 28C-28D.
  • the bias conditions for unselected memory cells 150 sharing the same column as selected memory cell 150a e.g. memory cell 150c in Fig. 27
  • Figs. 28E-28H The bias conditions for unselected memory cells 150 not sharing the same row or the same column as the selected memory cell 150a (e.g. memory cell 150d in Fig. 27) are shown in Figs. 28G-28H.
  • the positive back bias applied to the BW terminal 76 of the memory cells 150 is necessary to maintain the states of the unselected cells 150, especially those sharing the same row or column as the selected cell 150a, as the bias condition can potentially alter the states of the memory cells 150 without the intrinsic bipolar device 130 (formed by buried well region 22, floating body 24, and regions 16, 18) re-estabhshing the equihbrium condition. Furthermore, the holding operation does not interrupt the write "0" operation of the memory cells 150. Atty. Docket: ZENO-012WO
  • a write "1" operation can be performed on memory cell 150 through an impact ionization mechanism or a band-to-band tunneling mechanism, as described for example in "A Design of a Capacitorless IT-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory", Yoshida et al., pp. 913-918, International Electron Devices Meeting, 2003, which was incorporated by reference above.
  • GIDL Gate-Induced Drain Leakage
  • FIG. 29 An example of bias conditions applied to selected memory cell 150a under a band-to-band tunneling write "1" operation is further elaborated and is shown in Fig. 29.
  • the negative bias applied to the WL terminal 70a and the positive bias applied to the BL terminal 74a will result in hole injection to the floating body 24.
  • the positive bias applied to the BW terminal 76a will maintain the resulting positive charge on the floating body 24 as discussed above.
  • the unselected cells 150 will remain at the holding mode, with zero or negative voltage applied to the unselected WL terminal 70 (in Fig. 27, 70n and all other WL terminals 70 not connected to cell 150a) and zero voltage is applied to the unselected BL terminal 74b, 74n and all other BL terminals 74 not connected to cell 150a).
  • the positive bias applied to the BW terminal 76 employed for the holding operations does not interrupt the write "1 " operation of the selected memory cell(s). At the same time, the unselected memory cells 150 will remain in a holding operation during a write "1" operation on a selected memory cell 150.
  • a multi-level operation can also be performed on memory cell 150.
  • a holding operation to maintain the multi-level states of memory cell 50 is described with reference to Fig. 6.
  • the relationship between the floating body 24 current for different floating body 24 potentials as a function of the BW terminal 76 potential (Fig. 6B) is similar to that of floating body 24 current as a function of the substrate terminal 78 potential (Fig. 6A).
  • the current flowing into floating body 24 is balanced by the junction leakage between floating body 24 and regions 16 and 18.
  • the different floating body 24 potentials represent different charges used to represent different states of memory cell 150. This shows that different memory states can be maintained by using the holding/standby operation described here.
  • a multi-level write operation without alternate write and read operations on memory cell 150 is now described. To perform this operation, zero voltage is applied to SL terminal 72, a positive voltage is applied to WL terminal 70, a positive voltage (back bias) is applied to BW terminal 76, and zero voltage is applied to substrate terminal 78, while the voltage of BL terminal 74 is ramped up. These bias conditions will result in a hole injection to the floating body 24 through an impact ionization mechanism.
  • the state of the memory cell 150 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source line 72.
  • the cell current measured in the source line direction is a cumulative cell current of all memory cells 150 which share the same source line 72 (e.g. see Figs. 16A-16C for examples of monitoring cell current in the source line direction.
  • the same monitoring scheme can be applied to memory array 80 as well as memory array 180). As a result, only one memory cell 150 sharing the same source line 72 can be written. This ensures that the change in the cumulative cell current is a result of the write operation on the selected memory cell 150.
  • Fig. 17 shows the resulting increase of the floating body potential 24 over time.
  • the multi-level write operation using impact ionization mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.
  • a multi-level write operation can be performed through a band-to-band tunneling mechanism by ramping the voltage Atty. Docket: ZENO-012WO applied to BL terminal 74, while applying zero voltage to SL terminal 72, a negative voltage to WL terminal 70, a positive voltage to BW terminal 76, and zero voltage to substrate terminal 78.
  • the potential of the floating body 24 will increase as a result of the band-to-band tunneling mechanism.
  • the state of the memory cell 50 can be simultaneously read for example by monitoring the change in the cell current through a read circuitry 90 coupled to the source hne 72.
  • the voltage applied to BL terminal 74 can be removed. If positive voltage is applied to substrate terminal 78, the resulting floating body 24 potential is maintained through base hole current flowing into floating body 24. In this manner, the multi-level write operation can be performed without alternate write and read operations.
  • the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage applied to BL terminal 74.
  • a read while programming operation can be performed by monitoring the change in cell current in the bit line 74 direction (where bit hne current equals SL current plus BW current) through a reading circuitry 90 coupled to the bit line 74, for example as shown in Fig. 18A.
  • bit hne current equals SL current plus BW current
  • the voltage at the bit hne 74 can be sensed, rather than sensing the cell current.
  • the bit line voltage can be sensed, for example, using a voltage sensing circuitry, see Fig. 18B.
  • Figs. 30 and 31 show another embodiment of the memory cell 50 described in this invention.
  • cell 50 has a tin structure 52 fabricated on substrate 12 having a first conductivity type (such as n-type conductivity type) so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicularly to, and above the top surface of the substrate 12.
  • Fin structure 52 includes first and second regions 16, 18 having the first conductivity type.
  • the floating body Atty. Docket: ZENO-012WO region 24 is bounded by the top surface of the fin 52, the first and second regions 16, 18 and insulating layers 26 (insulating layers 26 can be seen in the top view of Fig. 34).
  • Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined to make a memory device (array 80).
  • the floating body region 24 is conductive having a second conductivity type (such as p-type conductivity type) and may be formed through an ion implantation process or may be grown epitaxially.
  • Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • Memory cell device 50 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in Fig. 30.
  • gates 60 can enclose three sides of the floating substrate region 24 as shown in Fig. 31.
  • Gates 60 are insulated from floating body 24 by insulating layers 62. Gates 60 are positioned between the first and second regions 16, 18, adjacent to the floating body 24.
  • Device 50 includes several terminals: word fine (WL) terminal 70, source fine (SL) terminal 72, bit line (BL) terminal 74, and substrate terminal 78.
  • Terminal 70 is connected to the gate 60.
  • Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18.
  • terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16.
  • Terminal 78 is connected to substrate 12.
  • Figs. 32 and 33 show another embodiment of memory cell 150 described in this invention.
  • cell 150 has a fin structure 52 fabricated on substrate 12, so as to extend from the surface of the substrate to form a three- dimensional structure, with fin 52 extending substantially perpendicularly to, and above the top surface of the substrate 12.
  • Fin structure 52 is conductive and is built on buried well layer 22. Region 22 may be formed by an ion implantation process on the material of substrate 12 or grown epitaxially. Buried well layer 22 insulates the floating substrate region 24, which has a first conductivity type (such as p-type conductivity type), from the bulk substrate 12.
  • Fin structure 52 includes first and second regions 16, 18 having a second conductivity type (such as n-type conductivity type).
  • the floating body region 24 is bounded by the top surface of the fin 52, the first and second regions Atty. Docket: ZENO-012WO
  • Insulating layers 26 insulate cell 150 from neighboring cells 150 when multiple cells 150 are joined to make a memory device.
  • Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • Memory cell device 150 further includes gates 60 on two opposite sides of the floating substrate region 24 as shown in Fig. 32.
  • gates 60 can enclose three sides of the floating substrate region 24 as shown in Fig. 33.
  • Gates 60 are insulated from floating body 24 by insulating layers 62. Gates 60 are positioned between the first and second regions 16, 18, adjacent to the floating body 24.
  • Device 150 includes several terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74, buried well (BW) terminal 76 and substrate terminal 78.
  • Terminal 70 is connected to the gate 60.
  • Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18.
  • terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16.
  • Terminal 76 is connected to buried layer 22 and terminal 78 is connected to substrate 12.
  • Fig. 34 illustrates the top view of the memory cells 50/150 shown in
  • Tack describes obtaining more than two states in the floating body of a standard MOSFET built in SOI by manipulating the "back gate” - a conductive layer below the bottom oxide (BOX) of the silicon tub the MOSFET occupies.
  • Okhonin-2 discloses attaining more than two voltage states in the floating body utilizing the intrinsic bipolar junction transistor (BJT) formed between the two source/drain regions of the standard MOSFET to generate read and write currents.
  • BJT intrinsic bipolar junction transistor
  • Yoshida and Okhonin-3 disclose a method of generating a read current from a standard MOSFET floating body memory cell manufactured in SOI-CMOS processes.
  • Okhonin-3 describes using the intrinsic BJT transistor inherent in the standard MOSFET structure to generate the read current.
  • Ohsawa-2 discloses a detailed sensing scheme for use with standard MOSFET floating body memory cells implemented in both SOI and standard bulk silicon.
  • Writing a logic-0 to a floating body DRAM cell known in the art is straight forward. Either the source line or the bit line is pulled low enough to forward bias the junction with the floating body removing the hole charge, if any.
  • Writing a logic- 1 typically may be accomplished using either a band-to- band tunneling method (also known as Gate Induced Drain Leakage or GIDL) or an impact ionization method
  • Yoshida A method of writing a logic- 1 through a gate induced band-to-band tunneling mechanism, as described for example in Yoshida.
  • the general approach in Yoshida is to apply an appropriately negative voltage to the word line (gate) terminal of the memory cell while applying an appropriately positive voltage to the bit line terminal (drain) and grounding the source line terminal (source) of the selected memory cell.
  • the negative voltage on WL terminal and the positive voltage on BL terminal creates a strong electric field between the drain region of the MOSFET transistor and the floating body region in the proximity of the gate (hence the "gate induced” portion of GIDL) in the selected memory cell.
  • the electrons which tunnel across the energy band become the drain leakage current (hence the "drain leakage" portion of GIDL), while the holes are inj ected into floating body region 24 and become the hole charge that creates the logic- 1 state.
  • This process is well known in the Atty. Docket: ZENO-012WO art and is illustrated in Yoshida (specifically Figs. 2 and 6 on page 3 and Fig. 9 on page 4).
  • Lin A New IT DRAM Cell with Enhanced Floating Body Effect
  • Lin and Chang pp. 23-27, IEEE International Workshop on Memory Technology, Design, and Testing, 2006, (“Lin”) which is incorporated in its entirety by reference herein.
  • the general approach in Lin is to bias both the gate and bit line (drain) terminals of the memory cell to be written at a positive voltage while grounding the source hne (source). Raising the gate to a positive voltage has the effect of raising the voltage potential of the floating body region due to capacitive coupling across the gate insulating layer.
  • the voltage across the reversed biased p-n junction between the floating body (base) and the drain (collector) will cause a small current to flow across the junction.
  • Some of the current will be in the form of hot carriers accelerated by the electric field across the junction. These hot carriers will collide with atoms in the semiconductor lattice which will generate hole-electron pairs in the vicinity of the junction.
  • the electrons will be swept into the drain (collector) by the electric field and become bit line (collector) current, while the holes will be swept into the floating body region, becoming the hole charge that creates the logic- 1 state.
  • the layer of material under the floating body cells is selectively etched away and replaced with Atty. Docket: ZENO-012WO insulator creating an SOI type of effect.
  • DSM Double SONOS Memory
  • J_Kim Very Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application
  • J. Kim et al. pp. 163-164, Symposium of VLSI Technology, 2010,
  • J_Kim the floating body is bounded by a gate on two sides with a source region above and a buried drain region below.
  • the drain is connected to a tap region, which allows a connection between a conductive plug at the surface to the buried drain region.
  • Widjaja describes a standard lateral MOSFET floating body DRAM cell realized in bulk sihcon with a buried well and a substrate which forms a vertical sihcon controlled rectifier (SCR) with a P1-N2-P3-N4 formed by the substrate, the buried well, the floating body, and the source (or drain) region of the MOSFET respectively.
  • SCR vertical sihcon controlled rectifier
  • This structure behaves like two bipolar junction transistor (BJT) devices coupled together - one an n-p-n (N2-P3-N4) and one a p-n-p (P3-N2-P1) - which can be manipulated to control the charge on the floating body region (P3).
  • BJT bipolar junction transistor
  • MOSFET device 100 An exemplary standard metal-oxide-semiconductor field effect transistor (MOSFET) device 100 is shown in Fig. 90A.
  • MOSFET device 100 consists of a substrate region of a first conductivity type 82 (shown as p-type in the figure), and first and second regions 84 and 86 of a second conductivity type Atty. Docket: ZENO-012WO
  • Insulating layers 96 can be used to separate one transistor device from other devices on the silicon substrate 82.
  • a standard MOSFET device 100A may also be used as shown in Fig. 90B.
  • a gate 90A separated from the surface region 88A by an insulating layer 92A, is also present in between the first and second regions 84A and 86A. Insulating layers 96A can be used to separate one transistor device from other devices in the well region 94A.
  • MOSFET devices 100 and 100A are both constructed in bulk silicon CMOS technology.
  • MOSFET device 100B is shown constructed out of silicon-on-insulator technology.
  • MOSFET device 100B consists of a tub region of a first conductivity type 82B (shown as p-type in the figure), and first and second regions 84B and 86B of a second conductivity type (shown as n-type) on the surface 88B, along with a gate 90B, separated from the semiconductor surface region by an insulating layer 92B.
  • Gate 90B is positioned in between the regions 84B and 86B.
  • the tub region 82B is isolated from other devices on the sides by insulating layers 96B and on the bottom by insulating layer 83B.
  • the transistors 100, 100A, and 100B are all called n-channel transistors because when turned on by applying an appropriate voltage to the gates 90, 90A and 90B respectively, the p-material under the gates is inverted to behave hke n- type conductivity type for as long as the gate voltage is applied.
  • This allows conduction between the two n-type regions 84 and 86 in MOSFET 100, 84A and 86A in MOSFET 100A and 84B and 86B in MOSFET 100B.
  • the conductivity types of all the regions may be reversed (i.e., the first conductivity type regions become n-type and the second conductivity type Atty. Docket: ZENO-012WO regions become p-type) to produce p-channel transistors.
  • n-channel transistors are be preferred for use in memory cells (of all types and
  • the invention below describes a semiconductor memory device having an electrically floating body that utilizes a back bias region to further reduce the memory device size.
  • One or more bits of binary information may be stored in a single memory cell.
  • semiconductor “diffusion” layers or regions such as transistor source, drain or source/drain regions, floating bodies, buried layers, wells, and the semiconductor substrate as well as related insulating regions between the diffusion regions (like, for example, silicon dioxide whether disposed in shallow trenches or otherwise) are typically considered to be “beneath” or “below” the semiconductor surface - and the drawing figures are generally consistent with this convention by placing the diffusion regions at the bottom of the drawing figures.
  • the convention also has various "interconnect" layers such as transistor gates (whether constructed of metal, p-type or n-type polysilicon or some other material), metal conductors in one or more layers, contacts between diffusion regions at the semiconductor surface and a metal layer, contacts between the transistor gates and a metal layer, vias between two metal layers, and the various insulators between them
  • the exemplary embodiments disclosed herein have at most one surface contact from the semiconductor region below the semiconductor surface to the interconnect region above the semiconductor surface within the boundary of the memory cell itself. This is in contrast to one-transistor (IT) floating body cell (FBC) D AMs of the prior art which have two contacts - one for the source region and one for the drain region of the transistor. " While some IT FBC DRAM cells of the prior art can share the two contacts with adjacent cells resulting in an average of one contact per cell, some embodiments of the present invention can also share its contact with an adjacent cell averaging half a contact per cell.
  • the advantage of the present invention is in the elimination of one of the source/drain regions at the surface of the semiconductor region thereby eliminating the need to contact it at the surface.
  • Fig 90B illustrating a prior art MOSFET with Fig. 35C illustrating an analogous cross section of one embodiment of the present invention.
  • the structure of Fig. 35C is inherently smaller than the structure of Fig. 90B.
  • the gate terminal is removed as well further reducing the size of the memory cell.
  • the analogous cross sections of the structures in Figs. 77C and 85C to the prior art MOSFET of Fig. 90B.
  • This new class of memory cell is referred to as a "Half Transistor Memory Cell” as a convenient shorthand for identical, similar or analogous structures.
  • a structure identical, similar or analogous to the structure of Fig. 35C is referred to as a "Gated Half Transistor Memory Cell.”
  • a structure identical, similar or analogous to the structures of Figs. 77C and 85C is referred to as a "Gateless Half Transistor Memory Cell.”
  • the vertical arrangement of the diffusion regions beneath the semiconductor surface common to all half transistor memory cells - specifically a bit line region at the surface of the semiconductor (allowing coupling to a bit line disposed above the semiconductor surface), a floating body region (for storing majority charge Atty.
  • ZENO-012WO carriers the quantity of majority carriers determining the logical state of the data stored in memory cell
  • a source line region completely beneath the semiconductor surface within the boundary of the memory cell allowing coupling to a source line running beneath the semiconductor surface, typically running beneath and coupling to a plurality of memory cells
  • the bit line region, the floating body, and the source line region form a vertical bipolar junction transistor that is used operatively and constructed deliberately by design for use in a floating body DRAM memory cell application - is referred to as a "Half Transistor.”
  • FIG. 1 Drawing figures in this specification, particularly diagrams illustrating semiconductor structures, are drawn to facilitate understanding through clarity of presentation and are not drawn to scale.
  • semiconductor structures illustrated there are two different conductivity types: p-type where the majority charge carriers are positively charged holes that typically migrate along the semiconductor valence band in the presence of an electric field, and n-type where the majority charge carriers are negatively charged electrons that typically migrate along the conduction band in the presence of an electric field.
  • Dopants are typically introduced into an intrinsic semiconductor (where the quantity of holes and electrons are equal and the ability to conduct electric current is low: much better than in an insulator, but far worse than in a region doped to be conductive - hence the "semi-" in “semiconductor") to create one of the conductivity types.
  • the quantities of dopant atoms used can vary widely over orders of magnitude of final concentration as a matter of design choice. However it is the nature of the majority carries and not their quantity that determines if the material is p-type or n-type. Sometimes in the art, heavily, medium, and lightly doped p-type material is designated p+, p and p- respectively while heavily, medium, and lightly doped n-type material is designated n+, n and n- respectively.
  • Figs. 35A through 35E illustrate an embodiment of a gated half transistor
  • FIG. 35A shows a top view of an embodiment of a partial memory array including memory cell 250 (shown by a dotted line) and Fig. 35B shows memory cell 250 in isolation.
  • Figs. 35C and 35D show the memory cell 250 cross sections along the ⁇ - ⁇ line and ⁇ - ⁇ cut lines, respectively, while Fig. 35E shows a method for electrically contacting the buried well and substrate layers beneath the cell.
  • the cell 250 includes a substrate
  • substrate 12 of a first conductivity type such as a p-type, for example.
  • Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, galhum arsenide, carbon nanotubes, or other semiconductor materials.
  • substrate 12 can be the bulk material of the semiconductor wafer.
  • substrate 12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice.
  • the substrate 12 will usually be drawn as the semiconductor bulk material as it is in Figs. 35C and 35D.
  • Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can also be grown epitaxially on top of substrate 12.
  • a floating body region 24 of the first conductivity type is bounded on top by bit line region 16 and insulating layer 62, on the sides by insulating layers 26 and 28, and on the bottom by buried layer 22.
  • Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted.
  • floating body 24 may be epitaxially grown.
  • floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments, as a matter of design choice.
  • Insulating layers 26 and 28 (like, for example, shallow trench isolation
  • Insulating layers 26 and 28 insulate cell 250 from neighboring cells 250 when multiple cells 250 are joined in an array 280 to make a memory device as illustrated in Figs. 38A-38C.
  • Insulating layer 26 insulates both body region 24 and buried region 22 of adjacent cells (see Fig. 35C), while insulating layer 28 insulates neighboring body region 24, but not the buried layer 22, allowing the buried layer 22 to be continuous (i.e. electrically conductive) in Atty. Docket: ZENO-012WO one direction (along the ⁇ - ⁇ direction as shown in Fig. 35D).
  • bit line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24 and is exposed at surface 14.
  • Bit line region 16 is formed by an implantation process formed on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to form bit line region 16.
  • a gate 60 is positioned in between the bit line region 16 and insulating layer 26 and above the floating body region 24.
  • the gate 60 is insulated from floating body region 24 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
  • Cell 250 further includes word line (WL) terminal 70 electrically
  • bit line (BL) terminal 74 electrically connected to bit line region 16
  • source line (SL) terminal 72 electrically connected to buried layer 22
  • substrate terminal 78 electrically connected to substrate 12.
  • contact between SL terminal 72 and buried layer 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22, while contact between substrate terminal 78 and substrate region 12 can be made through region 21 having a first conductivity type, and which is electrically connected to substrate region 12.
  • the SL terminal 72 connected to the buried layer region 22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor Atty. Docket: ZENO-012WO device, usually at the opposite side of the gate of the transistor coupled to the body or bulk of the device corresponding to region 82 in transistor 100 of Fig. 90A or region 94A in transistor 100A in Fig. 90B.
  • a conductive coupling to the floating body would be counterproductive since it would cease to be a floating body with such a connection.
  • the p-n junction between the floating body 24 and the buried well 22 coupled to the source line terminal 72 is forward biased to be conductive by applying a negative voltage to the source line terminal 72.
  • the SL terminal is biased to a positive voltage potential to maintain the charge in the floating body region 24.
  • the source line terminal 72 is used in a manner similar to the source line in floating body DRAM cells of the prior art.
  • SL terminal 72 may be used in a manner similar to a back bias terminal, or it may be used like a source line, or it may be used for another purpose entirely. In some embodiments it may be used in two or more of these ways in different operations. Thus both the terms “source line terminal” and "back bias terminal” are used
  • memory device 250 Comparing the structure of the memory device 250, for example, as shown in Fig. 35C to the structure of transistor devices 100, 100A and 100B in Figs. 90A through 90C, it can be seen that the memory device of present invention constitutes a smaller structure relative to the MOSFET devices 100, 100A and 100B, where only one region of a second conductivity type is present at the surface of the silicon substrate.
  • memory cell 250 of the present invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e. bit line region 16 as opposed to regions 84 and 86 or regions 84A and 86A) and hence requires only one contact per memory cell 250 (i.e. to create a connection between bit line region 16 and terminal 74).
  • first and second conductivity types can be reversed in memory cell 250as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way.
  • the first and second conductivity types can be p-type and n-type respectively in some embodiments Atty. Docket: ZENO-012WO of memory cell 50 and be n-type and p-type respectively in other embodiments.
  • FIG. 36A through 36U A method of manufacturing memory cell 250 will be described with reference to Figs. 36A through 36U. These 21 figures are arranged in groups of three related views, with the first figure of each group being a top view, the second figure of each group being a vertical cross section of the top view in the first figure of the group designated ⁇ - ⁇ , and the third figure of each group being a horizontal cross section of the top view in the first figure of the group designated ⁇ - ⁇ .
  • Figs. 36A, 36D, 36G, 36J, 36M, 36P and 36S are a series of top views of the memory cell 50 at various stages in the manufactirring process, Figs.
  • FIG. 36B, 36E, 36H, 36K, 36N, 36Q and 36T are their respective vertical cross sections labeled ⁇ - ⁇
  • Figs. 36C, 36F, 361, 36L, 360, 36R and 36U are their respective horizontal cross sections labeled ⁇ - ⁇ .
  • Identical reference numbers from Figs. 35A through 35E appearing in Figs. 36A through 36U represent similar, identical or analogous structures as previously described in conjunction with the earlier drawing figures.
  • vertical means running up and down the page in the top view diagram
  • “horizontal” means running left and right on the page in the top view diagram.
  • both cross sections are vertical with respect to the surface of the semiconductor device.
  • a thin silicon oxide layer 102 with a thickness of about 100A may be grown on the surface of substrate 12. This may be followed by a deposition of about 200A of polysilicon layer 104. This in turn may be followed by deposition of about 1200A silicon nitride layer 106.
  • Other process geometries like, for example, 250 nm, 180nm, 90 nm, 65 nm, etc., may be used.
  • other numbers of, thicknesses of, and combinations of protective layers 102, 104 and 106 may be used as a matter of design choice.
  • trench 108 may be formed using a lithography process. Then the silicon Atty. Docket: ZENO-012WO oxide 102, polysilicon 104, silicon nitride 106 layers may be subsequently patterned using the lithography process and then may be etched, followed by a silicon etch process, creating trench 108.
  • trenches 112 may be formed using a lithography process, which may be followed by etching of the silicon oxide 102, polysilicon 104, silicon nitride layers 106, and a silicon trench etch process, creating trench 1 12.
  • the trench 1 12 is etched such that the trench depth is deeper than that of trench 108.
  • the trench 108 depth may be about 1000A and the trench 1 12 depth may be about 2000A.
  • Other process geometries like, for example, 250 nm, 180nm, 90 nm, 65 nm, etc., may be used.
  • other trench depths may be used as a matter of design choice.
  • a silicon oxidation step which will grow silicon oxide films in trench 108 and trench 1 12 which will become insulating layers 26 and 28.
  • silicon oxide films in an exemplary 130 nm process, about 4000A silicon oxide nay be grown.
  • a chemical mechanical polishing step can then be performed to polish the resulting silicon oxide films so that the silicon oxide layer is flat relative to the silicon surface.
  • a silicon dry etching step can then be performed so that the remaining silicon oxide layer height of insulating layers 26 and 28 may be about 300A from the silicon surface. In other embodiments the top of insulating layers 26 and 28 may be flush with the silicon surface.
  • the silicon nitride layer 106 and the polysilicon layer 104 may then be removed which may then be followed by a wet etch process to remove silicon oxide layer 102 (and a portion of the silicon oxide films formed in the area of former trench 108 and former trench 1 12).
  • a wet etch process to remove silicon oxide layer 102 (and a portion of the silicon oxide films formed in the area of former trench 108 and former trench 1 12).
  • Other process geometries like, for example, 250 nm, 180nm, 90 nm, 65 nm, etc., may be used.
  • other insulating layer materials, heights, and thicknesses as well as alternate sequences of processing steps may be used as a matter of design choice.
  • an ion implantation step may then be performed to form the buried layer region 22 of a second conductivity (e.g. n- type conductivity).
  • the ion implantation energy is optimized such that the buried layer region 22 is formed shallower than the bottom of the insulating layer 26 and deeper than the bottom of insulating layer 28.
  • the insulating Atty. Docket: ZENO-012WO layer 26 isolates buried layer region 22 between adjacent cells while insulating layer 28 does not isolate buried layer region 22 between cells. This allows buried layer region 22 to be continuous in the direction of the ⁇ - ⁇ cross section. Buried layer 22 isolates the eventual floating body region 24 of the first conductivity type (e.g., p-type) from the substrate 12.
  • the first conductivity type e.g., p-type
  • a silicon oxide or high-dielectric material gate insulation layer 62 may then be formed on the silicon surface (e.g. about 100A in an exemplary 130 nm process), which may then be followed by a polysilicon or metal gate 60 deposition (e.g. about 500A in an exemplary 130 nm process).
  • a lithography step may then be performed to pattern the layers 62 and 60, which may then be followed by etching of the polysilicon and silicon oxide layers.
  • Other process geometries like, for example, 250 nm, 180nm, 90 nm, 65 nm, etc., may be used.
  • other gate and gate insulation materials with different thicknesses may be used a matter of design choice.
  • bit line region 16 of a second conductivity type (e.g. n-type conductivity). This may then be followed by backend process to form contact and metal layers (not shown in Figs. 36A through 36U).
  • the gate 60 and the insulating layers 26 and 28 serve as masking layer for the implantation process such that regions of second conductivity are not formed outside bit line region 16.
  • gate layer 60 and gate insulating layer 62 are shown flush with the edge of insulating layer 26.
  • gate layer 60 and gate insulating layer 62 may overlap insulating layer 16 to prevent any of the implant dopant for bit line region 16 from inadvertently implanting between gate layer 60 and gate insulating layer 62 and the adjacent insulating layer 26.
  • the memory cell will have a lower threshold voltage (the gate voltage where an ordinary MOSFET transistor is turned on - or in this case, the voltage at which an inversion layer is formed under gate insulating layer 62) compared to if cell 250 does not store holes in body region 24.
  • ZENO-012WO the gate voltage where an ordinary MOSFET transistor is turned on - or in this case, the voltage at which an inversion layer is formed under gate insulating layer 62
  • the positive charge stored in the floating body region 24 will decrease over time due to the diode leakage current of the p-n junctions formed between the floating body 24 and bit line region 16 and between the floating body 24 and the buried layer 22 and due to charge recombination.
  • a unique capability of the invention is the ability to perform the holding operation in parallel to all memory cells of the array.
  • the holding operation can be performed by
  • n-p-n bipolar device 30 formed by buried well region 22 (the collector region), floating body 24 (the base region), and bit line region 16 (the emitter region).
  • the hole current flowing into the floating region 24 (usually referred to as the base current) will maintain the logic- 1 state data.
  • the efficiency of the holding operation can be enhanced by designing the bipolar device formed by buried well region 22, floating region 24, and bit line region 16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector Atty. Docket: ZENO-012WO current flowing out of SL terminal 72 to the base current flowing into the floating region 24.
  • Fig. 37B shows the energy band diagram of the intrinsic n-p-n bipolar device 30 when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22.
  • the dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 30.
  • the Fermi level is located in the band gap between the solid line 17 indicating the top of the valance band (the bottom of the band gap) and the solid line 19 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art.
  • the positive charge in the floating body region lowers the energy barrier of electron flow into the base region.
  • the electrons will be swept into the buried well region 22 (connected to SL terminal 72) due to the positive bias applied to the buried well region 22.
  • the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism.
  • the resulting hot electrons flow into the SL terminal 72 while the resulting hot holes will subsequently flow into the floating body region 24. This process restores the charge on floating body 24 and will maintain the charge stored in the floating body region 24 which will keep the n-p-n bipolar transistor 30 on for as long as a positive bias is applied to the buried well region 22 through SL terminal 72.
  • Fig. 37C shows the energy band diagram of the intrinsic n-p-n bipolar device 30 when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22.
  • the energy level of the band gap bounded by solid lines 17A and 19A is different in the various regions of n-p-n bipolar device 30.
  • the Fermi levels are constant, resulting in an energy barrier between the bit line region 16 and the floating Atty. Docket: ZENO-012WO body region 24.
  • Solid line 23 indicates, for reference purposes, the energy barrier between the bit line region 16 and the floating body region 24. The energy barrier prevents electron flow from the bit line region 16 (connected to BL terminal 74) to the floating body region 24.
  • the n-p-n bipolar device 30 will remain off
  • bipolar device In the embodiment discussed in Figs. 37A through 37C, bipolar device
  • n-p-n transistor 30 has been an n-p-n transistor.
  • Persons of ordinary skill in the art will readily appreciate that by reversing the first and second connectivity types and inverting the relative values of the applied voltages memory cell 50 could comprise a bipolar device 30 which is a p-n-p transistor.
  • n-p-n transistor is an illustrative example for simplicity of explanation in Figs. 37A through 37C is not limiting in any way.
  • Fig. 38A shows an exemplary array 280 of memory cells 250 (four
  • representative memory cell 250 being labeled as 250a, 250b, 250c and 250d) arranged in rows and columns.
  • representative memory cell 250a will be representative of a "selected" memory cell 250 when the operation being described has one (or more in some embodiments) selected memory cells 250.
  • representative memory cell 250b will be representative of an unselected memory cell 250 sharing the same row as selected representative memory cell 250a
  • representative memory cell 250c will be representative of an unselected memory cell 250 sharing the same column as selected representative memory cell 250a
  • representative memory cell 250d will be representative of Atty. Docket: ZENO-012WO a memory cell 250 sharing neither a row or a column with selected
  • Fig. 38A Present in Fig. 38A are word lines 70a through 70n, source hnes 72a through 72 ⁇ , bit lines 74a through 74p, and substrate terminal 78.
  • Each of the word lines 70a through 70n is associated with a single row of memory cells 250 and is coupled to the gate 60 of each memory cell 250 in that row.
  • each of the source lines 72a through 72n is associated with a single row of memory cells 50 and is coupled to the buried well region 22 of each memory cell 50 in that row.
  • Each of the bit hnes 74a through 74p is associated with a single column of memory cells 50 and is coupled to the bit line region 16 of each memory cell 50 in that column.
  • Substrate 12 is present at all locations under array 280. Persons of
  • exemplary array 280 is shown as a single continuous array in Fig. 38A, that many other organizations and layouts are possible like, for example, word hnes may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, the array 280 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around exemplary array 280 or inserted between sub-arrays of array 280.
  • word decoders such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers
  • write amplifiers may be arrayed around exemplary array 280 or inserted between sub-arrays of array 280.
  • FIG. 38B array 280 previously discussed is shown along with multiplexers 40a through 40n and voltage waveforms 42a through 42n.
  • a periodic pulse of positive voltage can be applied to the back bias terminals of memory cells 250 through S L terminal 72 as opposed to applying a constant positive bias to reduce the power consumption of the memory cell 250.
  • Fig. 38B further shows multiplexers 40a through 40n each coupled to one of the source lines 72a through 72n that determine the bias voltages applied to SL terminals Atty. Docket: ZENO-012WO
  • the pulsing of the voltage on the SL terminals may be controlled, for example, by applying pulses of logic signals like waveforms 42a through 42n to the select input of multiplexers 40a through 40n thereby selecting, for example, ground (0.0 volts) or a power supply voltage such as Vcc-
  • Many other techniques may be used to pulse the voltage applied to SL terminals 72a through 72n like, for example, applying the waveforms 42a through 42n at different times, or applying them simultaneously, or coupling the select inputs of multiplexers 42a through 42n together and applying a single pulsed waveform to all of the multiplexers 42a through 42n simultaneously (not shown in the figure).
  • Many other options will readily suggest themselves to persons of ordinary skill in the art. Thus the described exemplary embodiments are not limiting in any way.
  • Fig. 38C shows another method to provide voltage pulses to SL terminals
  • the positive input signals to multiplexers 40a through 40n may be generated by voltage generator circuits 44a through 44n coupled to one input of each of the multiplexers 40a through 40n.
  • a single voltage generator circuit may be coupled to each of the multiplexers 40a through 40n reducing the amount of overhead circuitry required to refresh the memory cells 250 of array 280.
  • Other embodiments are possible including, for example, applying the waveforms 42a through 42n at different times, or applying them simultaneously, or coupling the select inputs of multiplexers 42a through 42n together and applying a single pulsed waveform to all of the multiplexers 42a through 42n simultaneously (not shown in the figure).
  • Fig. 38D shows a reference generator circuit suitable for use as reference generator circuits 44a through 44n in Fig. 38C.
  • the reference generator includes reference cell 53, which consists of a modified version of Gated half transistor memory cell 250 described above with region 25 of the first conductivity type (p-type conductivity).
  • the p-type 25 region allows for a direct sensing of the floating body region 24 potential.
  • Region 25 is drawn separately even though it has the same conductivity type as floating body region 24 because it may be doped differently to facilitate contacting it.
  • the reference cell 53 for example can be configured to be in state logic- 1 where the potential of the floating body Atty. Docket: ZENO-012WO region 24 is positive, for example at +0.5V.
  • the potential sensed through the p- type region is then compared with a reference value VKEF, e.g. +0.5V, by operational amplifier 27. If the potential of the floating body region 24 is less than the reference value, the voltage apphed to the back bias terminal 72 (which is connected to buried region 22 of the reference cell 53 and can also be connected to buried region 22 of the Gated half transistor memory cell 250) is increased by operational amplifier 27 until the potential of the floating body region 24 reaches the desired reference voltage. If the potential of the floating body 24 region is higher than that of the reference value, the voltage applied to back bias terminal 72 can be reduced by operational amplifier 27 until the potential of the floating body region 24 reaches the desired reference voltage.
  • Reference voltage VREF may be generated in many different ways like, for example, using a band gap reference, a resistor string, a digital-to-analog converter, etc. Similarly alternate voltage generators of types known in the art may be used
  • the holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24.
  • the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage VFB as the junction leakage current from floating body 24 to bit line region 16 increases exponentially at floating body potential greater than VFB -
  • the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and bit line region 16.
  • the maximum charge VMC stored in floating body 24 can be increased by applying a positive bias to the SL terminal 72 as shown in the graph in Fig. 39. The increase in the maximum charge stored in the floating body 24 results in a larger memory window.
  • the holding/standby operation can also be used for multi-bit operation in memory cell 250.
  • a multi-level operation is typically used. This is done by dividing the overall memory window into more than two different levels. In one embodiment four levels representing two binary bits of data are Atty. Docket: ZENO-012WO used, though many other schemes like, for example, using eight levels to represent three binary bits of data are possible.
  • the different memory states are represented by different charge in the floating body 24, as described, for example, in Tack and Oknonin-2 cited above.
  • the floating body 24 since the state with zero charge in the floating body 24 is the most stable state, the floating body 24 will over time lose its charge until it reaches the most stable state. In multi-level operation, the difference of charge representing different states is smaller than a single-level operation. As a result, a multi-level memory cell is more sensitive to charge loss.
  • Fig. 40 shows the floating body 24 net current for different floating body
  • the current flowing into floating body 24 is balanced by the junction leakage between floating body 24 and bit line region 16.
  • the different floating body 24 potentials represent different charges used to represent different states of memory cell 50. This shows that different memory states can be maintained by using the holding/standby operation described here.
  • the bias condition for the holding operation for memory cell 250 is: 0 volts is applied to BL terminal 74, a positive voltage hke, for example, +1.2 volts is applied to SL terminal 72, 0 volts is applied to " WL terminal 70, and 0 volts is applied to the substrate terminal 78. In another embodiment, a negative voltage may be applied to " WL terminal 70. In other embodiments, different voltages may be applied to the various terminals of memory cell 250 as a matter of design choice and the exemplary voltages described are not limiting in any way. Atty. Docket: ZENO-012WO
  • the amount of charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 250. If memory cell 250 is in a logic- 1 state having holes in the body region 24, then the memory cell will have a higher cell current (e.g. current flowing from the BL terminal 74 to SL terminal 72), compared to if cell 250 is in a logic-0 state having no holes in floating body region 24. A sensing circuit typically connected to BL terminal 74 can then be used to determine the data state of the memory cell.
  • a read operation may be performed by applying the following bias condition to memory cell 250: a positive voltage is applied to the selected BL terminal 74, and an even more positive voltage is applied to the selected WL terminal 70, zero voltage is applied to the selected SL terminal 72, and zero voltage is applied to the substrate terminal 78.
  • This has the effect of operating bipolar device 30 as a backward n-p-n transistor in a manner analogous to that described for operating bipolar device 30 for a hold operation as described in conjunction with Figs. 37A through 37C.
  • the positive voltage applied to the WL terminal 70 boosts the voltage on the floating body region 24 by means of capacitive coupling from the gate 60 to the floating body region 24 through gate insulating layer 62.
  • the optimal bias voltage to apply to WL terminal 70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.
  • FIG. 41 shows array 280 of memory cells 250 during a read operation in one exemplary embodiment of the present invention. Reading a memory cell 250 in array 280 is more complicated than reading a single cell as described above, since cells are coupled together along rows by word lines 70a through 70n and source lines 72a through 72n and coupled together along columns by bit lines Atty. Docket: ZENO-012WO
  • 0.0 volts is applied to the selected SL terminal 72a
  • about +0.4 volts is applied to the selected bit line terminal 74a
  • about +1.2 volts is applied to the selected word line terminal 70a
  • about 0.0 volts is applied to substrate terminal 78. All the unselected bit line terminals 74b (not shown) through 74p have 0.0 volts applied, the unselected word line terminals 70b (not shown) through 70n have 0.0 volts applied, and the unselected SL terminals 72b (not shown) have +1.2 volts applied.
  • 41 shows the bias conditions for the selected representative memory cell 250a and three unselected representative memory cells 250b, 250c, and 250d in memory array 280, each of which has a unique bias condition.
  • Persons of ordinary skill in the art will appreciate that other embodiments of the invention may employ other combinations of applied bias voltages as a matter of design choice. Such skilled persons will also realize that the first and second conductivity types may be reversed and the relative bias voltages may be inverted in other embodiments.
  • Fig. 42A also shows the bias condition of the selected representative memory cell 250a in cross section while Fig. 42B shows the equivalent circuit diagram illustrating the intrinsic n-p-n bipolar device 30 under the read bias conditions described above.
  • Figs. 42C, 42E, and 42G The three cases for unselected memory cells 250 during read operations are shown in Figs. 42C, 42E, and 42G, while illustrations of the equivalent circuit diagrams are shown in Figs. 42D, 42F, and 42H respectively.
  • the bias conditions for memory cells 250 sharing the same row (e.g. representative memory cell 250b) and those sharing the same column (e.g., representative memory cell 250c) as the selected representative memory cell 250a are shown in Figs. 42C-42D and Figs. 42E-42F, respectively, while the bias condition for memory cells 250 not sharing the same row nor the same column as the selected representative memory cell 250a (e.g., representative memory cell 250d) is shown in Fig. 42G-42H.
  • the SL terminal 72n will remain positively charged and the BL terminal 74p will remain grounded.
  • these cells will be in the holding mode, where memory cells in the logic- 1 state will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24 and memory cells in the logic- 0 state will remain in neutral state.
  • FIG. 43A A first type of write logic-0 operation of an individual memory cell 250 is now described with reference to Figs. 43A and 43B.
  • a negative voltage bias is applied to the back bias terminal (i.e. SL terminal 72)
  • a zero voltage bias is applied to WL terminal 70
  • a zero voltage bias is applied to BL terminal 72 and substrate terminal 78.
  • the p-n junction between floating body 24 and buried well 22 of the selected cell 250 is forward- biased, evacuating any holes from the floating body 24.
  • about -0.5 volts is applied to source line terminal 72, about 0.0 volts is applied to word line terminal 70, and about 0.0 volts is applied to bit line terminal 74 and substrate terminal 78.
  • These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
  • FIG. 43B an alternative embodiment of memory cell 250 is shown where substrate 12 is replaced by region 12A of the first conductivity type (p- type in the figure) which is a well inside substrate 29 of the second conductivity type (n-type in the figure).
  • This arrangement overcomes an undesirable side effect of the embodiment of Fig. 43A where lowering the buried well region 22 voltage on buried well terminal 72 to approximately -0.5V to forward bias the p- n junction between buried well 22 and floating body 24 also forward biases the p-n junction between buried well 22 and substrate 12 resulting in unwanted substrate current.
  • the substrate 29 is preferably biased to 0.0V through substrate terminal 31 as shown in Figure 43B.
  • These voltage levels are exemplary only may vary from embodiment to embodiment as a matter of design choice, Thus the exemplary embodiments, features, bias levels, etc., described are not limiting in any way.
  • Fig. 44 shows an example of bias conditions for the selected
  • Figs. 45A through 45B illustrate an example of bias conditions and an equivalent circuit diagram illustrating the intrinsic n-p-n bipolar devices 30 of unselected memory cells 250 like representative memory cells 250c and 250d in array 280 during the first type of logic-0 write operations.
  • representative memory cell 250d will be discussed for clarity of presentation though the principles apply to all unselected memory cells 250.
  • the logic-0 write operation only involves a negative voltage to the selected SL terminal 72a
  • the memory cells 250 coupled to the unselected S L terminals 72b (not shown in Fig. 44) through 72n are placed in a holding operation by placing a positive bias condition on S L terminals 72b through 72n.
  • the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero voltage, and the unselected SL terminal positively biased.
  • a second type of write logic-0 operation can also be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72.
  • the selected memory cells 250 include representative memory cells 250a and 250c and all the memory cells 250 that share the selected bit line 74a.
  • the SL terminal 72 will be positively biased, while zero voltage is applied to the substrate terminal 78, and zero voltage is applied to the WL terminal 70. Under these conditions, all memory cells sharing the same BL terminal 74 will be written to the logic-0 state.
  • the first and second types of write logic-0 operations referred to above each has a drawback that all memory cells 250 sharing either the same SL terminal 72 (the first type - row write logic-0) or the same BL terminal 74 will (the second type - column write logic-0) be written to simultaneously and as a result, does not allow writing logic-0 to individual memory cells 250.
  • a write logic-0 operation is first performed on all the memory cells to be written followed by one or more write logic- 1 operations on the bits that must be written to logic- 1.
  • a third type of write logic-0 operation that allows for individual bit writing can be performed on memory cell 250 by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or positive voltage to SL terminal 72, and zero voltage to substrate terminal 78.
  • the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70.
  • the p-n junction between 24 and bit line region 16 is forward- biased, evacuating any holes from the floating body 24.
  • the applied potential can be optimized as follows: if the floating body 24 potential of state logic- 1 is referred to as VFBI, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VFBI/2 while -VFBI/2 is applied to BL terminal 74. Additionally, either ground or a slightly positive voltage may also be applied to the BL terminals 74 of unselected memory cells 250 that do not share the same BL terminal 74 as the selected memory cell 250, while a negative voltage may also be applied to the WL terminals 70 of unselected memory cells 250 that do not share the same WL terminal 70 as the selected memory cell 250.
  • bias conditions are applied to the selected representative memory cell 250a in exemplary memory array 280 to perform an individual write logic-0 operation exclusively in representative memory cell 250a: a potential of about 0.0 volts to SL terminal 72a, a potential of about -0.2 volts to BL terminal 74a, a potential of about +0.5 volts is applied to word hne terminal 70a, and about 0.0 volts is applied to substrate terminal 78.
  • FIGs. 48A and 48B the potential difference between floating body 24 and bit line region 16 connected to BL terminal 74a is now increased due to the capacitive coupling from raising WL terminal 70a from ground to +0.5V, resulting in a higher forward bias current than the base hole current generated by the n-p-n bipolar device 30 formed by buried well region 22 connected to SL terminal 72a, floating body 24, and bit line region 16. The result is that holes will be evacuated from floating body 24.
  • the unselected memory cells 250 in memory array 280 under the bias conditions of Fig. 47 during the individual bit write logic-0 operation are shown in Figs. 48C through48H.
  • the bias conditions for memory cells sharing the same row (e.g. representative memory cell 250b) as the selected representative memory cell 250a are illustrated in Figs. 48C and 48D
  • the bias conditions for memory cells sharing the same column (e.g. representative memory cell 250c) as the selected representative memory cell 250a are shown in Figs. 48E and 48F
  • the bias conditions for memory cells sharing neither the same row nor the same column (e.g. representative memory cell 250d) as the selected representative memory cell 250a are shown in Figs. 48G and 48H.
  • memory cell 250b sharing the same row as the selected representative memory cell 250a will increase due to capacitive coupling from WL terminal 70 by AVFB-
  • the increase in the floating body 24 potential is not sustainable as the forward bias current of the p-n diodes formed by floating body 24 andjunction 16 will evacuate holes from floating body 24.
  • the floating body 24 potential will return to the initial state logic-0 equihhrium potential.
  • the floating body 24 potential will initially also increase by AVFB, which will result in holes being evacuated from floating body 24.
  • the floating body 24 potential After the positive bias on the WL terminal 70 is removed, the floating body 24 potential will decrease by AVFB- If the initial floating body 24 potential of state logic-1 is referred to as VFBI, the floating body 24 potential after the write logic-0 operation will become VFBI- AVFB- Atty. Docket: ZENO-012WO
  • the WL potential needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic- 1 is not too large during the time when the positive voltage is applied to (and subsequently removed from) WL terminal 70a.
  • the maximum floating body potential increase due to the coupling from the WL potential cannot exceed VFBI/2.
  • a negative voltage is applied to the BL terminal 74a, resulting in an increase in the potential difference between floating body 24 and bit line region 16 connected to the BL terminal 74a.
  • the p-n diode formed between floating body 24 and bit line region 16 will be forward biased.
  • the increase in the floating body 24 potential will not change the initial state from logic-0 as there is initially no hole stored in the floating body 24.
  • the net effect is that the floating body 24 potential after write logic-0 operation will be reduced.
  • the BL potential also needs to be optimized such that the decrease in floating body potential of memory cells 250 in state logic- 1 is not too large during the time when the negative voltage is applied to BL terminal 74a.
  • the - VFBI/2 is applied to the BL terminal 74a.
  • memory cell 250d sharing neither the same row nor the same column as the selected representative memory cell 250a, these cells will be in a holding mode as positive voltage is applied to the S L terminal 72n, zero voltage is applied to the BL terminal 74p, and zero or negative voltage is applied to WL terminal 70n, and zero voltage is applied to substrate terminal 78.
  • a write logic- 1 operation may be performed on memory cell 250 through impact ionization as described, for example, with reference to Lin cited above, or through a band-to-band tunneling mechanism (also known as Gate Induced Drain Leakage or GIDL), as described, for example with reference to Yoshida cited above.
  • a band-to-band tunneling mechanism also known as Gate Induced Drain Leakage or GIDL
  • An example of a write logic-1 operation using the GIDL method is described in conjunction with Figs. 49 and 50A through 50H while an example of a write logic-1 operation using the impact ionization method is described in conjunction with Figs 51 and 52A through 52H.
  • Fig. 49 an example of the bias conditions of the array 280 including selected representative memory cell 250a during a band-to-band tunneling write logic- 1 operation is shown.
  • the negative bias applied to the WL terminal 70a and the positive bias applied to the BL terminal 74a results in hole injection to the floating body 24 of the selected representative memory cell 250a.
  • the SL terminal 72a and the substrate terminal 78 are grounded during the write logic-1 operation.
  • the negative voltage on WL terminal 70 couples the voltage potential of the floating body region 24 in representative memory cell 250a downward. This combined with the positive voltage on BL terminal 74a creates a strong electric field between the bit line region 16 and the floating body region 24 in the proximity of gate 60 (hence the "gate induced” portion of GIDL) in selected representative memory cell 250a. This bends the energy bands sharply upward Atty. Docket: ZENO-012WO near the gate and drain junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band.
  • the following bias conditions may be applied to the selected representative memory cell 250a: a potential of about 0.0 volts is apphed to SL terminal 72a, a potential of about +1.2 volts is apphed to BL terminal 74a, a potential of about -1.2 volts is applied to WL terminal 70a, and about 0.0 volts is apphed to substrate terminal 78.
  • bias conditions are apphed to the terminals for unselected memory cells 250 including representative memory cells 250b, 250c and 250d: about +1.2 volts is apphed to SL terminal 72 ⁇ , about 0.0 volts is apphed to BL terminal 74p, a potential of about 0.0 volts is applied to WL terminal 70n, and about 0.0 volts is applied to substrate terminal 78.
  • Fig. 49 shows the bias condition for the selected and unselected memory cells in memory array 280.
  • these voltage levels may vary from embodiment to embodiment of the present invention and are exemplary only and are in no way limiting.
  • the unselected memory cells during write logic-1 operations are shown in Figs. 50C through 50H.
  • the bias conditions for memory cells sharing the same row are shown in Figs. 50C and 50D.
  • the bias conditions for memory cells sharing the same column as the selected representative memory cell 250a are shown in Figs. 50E and 50F.
  • the bias conditions for memory cells 250 not sharing the same row nor the same column as the selected representative memory cell 250a are shown in Figs. 50G and 50H.
  • representative memory cell 250b sharing the same row as the selected representative memory cell 250a, has both terminals 72a and 74p grounded, while about -1.2 volts is applied to WL Atty. Docket: ZENO-012WO terminal 70a. Because SL terminal 70a is grounded, memory cell 250b will not be at the holding mode since there is no voltage across between the emitter and collector terminals of the n-p-n bipolar device 30 tirrning it off. However, because the write logic-1 operation is accomplished much faster (on the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (on the order of milliseconds), it should cause little disruption to the charge stored in the floating body.
  • the SL terminal 72n will remain positively charged while the gate terminal 70n and the BL terminal 74p remain grounded. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30a will generate holes current to replenish the charge in floating body 24, while memory cells in state logic-0 will remain in neutral state.
  • Fig. 51 shows a write logic-1 operation using the impact ionization
  • both the gate 60 and bit line 16 of the memory cell 250 to be written are biased at a positive voltage. This is similar to the holding operation described earlier in conjunction with Figs. 37A through 38D which also uses impact ionization to supply hole current to the floating body 24.
  • the n-p-n bipolar device 30 stays off when a logic-0 is stored in memory cell 250 and impact ionization current only flows when a logic- 1 is stored in the cell restoring the charge level in the floating body 24 to a full logic-1 level.
  • the voltage on the gate terminal is positive rather than zero.
  • the action of raising the gate 60 to a positive voltage has the effect of raising the voltage potential of the floating body region 24 due to capacitive coupling across the gate insulating layer 62 which causes the n-p-n bipolar transistor 30 to turn on regardless of whether or not a logic- 1 or logic-0 is stored in memory cell 250. This causes impact ionization current to flow charging the floating body 24 to the logic- 1 state regardless of the data originally stored in the cell.
  • the selected word line terminal 70a is biased at about +1.2V while the unselected word line terminals 70b (not shown) through 70n are biased at about 0.0V
  • the selected bit line terminal 74a is also biased at about + 1.2V while the unselected bit line terminals 74b through 74p are biased at about 0.0V
  • the selected source line 72a is biased at about 0.0V
  • the unselected source line terminals 72b (not shown) through 72n are biased at about +1.2V
  • the substrate terminal 78 is biased at about 0.0V.
  • FIG. 52A through 52B selected representative memory cell 50a is shown with gate 60 coupled to WL terminal 70A biased at +1.2V, bit line region 16 coupled to BL terminal 74a biased at +1.2V, and buried layer 22 coupled to source line terminal 72a biased at 0.0V.
  • impact ionization current flows into the cell from BL terminal 74a inj ecting holes into the floating body region 24 writing a logic- 1 state into representative memory cell 250a.
  • unselected representative memory cell 250b sharing a row but not a column with selected representative memory cell 250a, is shown with gate 60 coupled to WL terminal 70a biased at +1.2V, bit line region 16 coupled to BL terminal 74p biased at 0.0V, and buried layer 22 coupled to source line terminal 72a biased at 0.0V.
  • the collector-to- emitter voltage of n-p-n bipolar device 30 is 0.0V causing the device to be off protecting the contents of representative memory cell 250b.
  • n-p-n bipolar device 30 As shown in Figs. 52E through 52F, unselected representative memory cell 250c, sharing a column but not a row with selected representative memory Atty. Docket: ZENO-012WO cell 250a, is shown with gate 60 coupled to WL terminal 70n biased at 0.0V, bit line region 16 coupled to BL terminal 74a biased at +1.2V, and buried layer 22 coupled to source line terminal 72n biased at +1.2V. In this state, the n-p-n bipolar device 30 will be off since there is no voltage difference between the collector and emitter terminals of n-p-n bipolar device 30.
  • unselected representative memory cell 250d sharing neither a row nor a column with selected representative memory cell 250a, is shown with gate 60 coupled to WL terminal 70n biased at 0.0V, bit line region 16 coupled to BL terminal 74p biased at 0.0V, and buried layer 22 coupled to source line terminal 72n biased at + 1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30a will generate holes current to replenish the charge in floating body 24, while memory cells in state logic-0 will remain in neutral state.
  • Fig. 53A shows a top view of an embodiment of a partial memory array including Gated half transistor memory cell 350 according to the present invention and Fig. 53B shows memory cell 350 in isolation.
  • Figs. 53C and 53D show the memory cell 350 cross sections along the I-F line and ⁇ - ⁇ cut lines, respectively, while Fig. 53E shows a method of contacting the buried well and substrate layers beneath the cells.
  • Figs. 54A through 54H show memory array 380 comprised of rows and columns of memory cell 350. The primary difference between memory cell 250 and memory cell 350 is that while insulating layers 26 isolate the buried layer 22 between memory cells in adjacent rows in memory cell 250, in memory cell 350 the regions occupied by insulating layer 26 are replaced by insulating layer 28.
  • memory cell 350 is surrounded by insulating layer 28 on all four sides and the buried layer 22 is continuously connected as a single "source line" amongst all of the memory cells 350 in memory array 380.
  • memory cell 250 in memory cell 280 there is no contact to the buried layer 22 within the boundary of memory cell 350.
  • the cell 350 includes a substrate
  • substrate 12 of a first conductivity type such as a p-type, for example.
  • Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials.
  • substrate 12 can be the bulk material of the semiconductor wafer.
  • substrate 12 can be a well of the first conductivity type embedded in either a well of the second conductivity type or, alternatively, in the bulk of the semiconductor wafer of the second conductivity type, such as n-type, for example, (not shown in the figures) as a matter of design choice.
  • the substrate 12 will is drawn as the semiconductor bulk material as it is in Figs. 53C and 53D though it may also be a well in a substrate of material of the second type of conductivity.
  • Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can also be grown epitaxially on top of substrate 12.
  • a floating body region 24 of the first conductivity type such as p-type, for example, is bounded on top by bit line region 16 an insulating layer 62, on the sides by insulating layer 28, and on the bottom by buried layer 22.
  • Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted.
  • floating body 24 may be epitaxially grown.
  • floating body 24 may have the same doping as substrate 12 in some
  • Insulating layers 28 may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 28 insulate cell 350 from neighboring cells 350 when multiple cells 350 are joined in an array 380 to make a memory device as illustrated in Figs. 54A-54F. Insulating layer 28 insulates neighboring body regions 24, but not the buried layer 22, allowing the buried layer 22 to be continuous (i.e. electrically conductive) under the entire array 380. Atty. Docket: ZENO-012WO
  • bit line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24 and is exposed at surface 14.
  • Bit line region 16 is formed by an implantation process formed on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion process could be used to form bit line region 16.
  • a gate 60 is positioned in between the bit line region 16 and insulating layer 28 and above the floating body region 24.
  • the gate 60 is insulated from floating body region 24 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
  • Memory cell 350 further includes word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 16, source line (SL) terminal 72 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to substrate 12.
  • WL word line
  • BL bit line
  • SL source line
  • substrate terminal 78 electrically connected to substrate 12.
  • contact between SL terminal 72 and buried layer 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22, while contact between substrate terminal 78 and substrate region 12 can be made through region 21 having a first conductivity type, and which is electrically connected to substrate region 12.
  • the SL terminal 72 connected to the buried layer region 22 serves as a back bias terminal, i.e. a terminal at the back side of a semiconductor transistor device, usually at the opposite side of the gate of the transistor.
  • memory device 350 Comparing the structure of the memory device 350, for example, as shown in Fig. 53C to the structure of transistor devices 100, 100A and 100B in Figs. 90A through 90C, it can be seen that the memory device of present invention constitutes a smaller structure relative to the MOSFET devices 100, 100A and 100B, where only one region of a second conductivity type is present at the surface of the silicon substrate.
  • memory cell 350 of the present Atty. Docket: ZENO-012WO invention provides an advantage that it consists of only one region of second conductivity at the surface (i.e. bit line region 16 as opposed to regions 84 and 86 or regions 84A and 86A) and hence requires only one contact per memory cell 350 (i.e. to create a connection between bit line region 16 and terminal 74).
  • first and second conductivity types can be reversed in memory cell 350 as a matter of design choice and that the labeling of regions of the first conductivity type as p-type and the second conductivity type as p-type is illustrative only and not limiting in any way.
  • the first and second conductivity types can be p-type and n-type respectively in some embodiments of memory cell 350 and be n-type and p-type respectively in other embodiments.
  • the relative doping levels of the various regions of either conductivity type will also vary as a matter of design choice and that there is no significance to the absence of notation signifying higher or lower doping levels such as p+ or p- or n+ or n- in any of the diagrams.
  • Fig. 54A shows an exemplary memory array 380 of memory cells 350
  • representative memory cell 350a will be representative of a "selected" memory cell 350 when the operation being described has one (or more in some embodiments) selected memory cells 350.
  • representative memory cell 350b will be representative of an unselected memory cell 350 sharing the same row as selected representative memory cell 350a
  • representative memory cell 350c will be representative of an unselected memory cell 350 sharing the same column as selected representative memory cell 350a
  • representative memory cell 350d will be representative of a memory cell 350 sharing neither a row or a column with selected
  • Fig. 54A Present in Fig. 54A are word lines 70a through 70n, source line terminal
  • Each of the word lines 70a through 70n is associated with a single row of memory cells 350 and is coupled to the gate 60 of each memory cell 350 in that row.
  • Each of the bit lines 74a through 74p is associated with a single column of memory cells 350 and is Atty. Docket: ZENO-012WO coupled to the bit line region 16 of each memory cell 350 in that column.
  • source line terminal 72X is really no longer a control line terminal associated with the source line 72 of a row of memory cells 350 but a control terminal associated with all of the memory cells 350 in exemplary memory array 380, it will still be referred to as "source hne" terminal 72X to minimize confusion since it still serves that function for each individual memory cell 350.
  • Substrate 12 and buried layer 22 are both present at all locations under array 380.
  • one or more substrate terminals 78 and one or more buried well terminals 72 will be present in one or more locations as a matter of design choice.
  • Such skilled persons will also appreciate that while exemplary array 380 is shown as a single continuous array in Fig.
  • word lines may be segmented or buffered
  • bit lines may be segmented or buffered
  • source lines may be segmented or buffered
  • the array 380 may be broken into two or more sub-arrays
  • control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around exemplary array 380 or inserted between sub- arrays of array 380.
  • Fig. 54B illustrates an array hold operation on exemplary memory array
  • the hold operation is performed simultaneously by applying about + 1.2V to the source hne terminal 72 while applying about 0.0V to the word hne terminals 70a through 70 ⁇ , the bit line terminals 74a through 74p, and the substrate terminal 78.
  • This bias condition causes each of the memory cells 350 in the array 380 storing a logic- 1 to have its intrinsic bipolar transistor 30 turned on to restore the hole charge on its floating body 24 as discussed above. Simultaneously, this bias condition causes each of the memory cells 350 in the array 380 storing a logic-0 to have its intrinsic bipolar transistor 30 turned off to retain charge neutrality in its floating body 24 as previously discussed.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment and are in no way limiting. Atty. Docket: ZENO-012WO
  • Fig. 54C illustrates a single cell read operation of selected representative memory cell 350a in exemplary memory array 350.
  • the selected word line terminal 70a is biased to approximately +1.2V while the unselected word line terminals 70b (not shown) through 70n are biased to about 0.0V
  • the selected bit line terminal 74a is biased to approximately +0.4V while the unselected bit line terminals 74b through 74p are biased to about 0.0V
  • the source line terminal 72 is biased to about 0.0V
  • the substrate terminal is biased to about 0.0V.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • the capacitive coupling between the word line terminal 70a and the floating body 24 of selected memory cell 350a increase the differentiation in the read current between the logic- 1 and logic-0 states as previously described.
  • the optimal bias voltage to apply to WL terminal 70 will vary from embodiment to embodiment and process to process. The actual voltage applied in any given embodiment is a matter of design choice.
  • Unselected representative memory cell 350b which shares a row with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
  • Unselected representative memory cell 350c which shares a column with selected representative memory cell 350a, will either be off or be in a weak version of the holding operation depending on the device characteristics of the process of any particular embodiment. It also retains its logic state during the short duration of the read operation.
  • Unselected representative memory cell 350d which shares neither a row nor a column with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation. Atty. Docket: ZENO-012WO
  • Fig. 54D illustrates an array write logic-0 operation of all the memory cells 350 in exemplary memory array 350.
  • all the word line terminals 70a through 70n are biased to approximately 0.0V
  • all the bit line terminals 74a through 74p are biased to approximately -1.2V
  • the source line terminal 72 is biased to about 0.0V
  • the substrate terminal is biased to about 0.0V.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in each of the memory cells 350 as previously described. This evacuates all of the holes in the floating body regions 24 writing a logic-0 to all of the memory cells 350 in array 380.
  • Fig. 54E illustrates a column write logic-0 operation of one column of the memory cells 350 in exemplary memory array 350.
  • all the word line terminals 70a through 70n are biased to approximately 0.0V
  • selected the bit line terminal 74a is biased to approximately -1.2V while the unselected bit line terminals 74b through 74p are biased to about 0.0V
  • the source line terminal 72 is biased to about +1.2V
  • the substrate terminal is biased to about 0.0V.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in each of the memory cells 350 coupled to bit line 74a, including representative memory cells 350a and 350c, as previously described. This evacuates all of the holes in the floating body regions 24 writing a logic-0 to all of the memory cells 350 in the selected column.
  • the remaining memory cells 350 in array 380 including representative memory cells 350b and 350d, are in a holding operation and will retain their logic state during the write logic-0 operation.
  • Fig. 54F illustrates a single cell write logic-0 operation of selected
  • the selected word line terminal 70a is biased to approximately +0.5V while the unselected word line terminals 70b (not shown) through 70n are Atty. Docket: ZENO-012WO biased to about -1.2V, the selected bit line terminal 74a is biased to
  • the unselected bit line terminals 74b through 74p are biased to about 0.0V
  • the source line terminal 72 is biased to about 0.0V
  • the substrate terminal is biased to about 0.0V.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • This bias condition forward biases the p-n junction between the floating body 24 and the bit line region 16 turning on the intrinsic bipolar device 30 in selected representative memory cell 350a.
  • the capacitive coupling between the word line terminal 70a and the floating body 24 of selected memory cell 350a causes bipolar device 30 to turn on evacuating the holes in floating body region 24 as previously described.
  • Unselected representative memory cell 350b which shares a row with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
  • Unselected representative memory cell 350c which shares a column with selected representative memory cell 350a, has the voltage potential of its floating body temporarily lowered because the negative capacitive coupling between its floating body 24 its gate 60 (coupled to word line terminal 70n) preventing its bipolar device 30 from turning on. It also retains its logic state during the short duration of the read operation, and the voltage potential of its floating body 24 is restored to its previous level by the positive coupling between its floating body 24 its gate 60 (coupled to word line terminal 70n) when the word line terminal is returned to its nominal value of about 0.0V after the operation is complete.
  • Unselected representative memory cell 350d which shares neither a row nor a column with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
  • Fig. 54G illustrates a single cell write logic-1 operation using a GIDL mechanism in selected representative memory cell 350a in exemplary memory array 350.
  • the selected word line terminal 70a is biased to approximately -1.2V while the unselected word line terminals 70b (not shown) Atty. Docket: ZENO-012WO through 70n are biased to about 0.0V, the selected bit line terminal 74a is biased to approximately +1.2V while the unselected bit line terminals 74b through 74p are biased to about 0.0V, the source line terminal 72 is biased to about 0.0V, and the substrate terminal is biased to about 0.0V.
  • the voltages applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • This bias condition causes selected representative memory cell 350a to conduct current due to the GIDL mechanism discussed with reference to Yoshida cited above.
  • the combination of -1.2V on word Hne terminal and +1.2V on bit line terminal 74a creates the strong electric field necessary to produce GIDL current from bit Hne 74a into representative memory ceU 350a generating sufficient hole charge in its floating body 24 to place it in the logic-1 state.
  • Unselected representative memory ceU 350b which shares a row with selected representative memory ceU 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
  • Unselected representative memory ceU 350c which shares a column with selected representative memory ceU 350a, is in the holding state. It also retains its logic state during the short duration of the write logic- 1 operation.
  • Unselected representative memory ceU 350d which shares neither a row nor a column with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
  • Fig. 54H iUustrates a single cell write logic-1 operation using an impact ionization mechanism in selected representative memory ceU 350a in exemplary memory array 350.
  • the selected word Hne terminal 70a is biased to approximately +1.2V while the unselected word line terminals 70b (not shown) through 70n are biased to about 0.0V
  • the selected bit line terminal 74a is biased to approximately +1.2V while the unselected bit Hne terminals 74b through 74p are biased to about 0.0V
  • the source line terminal 72 is biased to about 0.0V
  • the substrate terminal is biased to about 0.0V.
  • the voltages Atty. Docket: ZENO-012WO applied are exemplary only, may vary from embodiment to embodiment, and are in no way limiting.
  • This bias condition causes selected representative memory cell 350a to conduct current due to the impact ionization mechanism discussed with reference to Lin cited above.
  • the combination of +1.2V on word line terminal and +1.2V on bit line terminal 74a turns on the bipolar device 30 in
  • Unselected representative memory cell 350b which shares a row with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the read operation.
  • Unselected representative memory cell 350c which shares a column with selected representative memory cell 350a, is in the holding state. It also retains its logic state during the short duration of the write logic- 1 operation.
  • Unselected representative memory cell 350d which shares neither a row nor a column with selected representative memory cell 350a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It too retains its logic state during the short duration of the read operation.
  • the information stored in memory cell 250 or 350 corresponds to an integer number of binary bits, meaning that the number of voltage levels stored in memory cell 50 or 350 will be equal to a power of two (e.g., 2, 4, 8, 16, etc.), though other schemes are possible within the scope of the invention. Due to the lower noise margins, it may be desirable to encode the data in memory Atty. Docket: ZENO-012WO array 80 or 380 using any error correction code (ECC) known in the art. In order to make the ECC more robust, the voltage levels inside may be encoded in a non-binary order like, for example, using a gray code to assign binary values to the voltage levels .
  • ECC error correction code
  • gray coding only one bit changes in the binary code for a single level increase or decrease in the voltage level.
  • the lowest voltage level corresponding to the floating body region 24 voltage being neutral might be encoded as logic-00
  • the next higher voltage level being encoded as logic-01
  • the next higher voltage level after that being encoded as logic- 1 1
  • the highest voltage level corresponding to the maximum voltage level on floating body region 24 being encoded as logic- 10.
  • the logic levels from lowest to highest might be ordered logic-000, logic-001, logic-011, logic- 010, logic- 1 10, logic- 1 11, logic-101, and logic- 100.
  • this sort of encoding ensures that a single level reading error will produce at most a single bit correction per error minimizing the number of bits needing correction for any single error in a single cell.
  • Other encodings may be used, and this example is in no way limiting.
  • a multi-level write operation can be performed using an alternating write and verify algorithm, where a write pulse is first applied to the memory cell 250 or 350, followed by a read operation to verify if the desired memory state has been achieved. If the desired memory state has not been achieved, another write pulse is applied to the memory cell 250 or 350, followed by another read verification operation. This loop is repeated until the desired memory state is achieved.
  • the write operation is
  • a potential of about 0.0 volts is applied to SL terminal 72, a potential of about -1.2 volts is applied to WL terminal 70, and about 0.0 volts is applied to substrate terminal 78, while the potential applied to BL terminal 74 is incrementally raised. For example, in one non-limiting embodiment, 25 millivolts is initially applied to BL terminal 74, followed by a read verify operation. If the read verify operation indicates that the cell current has reached the desired state (i.e. cell current corresponding to whichever binary value of 00, 01, 11 or 10 is desired is achieved), then the multi -level write operation is successfully concluded.
  • the voltage applied to BL terminal 74 is raised, for example, by another 25 millivolts, to 50 millivolts. This is subsequently followed by another read verify operation, and this process iterates until the desired state is achieved.
  • the voltage levels described may vary from embodiment to embodiment and the above voltage levels are exemplary only and in no way limiting.
  • To write four levels to the memory cells at least three different positive voltage pulses (which may comprise of different amplitudes) to the BL terminal 74 are required. The first pulse corresponds to writing the memory cell to the level associated with the binary value of 01, the second pulse corresponds to writing the memory cell to the level associated with the binary value of 1 1, and the third pulse corresponds to writing the memory cell to the level associated with the binary value of 10.
  • the present invention provides a multi-level write operation that can be performed without alternate write and read operations as described in Figs. 55A through 55F with respect to exemplary memory array 280.
  • Figs. 55A through 55F with respect to exemplary memory array 280.
  • Persons of ordinary skill in the art will appreciate that the principles described will apply to all of the Half Transistor memory cells within the scope of the present invention.
  • the potential of the floating body 24 increases over time as a result of hole injection to floating body 24, for example through Atty. Docket: ZENO-012WO an impact ionization mechanism.
  • the change in cell current reaches the level associated with the desired state of the selected representative memory cell 250, the voltage applied to BL terminal 74 can be removed.
  • the multi -level write operation can be performed without alternate write and read operations by applying a voltage ramp of the correct duration.
  • the apphed voltage returns to the starting value like, for example, ground.
  • a voltage ramp of pulse width Tl apphed to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic- 00 level to the logic-01 level.
  • a voltage ramp of pulse width T2 applied to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic-00 level to the logic- 11 level
  • a voltage ramp of pulse width T3 apphed to the bit line terminal 74 of memory cell 250 in the lowest (logic-00 state) potential state will increase the potential of the floating body 24 from the logic- 00 level to the logic-10 level.
  • the state of the memory cell 250a can be simultaneously read for example by monitoring the change in the cell current through read circuitry 91a coupled to the source line 72a.
  • the unselected representative memory cell 250b has zero volts between the BL terminal 74p and the SL terminal 72a so no current flows and the state of the data stored in them will not change. Unselected
  • representative memory cell 250c sharing BL terminal 74a with selected representative memory cell 250a has its WL terminal grounded. Thus its floating body region 24 does not get the voltage coupling boost that the floating body region 24 in selected representative memory cell 250a gets.
  • a positive bias is also applied to the unselected SL terminal 72n. This condition substantially reduces the current in representative memory cell 250c which reduces the degree of hole charge its floating body region 24 receives as the voltage applied to BL terminal 74a is ramped up.
  • Unselected representative memory cell 250d sharing neither a row nor a column with selected representative memory cell 250a, is shown with gate 60 coupled to WL terminal 70n biased at 0.0V, bit line region 16 coupled to BL terminal 74p biased at 0.0V, and buried layer 22 coupled to source line terminal 72n biased at +1.2V. As can be seen, these cells will be at holding mode. Memory cells in state logic- 1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30a will generate holes current to replenish the charge in floating body 24, while memory cells in state logic-0 will remain in neutral state.
  • Fig. 55B also shows reference generator circuits 93a through 93n
  • source line terminals 72a through 72n coupled respectively to source line terminals 72a through 72n and read circuits 91a through 9 In coupled respectively to source line terminals 72a through 72n and coupled respectively to reference generator circuit 93a through 93n.
  • Reference generator circuit 93a serves to store the initial total cell current of selected representative memory cell 250a and provide this value to read circuit 91a during the write operation in real time so that the change in current can be monitored and feedback (not shown in Fig. 55B) can be used to shut off the voltage ramp at the appropriate time.
  • This function can be implemented in a variety of ways.
  • Fig. 55C for example, the cumulative charge of the initial state for selected memory cell 250a sharing the same source line 72a can be stored in a Atty. Docket: ZENO-012WO capacitor 97a. Transistor 95a is turned on when charge is to be written into or read from capacitor 94.
  • 250Rn similar to a memory cell 250 replace capacitors 97a through 97n in reference generator circuits 93a through 93n.
  • the reference cells 250Ra through 250Rn can also be used to store the initial state of selected representative memory cell 250a.
  • ionization mechanism can be performed by ramping the write current applied to BL terminal 74 instead of ramping the BL terminal 74 voltage.
  • a multi -level write operation can be performed on memory cell 250 through a band-to-band tunneling mechanism by ramping the voltage applied to BL terminal 74, while applying zero voltage to SL terminal 72, a negative voltage to WL terminal 70, and zero voltage to substrate terminal 78 of the selected memory cells 250.
  • the unselected memory cells 250 will remain in holding mode, with zero or negative voltage applied to WL terminal 70, zero voltage applied to BL terminal 74, and a positive voltage applied to SL terminal 72.
  • multiple BL terminals 74 can be simultaneously selected to write multiple cells in parallel. The potential of the floating body 24 of the selected memory cell(s) 250 will increase as a result of the band-to-band tunneling mechanism.
  • the state of the selected memory cell(s) 250 can be simultaneously read for example by monitoring the change in the cell current through a read circuit 91 coupled to the source line. Once the change in the cell current reaches the desired level associated with a state of the memory cell, the voltage applied to BL terminal 74 can be removed. In this manner, the multi -level write operation can be performed without alternate write and read operations.
  • the multi-level write operation using band-to-band tunneling mechanism can also be performed by ramping the write current applied to BL terminal 74 instead of ramping the voltage applied to BL terminal 74.
  • a reading circuit 99b through 99p may be coupled to each bit of the other bit lines 74b through 74p, while in other embodiments reading circuit 99a may be shared between multiple columns using a decoding scheme (not shown).
  • Reference cells 250R representing different memory states are used to verify the state of the write operation.
  • the reference cells 250R can be configured through a write-then-verify operation, for example, when the memory device is first powered up or during subsequent refresh periods .
  • selected representative memory cell 250a is being written
  • selected reference cell 250R containing the desired voltage state (or a similar voltage) to be written is read and the value is used to provide feedback to read circuit so that the write operation may be terminated when the desired voltage level in selected representative memory cell 250a is reached.
  • multiple columns of reference cells containing different reference values corresponding to the different multilevel cell write values may be present (not shown in Fig. 55E).
  • representative memory cell 250a being written is compared to the reference cell 250R current by means of the read circuitry 99a.
  • the reference cell 250R is also being biased at the same bias conditions applied to the selected memory cell 250 during the write operation. Therefore, the write operation needs to be ceased after the desired memory state is achieved to prevent altering the state of the reference cell 250R.
  • the voltage at the bit line 74a can be sensed instead of the cell current.
  • a positive bias is applied to the source line terminal 72a and current is forced through the BL terminal 74a.
  • the voltage of the BL terminal 74a will reflect the state of the memory cell 250a. Initially, when memory cell 250a is in logic-0 state, a large voltage drop is observed across the memory cell 250a and the voltage of the BL terminal 74a will be low. As the current flow through the memory cell 250a increases, hole injection will increase, resulting memory cell 250a to be in logic- 1 state. At the conclusion of the logic- 1 state write operation, the voltage drop across the memory cell 250a will decrease and an increase in the potential of BL terminal 74a will be observed. Atty. Docket: ZENO-012WO
  • the reference cell 250R corresponding to state “01 " is activated.
  • the bias conditions described above are applied both to the selected memory cell 250 and to the "01" reference cell 250R: zero voltage is applied to the source line terminal 72, zero voltage is applied to the substrate terminal 78, a positive voltage is applied to the WL terminal 70 (for the impact ionization mechanism), while the BL terminal 74 is being ramped up, starting from zero voltage. Starting the ramp voltage from a low voltage (i.e. zero volts) ensures that the state of the reference cell 250R does not change.
  • Unselected representative memory cell 250b which shares a row with selected representative memory cell 250a, has its bipolar device 30 turned off because there is no voltage between the collector and emitter terminals. It retains its logic state during the short duration of the multi-level write operation.
  • Unselected representative memory cell 250c which shares a column with selected representative memory cell 250a, is in the holding state. Less base current will flow into the floating body 24 due to the smaller potential difference between SL terminal 72n and BL terminal 74a (i.e. the emitter and collector terminals of the n-p-n bipolar device 30). It also retains its logic state during the short duration of the multi-level write operation.
  • Unselected representative memory cell 250d which shares neither a row nor a column with selected representative memory cell 250a, is in the holding Atty. Docket: ZENO-012WO state. It too retains its logic state during the short duration of the multi-level write operation.
  • multistate mode is self-selecting.
  • the quantity of holes injected into the floating body 24 is proportional to the quantity of holes (i.e., the charge) already present on the floating body 24.
  • each memory cell selects its own correct degree of holding current.
  • Figs. 56 and 57 show gated half transistor memory cell 250V with Fig.
  • Memory cell 250V has a fm structure 52 fabricated on substrate 12, so as to extend from the surface of the substrate to form a three- dimensional structure, with fm 52 extending substantially perpendicular to and above the top surface of the substrate 12.
  • Fin structure 52 is conductive and is built on buried well layer 22 which is itself built on top of substrate 12.
  • buried well 22 could be a diffusion inside substrate 12 with the rest of the fm 52 constructed above it, or buried well 22 could be a conductive layer on top of substrate 12 connected to all the other fm 52 structures in a manner similar to memory cell 350 described above.
  • Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • Buried well layer 22 may be formed by an ion implantation process on the material of substrate 12 which may be followed by an etch so that buried well 22 is above the portion of substrate 12 remaining after the etch.
  • buried well layer 22 may be grown epitaxially above substrate 22 and the unwanted portions may then be etched away.
  • Fin structure 52 includes bit line region 16 having a second conductivity type (such as n-type conductivity type).
  • Memory cell 250V further includes gates 60 on two opposite sides of the floating substrate region 24 Atty. Docket: ZENO-012WO insulated from floating body 24 by insulating layers 62. Gates 60 are insulated from floating body 24 by insulating layers 62. Gates 60 are positioned between the bit line region 16 and the insulating layer 28, adjacent to the floating body 24.
  • the floating body region 24 is bounded by the top surface of the fin 52, the facing side and bottom of bit line region 16, top of the buried well layer 22, and insulating layers 26, 28 and 62.
  • Insulating layers 26 and 28 insulate cell 250V from neighboring cells 250V when multiple cells 250V are joined to make a memory array.
  • Insulating layer 26 insulates adj acent buried layer wells 22, while insulating layer 28 does not.
  • the buried layer 22 is therefore continuous (i.e. electrically conductive) in one direction.
  • the surface 14 of the semiconductor is at the level of the top of the fin structure. As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 250V.
  • an alternate fin structure 52A can be constructed.
  • gates 60 and insulating layers 62 can enclose three sides of the floating substrate region 24. The presence of the gate 60 on three sides allows better control of the charge in floating body region 24.
  • Memory cell 250V can be used to replace memory cell 250 in an array similar to array 280 having similar connectivity between the cells and the array control signal terminals. In such a case, the hold, read and write operations are similar to those in the lateral device embodiments described earlier for memory cell 250 in array 280. As with the other embodiments, the first and second conductivity types can be reversed as a matter of design choice. As with the other embodiments, many other variations and combinations of elements are possible, and the examples described in no way limit the present invention.
  • Figure 58B shows an array 280V of memory cells 250V. Due the nature of fin structure 52A, the most compact layout will typically be with the word lines 70 running perpendicular to the source lines 72, instead of in parallel as in memory array 280 discussed above. This leads to the structure of array 580 where the cell 250V is constructed using fin structure 52A and the source lines 72a through 72p run parallel to the bit lines 74a through 74p and orthogonal to the word lines 70a through 70m. The operation of memory array 280V is Atty.
  • Fig. 59A shows another embodiment of a gated half transistor memory cell 450 (denoted by a dotted line) according to the present invention.
  • Fig. 59B shows a smaller portion of Fig. 59A comprising a single memory cell 450 with two cross section lines ⁇ - ⁇ and ⁇ - ⁇ .
  • Fig. 23C shows the cross section designated I-F in Fig. 59B.
  • Fig. 59D shows the cross section designated ⁇ - ⁇ in Fig. 59B.
  • 59A through 59F are substrate 12, semiconductor surface 14, bit line region 16, buried well layer 22, floating body region 24, insulating layers 26 and 28, gate 60, gate insulator 62, word line terminal 70, buried well terminal 72, bit line terminal 74 and substrate terminal 78, all of which perform similar functions in the exemplary embodiments of memory cell 450 as they did in the exemplary embodiments of memory cell 250 described above.
  • the cell 450 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example.
  • substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • a buried layer 22 of the second conductivity type is provided in the substrate 12. Buried layer 22 is also formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can also be grown epitaxially.
  • bit line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body 24 and is exposed at surface 14.
  • Bit line region 16 is formed by an implantation process formed on the material making up floating body 24, according to any of implantation processes known and typically used in the art. Alternatively, a sohd state diffusion process could be used to form bit line region 16.
  • a floating body region 24 of the substrate 12 is bounded by surface 14, bit line region 16, insulating layers 26 and 28 and buried layer 22.
  • Insulating Atty. Docket: ZENO-012WO layers 26 and 28 may be made of silicon oxide, for example. Insulating layers 26 and 28 insulate cell 450 from neighboring cells 450 when multiple cells 450 are joined in an array 180 to make a memory device as illustrated in Fig. 61A.
  • STI shallow trench isolation
  • Insulating layer 26 insulates both neighboring body regions 24 and buried regions 22 of adjacent cells memory cells 450A, 450, and 450B, while insulating layer 28 insulates neighboring body regions 24, but not neighboring buried layer regions 22, allowing the buried layer 22 to be continuous (i.e. electrically conductive) in one direction in parallel with the ⁇ - ⁇ cut hne as shown in Figs. 59B and 59D. As in other embodiments, there is no contact to the buried layer 22 at the semiconductor surface 14 inside the boundary of memory cell 450.
  • a gate 60 is positioned in between bit hne regions 16 of neighboring cells 450 and 450A and above the surface 14, the floating body regions 24, and one of the adjacent insulating layers 26 as shown in Fig. 59C.
  • the gate terminal 70 is coupled to the gates 60 of both memory cells 450 and 450A.
  • the gate 60 is insulated from surface 14 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. In Figs. 59A, 59B and 59C, the gate 60 is shown above the insulating layer 26 isolating neighboring cells 450 and 450A.
  • Cell 450 further includes word line (WL) terminal 70 electrically
  • bit line (BL) terminal 74 electrically connected to bit line region 16
  • source hne (SL) terminal 72 electrically connected to the buried layer 22
  • substrate terminal 78 electrically connected to substrate 12.
  • contact to buried well region 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 and buried well terminal 72, while contact to substrate region 12 can be made through region 28 having a first conductivity type, and which is electrically connected to substrate region 12 and substrate terminal 78.
  • the SL terminal 72 serves as the back bias terminal for the memory cell 450. Atty. Docket: ZENO-012WO
  • the buried well 22 may also be shared between two adjacent memory cells 450 and 450B not sharing the same WL terminal 70.
  • insulating layer 26A is built to a similar depth as insulating layer 28 allowing this connection to be made using buried well 22.
  • each memory cell 450 shares a source line terminal with one adjacent cell (e.g., 450B) and a word line terminal 70 with another adjacent cell (e.g., 450A). It is worth noting that this connectivity is possible because when memory cells 450 are mirrored in alternate rows when arrayed, while memory cell 50 is not mirrored when arrayed.
  • FIGS 60A through 60E shown an alternate embodiment of memory cell 450 where a part of the gate 60 can also be formed inside a trench adjacent to the floating body regions 24 of two adjacent memory cells 450.
  • the primary difference between this embodiment and the one described in Figures 59A through 59E is that the insulating layers 26 in alternate rows adjacent to the floating body regions 24 and under the gates 60 are replaced with a trench labeled 26T in Figure 60C.
  • This trench can be filled with gate insulator 62 and gate material 60 to form a "T" shaped structure.
  • This allows gate 60 to be adj acent to floating body region 24 on two sides allowing better control of the charge in floating body region 24 in response to electrical signals apphed to gate 60 through word line terminal 70.
  • operations where word line terminal is driven to a positive voltage potential to provide a boost to the voltage potential of the floating body 24 by means of capacitive coupling will benefit from this arrangement since the capacitance between the gate 60 and the floating body 24 will be substantially increased.
  • Fig. 60A shows a top view of one such embodiment of a memory cell
  • Fig. 60B shows a smaller portion of Fig. 60A with two cross section lines ⁇ - ⁇ and ⁇ - ⁇ .
  • Fig. 60C shows the cross section designated ⁇ - ⁇ in Fig. 60B.
  • Fig. 60D shows the cross section designated ⁇ - ⁇ in Fig. 60B.
  • Present in Figs. 60A through 60F are Atty.
  • the cell 450 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example.
  • substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • a buried layer 22 of the second conductivity type is provided in the substrate 12. Buried layer 22 is also formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can also be grown epitaxially.
  • Region 16 is provided in floating body 24 and is exposed at surface 14.
  • Region 16 is formed by an implantation process formed on the material making up floating body 24, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process could be used to form region 16.
  • a floating body region 24 of the substrate 12 is bounded by surface 14, region 16, insulating layers 26, and 28, buried layer 22, and trench 26T.
  • Insulating layers 26 and 28 may be made of silicon oxide, for example. Insulating layers 26 and 28 combined with trench 26T insulate cell 450 from neighboring cells 450 when multiple cells 450 are joined in an array 480 to make a memory device as illustrated in Fig. 61 A. Insulating layer 26 and trench 26T together insulate both neighboring body regions 24 and buried regions 22 of adjacent cells memory cells 450A, 450, and 450B, while insulating layer 28 insulates neighboring body regions 24, but not neighboring buried layer regions 22, allowing the buried layer 22 to be continuous (i.e. electrically conductive) in one direction in parallel with the ⁇ - ⁇ cut line as shown in Figs. 60B and 60D.
  • STI shallow trench isolation
  • a gate 60 is positioned in trench 26T in between bit line regions 16 of neighboring cells 450 and 450A and above the surface 14 over the floating body Atty. Docket: ZENO-012WO regions 24 forming a "T" shaped structure as shown in Fig. 60C.
  • the gate terminal 70 is coupled to the gates 60 of both memory cells 450 and 450A.
  • the gate 60 is insulated from floating body regions 24 by an insulating layer 62 both on surface 14 and along the walls and bottom of trench 26T.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
  • the trench 26T could be formed through silicon etching process similar to the STI formation after the STI 26 and 28 have been formed. Instead of filling the trench 26T with thick oxide, gate oxide 62 could be grown after the trench etch, followed by gate 60 formation.
  • Cell 450 further includes word line (WL) terminal 70 electrically
  • bit line (BL) terminal 74 electrically connected to region 16
  • source line (SL) terminal 72 electrically connected to the buried layer 22
  • substrate terminal 78 electrically connected to substrate 12.
  • contact to buried well region 22 can be made through region 20 having a second conductivity type, and which is electrically connected to buried well region 22 and buried well terminal 72, while contact to substrate region 12 can be made through region 28 having a first conductivity type, and which is electrically connected to substrate region 12 and substrate terminal 78.
  • the SL terminal 72 serves as the back bias terminal for the memory cell 450.
  • the buried well 22 may also be shared between two adjacent memory cells 450 and 450B not sharing the same WL terminal 70.
  • insulating layer 26A is built to a similar depth as insulating layer 28 allowing this connection to be made using buried well 22.
  • each memory cell 450 shares a source line terminal with one adjacent cell (e.g., 450B) and a word line terminal 70 with another Atty. Docket: ZENO-012WO adjacent cell (e.g., 450A). It is worth noting that this connectivity is possible because when memory cells 450 are mirrored in alternate rows when arrayed, while memory cell 50 is not mirrored when arrayed.
  • the first and second conductivity types may be reversed as a matter of design choice.
  • Other physical geometries may be used like, for example, substrate 12 may be replaced by a well placed in a substrate of the second conductivity type (not shown) as a matter of design choice.
  • the embodiments shown are in no way limiting of the present invention.
  • Fig 61 A shows an exemplary memory array 480 of memory cells 450.
  • an embodiment of memory cell 450 is chosen where word lines 70a through 70n are shared between adj acent rows of memory cells 450 and source lines 72a through 72n+l are shared between adj acent rows of memory cells 450 offset by one row.
  • word lines 70a through 70n are shared between adj acent rows of memory cells 450 and source lines 72a through 72n+l are shared between adj acent rows of memory cells 450 offset by one row.
  • word lines 70a through 70n are shared between adj acent rows of memory cells 450 and source lines 72a through 72n+l are shared between adj acent rows of memory cells 450 offset by one row.
  • word lines 70a through 70n are shared between adj acent rows of memory cells 450 and source lines 72a through 72n+l are shared between adj acent rows of memory cells 450 offset by one row.
  • the WL terminals 70a through 70n and source line terminals 72a through 72n+ 1 can
  • FIG. 6 IB the circuit schematic for an individual memory cell 450 is identical to that for memory cell 250 as shown in Fig. 37A, the main differences between memory cells 250 and 450 being the physical construction, relative orientation, and the sharing of control lines.
  • the operating principles of memory cell 450 will follow the principles of the previously described memory cell 250.
  • the memory cell operations will be described, realizing that the WL and SL terminals are now shared between neighboring memory cells .
  • Persons of ordinary skill in the art will realize the operation of the embodiments of memory cell 450 which share word lines 70 but have separate Atty. Docket: ZENO-012WO source lines 72 can be handled identically by manipulating the non-shared source lines 72 identically or by manipulating them in an analogous manner to other rows in the memory array as a matter of design choice.
  • the holding operation for memory cell 450 can be performed in a similar manner to that for memory cell 250 by applying a positive bias to the back bias terminal (i.e. SL terminal 72 coupled to buried well region 22) while grounding bit line terminal 74 coupled to bit line region 16 and substrate terminal 78 coupled to substrate 12.
  • the holding operation is relatively independent of the voltage apphed to terminal 70 which is preferably grounded in some embodiments.
  • Inherent in the memory cell 450 is n-p-n bipolar device 30 formed by buried well region 22, floating body 24, and bit line region 16.
  • bipolar transistor 30 formed by bit line region 16, floating body 24, and buried well region 22 will be turned on as discussed above in conjunction with Figs. 37A through 37C above. A fraction of the bipolar transistor current will then flow into floating body region 24 (usually referred to as the base current) and maintain the logic- 1 data.
  • the efficiency of the holding operation can be enhanced by designing the bipolar device formed by buried well region 22, floating region 24, and bit line region 16 to be a low-gain bipolar device, where the bipolar gain is defined as the ratio of the collector current flowing out of SL terminal 72 to the base current flowing into the floating region 24.
  • a periodic pulse of positive voltage can be applied to the SL terminal 72 as opposed to applying a constant positive bias to reduce the power consumption of the memory cell 450 in a manner analogous to that described in conjunction with Figs. 38A through 38D above.
  • exemplary memory array 480 As illustrated in Fig. 62, an example of the bias condition for a two row holding operation is applied to exemplary memory array 480. In one particular non-limiting embodiment, about +1.2 volts is apphed to SL terminal 72b, about Atty. Docket: ZENO-012WO
  • 0.0 volts is applied to the other source line terminals 72a and 72c (not shown) through 72n+l, about 0.0 volts is applied to BL terminals 74a through 74p, about 0.0 volts is applied to WL terminals 70a through 7 On, and about 0.0 volts is applied to substrate terminals 78a through 78n+ 1. This will place
  • the charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 450. If cell 450 is in a state logic-1 having holes in the body region 24, then the memory cell will have a higher cell current, compared to if cell 450 is in a state logic-0 having no holes in body region 24.
  • a sensing circuit typically connected to BL terminal 74 of memory array 480 can then be used to determine the data state of the memory cell. Examples of the read operation are described with reference to Yoshida, Ohsawa-1, and Ohsawa-2 discussed above.
  • the read operation can be performed by applying the following bias condition to memory cell 450: a positive voltage is applied to the selected BL terminal 74, and a positive voltage greater than the positive voltage applied to the selected BL terminal 74 is applied to the selected WL terminal 70, zero voltage is applied to the selected SL terminal 72, and zero voltage is applied to the substrate terminal 78.
  • the unselected BL terminals will remain at zero voltage, the unselected WL terminals will remain at zero voltage, and the unselected SL terminals will remain at positive voltage.
  • the bias conditions for an exemplary embodiment for a read operation for the exemplary memory array 480 are shown in Fig. 63, while the bias conditions during a read operation for selected representative memory cell 450a are further illustrated in Figs. 64A through 64B and the bias conditions during a read operation for the seven cases illustrated by unselected representative memory cells 450b through 450h during read operations are further shown in Figs. 64C through 64P.
  • the bias conditions for unselected representative memory cell 450b sharing the same WL terminal 70a and BL terminal 74a but not the same SL terminal 72 as the selected representative memory cell 450a are shown in Figs. 64C through 64D.
  • the bias conditions for Atty is shown in Fig. 63, while the bias conditions during a read operation for selected representative memory cell 450a are further illustrated in Figs. 64A through 64B and the bias conditions during a read operation for the seven cases illustrated by unselected representative memory cells 450b through 450h during read operations are further shown in Figs. 64C through 64P
  • Figs. 64E through 64F The bias conditions for unselected representative memory cell 450d sharing the same WL terminal 70a and SL terminal 72b but not the same BL terminal 74 as the selected representative memory cell 450a are shown in Figs. 64G through 64H.
  • Figs. 641 through 64J show the bias conditions for unselected representative memory cell 450e sharing the same WL terminal 70a but neither the same SL terminal 72 nor BL terminal 74 as the selected representative memory cell 450a.
  • 64K through 64L show the bias conditions for unselected representative memory cell 450f sharing the same SL terminal 72b but neither the same WL terminal 70 nor BL terminal 74 as the selected representative memory cell 450a.
  • the bias conditions for unselected representative memory cell 450g sharing the same BL terminal 74a as the selected representative memory cell 450a but not the same WL terminal 70 nor SL terminal 72 is shown in Figs. 64M through 64N.
  • the bias condition for representative memory cell 450h not sharing any control terminals as the selected representative memory cell 450a is shown in Figs. 640 through 64P.
  • Figs. 63, 64A and 64B the bias conditions for selected representative memory cell 450a and are shown.
  • about 0.0 volts is apphed to the selected SL terminal 72b
  • about +0.4 volts is apphed to the selected bit hne terminal 74a
  • about + 1.2 volts is applied to the selected word line terminal 70a
  • about 0.0 volts is applied to substrate terminal 78 (not shown in Fig. 64B).
  • Figs. 64C through 64P show in more detail the unselected representative memory cells 450b-450h in memory array 480. It is noteworthy that these voltage levels are exemplary only may vary substantially as a matter of design choice and processing technology node, and are in no way limiting. Atty. Docket: ZENO-012WO
  • a two row write logic-0 operation of the cell 450 is now described with reference to Fig. 65.
  • a negative bias may be applied to the back bias terminal (i.e. SL terminal 72), zero potential may be applied to WL terminal 70, zero voltage may be applied to BL terminal 72 and substrate terminal 78.
  • the unselected SL terminal 72 will remain positively biased.
  • the p-n junction between floating body 24 and buried well 22 of the selected cell 50 is forward-biased, evacuating any holes from the floating body 24.
  • about -0.5 volts is applied to terminal 72
  • about 0.0 volts is applied to terminal 70
  • about 0.0 volts is applied to terminal 74 and 78.
  • these voltage levels may vary, while maintaining the relative relationship between the charges applied, as described above.
  • the selected SL terminal 72b is biased at about -0.5V while the unselected SL terminals 72a, and 72c (not shown) through 72n+l are biased at about +1.2V, the WL terminals 70a through 70n are biased at about 0.0V, the BL terminals 74a through 74p are biased at about 0.0V and the substrate terminals 78a through 78n+l are biased at about 0.0V.
  • the substrate terminals may be biased at about -0.5V to avoid unwanted current from the selected SL terminal 72b. This condition causes all of the memory cells 450 coupled to SL terminal 72b, including the selected representative memory cells 450a, 450c, 450d, and 450f, to be written to the logic-0 state.
  • Figs. 65, 66A and 66B show an example of bias conditions for the
  • the negative bias applied to SL terminal 72 causes large potential difference between floating body 24 and buried well region 22. This causes the hole charge in the floating body 24 to be discharged as discussed above. Because the buried well 22 is Atty. Docket: ZENO-012WO shared among multiple memory cells 50, all memory cells 450 sharing the same SL terminal 72 will be written into state logic-0.
  • Figs. 66A through 66B illustrating the intrinsic n-p-n bipolar devices 30 of unselected memory cells 450, including representative memory cells 450b, 450e, 450g and 450h, during write logic-0 operations are illustrated in Figs. 66A through 66B. Since the write logic-0 operation only involves a negative voltage to the selected SL terminal 72, the bias conditions for all the unselected cells are the same. As can be seen, the unselected memory cells will be in a holding operation, with the BL terminal at about 0.0 volts, WL terminal at zero or negative voltage, and the unselected SL terminal positively biased.
  • a single column write logic-0 operation can be performed by applying a negative bias to the BL terminal 74 as opposed to the SL terminal 72 (as in Figs. 65, 66A, and 66B).
  • the SL terminal 72 will be positively biased, while zero voltage is applied to the substrate terminal 78, and zero voltage is applied to the WL terminal 70. Under these conditions, all memory cells sharing the same BL terminal 74 will be written into state logic-0 while all the other memory cells 450 in the array 480 will be in the holding state.
  • selected BL terminal 74a may be biased at about -1.2V while the unselected BL terminals 74b through 74p may be biased at about 0.0V, the WL terminals 70a through 70n may be biased at about 0.0V, the source line terminals 72a through 27n+l may be biased at + 1.2V, and the substrate terminals 78a through 78n+l may be biased at 0.0V.
  • This condition causes all of the memory cells 450 coupled to BL terminal 74a, including the selected representative memory cells 450a, 450b, 450c, and 450g, to be written to the logic-0 state while the remaining memory cells 450, including unselected representative memory cells 450d, 450e, 450f, and 450h, to be in a holding operation.
  • These voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.
  • a single cell write logic-0 operation that allows for individual bit writing can be performed by applying a positive voltage to WL terminal 70, a negative voltage to BL terminal 74, zero or Atty. Docket: ZENO-012WO positive voltage to SL terminal 72, and zero voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction between floating body 24 and bit line region 16 is forward-biased, evacuating any holes from the floating body 24.
  • the applied potential can be optimized as follows: if the floating body 24 potential of state logic- 1 is referred to VFBI, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by VFBI/2 while -VFBI/2 is applied to BL terminal 74.
  • the following bias conditions are applied to the selected memory cell 450a: a potential of about 0.0 volts to SL terminal 72b, a potential of about -0.2 volts to BL terminal 74a, a potential of about +0.5 volts is applied to WL terminal 70a, and about 0.0 volts is applied to substrate terminals 78a through 78n+l; while about +1.2 volts is applied to unselected SL terminals 72a and 72c (not shown) through 72n+l, about 0.0 volts is applied to unselected BL terminals 74b through 74p, and about 0.0 volts is applied to unselected WL terminals 70b through 70n.
  • Fig. 68 shows the bias condition for the selected and unselected memory cells 450 in memory array 480.
  • these voltage levels are exemplary only may vary substantially from embodiment to embodiment as a matter of design choice and processing technology node used, and are in no way limiting.
  • the unselected memory cells 450 during write logic-0 operations are shown in Figs. 69C through 69P:
  • the bias conditions for memory cell 450b Atty. Docket: ZENO-012WO sharing the same WL terminal 70a and BL terminal 74a but not the same SL terminal 72 as the selected memory cell 450a are shown in Figs. 69C through 69D.
  • the bias conditions for memory cell 450c sharing the same SL terminal 72b and BL terminal 74a but not the same WL terminal 70 as the selected memory cell 450a are shown in Figs. 69E through 69F.
  • Figs. 69G through 69H The bias conditions for memory cell 450d sharing the same WL terminal 70a and SL terminal 72b but not the same BL terminal 74 as the selected memory cell 450 are shown in Figs. 69G through 69H.
  • Figs. 691 through 69J show the bias conditions for memory cell 450e sharing the same WL terminal 70a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450a.
  • Figs. 69K through 69L show the bias conditions for memory cell 450f sharing the same SL terminal 72b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450a.
  • bias conditions for memory cells sharing the same BL terminal 74a as the selected memory cell 450a but not the same WL terminal 70 nor SL terminal 72 are shown in Figs. 69M through 69N, while the bias condition for memory cells not sharing the same WL, SL, and BL terminals 70, 72, and 74 respectively as the selected memory cell 450a (e.g. memory cell 450h) is shown in Fig. 690 through 69P.
  • the floating body 24 potential of memory cells sharing the WL terminal 70 as the selected memory cell will increase due to capacitive coupling from WL terminal 70 by AVEB .
  • the increase in the floating body 24 potential is not sustainable as the forward bias current of the p- n diodes formed by floating body 24 andjunction 16 will evacuate holes from floating body 24.
  • the floating body 24 potential will return to the initial state logic-0 equilibrium potential.
  • the floating body 24 potential will initially also increase by AVFB, which will result in holes being evacuated from floating body 24. After the positive bias on the WL terminal 70 is removed, the floating body 24 potential will decrease by AVEB .
  • the WL potential needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic-1 is not too Atty. Docket: ZENO-012WO large. For example, the maximum floating body potential due to the coupling from the WL potential cannot exceed VEB I/2.
  • a negative bias is applied to the BL terminal while the SL terminal is positively biased.
  • the potential difference between the BL and SL terminals i.e. the emitter and collector terminals of the bipolar device 30
  • the forward bias current of the p-n diode formed by floating body 24 and bit line region 16 is balanced by higher base current of the bipolar device 30.
  • memory cell 450b will still be at holding mode.
  • memory cell 450b when memory cell 450b is in state logic- 1 it will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24, and when memory cell 450b is in state logic-0 the bipolar device 30 will remain off leaving the floating body 24 charge level in a neutral state.
  • the SL terminal 72 is now grounded with the BL terminal now negatively biased.
  • the p-n diode formed between floating body 24 and bit line region 16 will be forward biased.
  • the increase in the floating body 24 potential will not change the initial state logic-0 as there is initially no hole stored in the floating body 24.
  • the net effect is that the floating body 24 potential after write logic-0 operation will be reduced. Therefore, the BL potential also needs to be optimized such that the decrease in floating body potential of memory cells 50 in state logic- 1 is not too large.
  • the -VFBI/2 is applied to the BL terminal 74.
  • the bipolar device 30 remains off leaving the cell in the logic-0 state.
  • both the SL Atty. Docket: ZENO-012WO terminal 72 and BL terminal 74 are now grounded.
  • ZENO-012WO terminal 72 and BL terminal 74 are now grounded.
  • there is no potential difference between the emitter and collector terminals of the n-p-n bipolar device 30 and consequently memory cells 450d is no longer in holding mode.
  • write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
  • both the SL terminal 72 and BL terminal 74 are grounded.
  • write operation is accomplished much faster (in the order of nanoseconds) compared to the lifetime of the charge in the floating body 24 (in the order of milliseconds), it should cause little disruptions to the charge stored in the floating body.
  • memory cell 450g will still be at holding mode.
  • memory cells in state logic- 1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate hole current to replenish the charge in floating body 24, while memory cells in state logic-0 will remain in neutral state.
  • both the SL terminal 72 will remain positively charged and the BL terminal will remain grounded.
  • these cells will be at holding mode, where memory cells in state logic-1 will maintain the charge in floating body 24 because the intrinsic bipolar device 30 will generate holes current to replenish the charge in floating body 24, while memory cells in state logic-0 will remain in neutral state.
  • a write logic-1 operation can be performed on memory cell 450 by
  • FIG. 70 Illustrated in Fig. 70, is an example of the bias condition of the selected memory cell 450a in memory array 480 under a band-to-band tunnehng (GIDL) write logic-1 operation.
  • the negative bias applied to the WL terminal 70a and the positive bias applied to the BL terminal 74a of the selected representative memory cell 450a result in hole injection to the floating body 24 of the selected memory cell 450 as discussed above with reference to Yoshida.
  • the SL terminal 72 and the substrate terminal 78 are grounded during the write logic- 1 operation.
  • the following bias conditions are applied to the selected memory cell 450a: a potential of about 0.0 volts is applied to SL terminal 72b, a potential of about +1.2 volts is applied to BL terminal 74a, a potential of about -1.2 volts is applied to WL terminal 70a, and about 0.0 volts is applied to substrate Atty. Docket: ZENO-012WO terminal 78 (not shown in Fig. 71B).
  • This bias condition bends the energy bands upward in the portion of bit line region 16 near the gate 60 in selected representative memory cell 450a creating GIDL current on the bit line
  • Fig. 70 the following bias conditions are apphed to the unselected terminals: about + 1.2 volts is apphed to unselected SL terminals 72a and 72c (not shown) through 72n+l, about 0.0 volts is applied to unselected BL terminals 74b through 74p, a potential of about 0.0 volts is applied to unselected WL terminals 70 b through 70n+l, and about 0.0 volts is applied to substrate terminals 78a through 78n+l .
  • the unselected memory cells during write logic- 1 operations are shown in Figs. 71C through 710:
  • the bias conditions for memory cell 450b sharing the same WL terminal 70a and BL terminal 74a but not the same SL terminal 72 as the selected memory cell 450a are shown in Figs. 71C through 7 ID.
  • the bias conditions for memory cell 450c sharing the same SL terminal 72b and BL terminal 74a but not the same WL terminal 70 as the selected memory cell 450a are shown in Figs. 71E through 71F.
  • the bias conditions for memory cell 450d sharing the same WL terminal 70a and SL terminal 72b but not the same BL terminal 74 as the selected memory cell 450a are shown in Figs.
  • Figs. 711 through 71 J show the bias conditions for memory cell 450e sharing the same WL terminal 70a but not the same SL terminal 72 nor BL terminal 74 as the selected memory cell 450a.
  • Figs. 71 K through 71 L show the bias conditions for memory cell 450f sharing the same SL terminal 72b but not the same WL terminal 70 nor BL terminal 74 as the selected memory cell 450a.
  • the bias conditions for memory cells sharing the same BL terminal 74a as the selected memory cell 450a but not the same WL terminal 70 nor S L terminal 72 are shown in Figs.

Abstract

L'invention concerne une cellule de mémoire à semi-conducteurs comprenant une région de corps flottant configurée pour être chargée jusqu'à un niveau indiquant un état de la cellule de mémoire ; une première région en contact électrique avec ladite région de corps flottant ; une deuxième région en contact électrique avec ladite région de corps flottant et espacée de ladite première région ; et une grille positionnée entre ladite première et ladite deuxième région. La cellule peut être une cellule multiniveau. L'invention concerne également des réseaux de cellules de mémoire pour fabriquer un dispositif de mémoire, ainsi que des procédés de fonctionnement de cellules de mémoire.
EP11740503.5A 2010-02-07 2011-02-07 Dispositif de mémoire à semi-conducteurs comportant un transistor à corps électriquement flottant, dispositif de mémoire à semi-conducteurs ayant une fonction volatile et non volatile, et procédé de fonctionnement associé Ceased EP2532005A4 (fr)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US30212910P 2010-02-07 2010-02-07
US30958910P 2010-03-02 2010-03-02
US12/797,320 US8130548B2 (en) 2007-11-29 2010-06-09 Semiconductor memory having electrically floating body transistor
US12/797,334 US8130547B2 (en) 2007-11-29 2010-06-09 Method of maintaining the state of semiconductor memory having electrically floating body transistor
US12/897,516 US8547756B2 (en) 2010-10-04 2010-10-04 Semiconductor memory device having an electrically floating body transistor
US12/897,528 US8514622B2 (en) 2007-11-29 2010-10-04 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
US12/897,538 US8264875B2 (en) 2010-10-04 2010-10-04 Semiconductor memory device having an electrically floating body transistor
US201061425820P 2010-12-22 2010-12-22
PCT/US2011/023947 WO2011097592A1 (fr) 2010-02-07 2011-02-07 Dispositif de mémoire à semi-conducteurs comportant un transistor à corps électriquement flottant, dispositif de mémoire à semi-conducteurs ayant une fonction volatile et non volatile, et procédé de fonctionnement associé

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EP2532005A4 EP2532005A4 (fr) 2016-06-22

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EP (1) EP2532005A4 (fr)
CN (1) CN107293322B (fr)
IN (1) IN2012DN06399A (fr)
SG (2) SG182538A1 (fr)
TW (3) TWI566243B (fr)
WO (1) WO2011097592A1 (fr)

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