EP2345069A1 - Biocompatible electrodes - Google Patents

Biocompatible electrodes

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Publication number
EP2345069A1
EP2345069A1 EP09756821A EP09756821A EP2345069A1 EP 2345069 A1 EP2345069 A1 EP 2345069A1 EP 09756821 A EP09756821 A EP 09756821A EP 09756821 A EP09756821 A EP 09756821A EP 2345069 A1 EP2345069 A1 EP 2345069A1
Authority
EP
European Patent Office
Prior art keywords
metal
electrode
layer
semiconductor device
etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP09756821A
Other languages
German (de)
French (fr)
Other versions
EP2345069B1 (en
Inventor
Roel Daamen
Matthias Merz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
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Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Priority to EP09756821.6A priority Critical patent/EP2345069B1/en
Publication of EP2345069A1 publication Critical patent/EP2345069A1/en
Application granted granted Critical
Publication of EP2345069B1 publication Critical patent/EP2345069B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation

Definitions

  • the invention relates to biocompatible electrodes and to a method of making them.
  • Electrodes for biological applications increasingly need to be included in semiconductor devices manufactured with modern semiconductor processing, especially complementary metal oxide semiconductor (CMOS) devices manufactured using CMOS processing techniques.
  • CMOS complementary metal oxide semiconductor
  • An existing process for manufacturing an electrode for a biosensor is described in Eversmann et al, CMOS Biosensor Array for Extracellular Recording of Neural Activity, IEEE Journal of Sol id-State Circuits, volume 38 number 12 (December 2003), After completing a standard CMOS process to form devices, two metal layers, with a nitride passivation and a tungsten via, an additional process is used to form the additional sensor electrode.
  • the surface is planarised, and a 50nm thick Ti/Pt stack is deposited and patterned using a liftoff process. The stack is used both as the sensor electrodes and as an adhesion layer for the bond pads.
  • a 40nm sensor dielectric of TiO 2 , ZrO 2 , TiO 2 , ZrO 2 , and TiO 2 is formed by sputtering to protect the biocompatible electrode. The sensor dielectric is removed over the bond pads.
  • the conventional CMOS process is used and ends with a nitride passivation layer over a silicon dioxide layer.
  • a via is formed to the top layer of metallization, and filled with a Ti/TiN barrier layer and tungsten.
  • a CMP process is used to etch back to the nitride passivation layer.
  • a Cr adhesion layer is followed by a Pt electrode layer and patterned using a lift-off process.
  • TiO 2 and/or ZrO 2 are then deposited by sputtering. At the contact pads, but not the biocompatible electrodes, the TiO 2 is etched away and a gold contact evaporated.
  • the biocompatible electrode is formed with no lithography steps at all (after forming the via) and so the process is cheaper than those proposed before.
  • the inventors have realized that a further problem occurs with the lithography step used to pattern the biocompatible electrode in the prior art approaches discussed above. If the lithography is slightly misaligned with the contact then some of the contact may be exposed after the manufacture of the electrode which can lead to contamination issues. In contrast, using the method proposed, the method is self aligned. This minimises contamination and overlay issues.
  • the method is compatible with modern CMOS processes, including both processes with copper-based interconnects and aluminium-based interconnects.
  • a further benefit is that the electrode is completely planar. This avoids stress at corners where subsequent dielectrics are deposited, improving reliability.
  • the invention also relates to a semiconductor device according to claim 6.
  • Figures 1 to 6 illustrate steps in the manufacture of a semiconductor device according to a first embodiment of the invention
  • Figures 7 and 8 illustrate steps in the manufacture of a semiconductor device according to a second embodiment of the invention
  • FIG. 9 illustrates a semiconductor device according to a third embodiment of the invention.
  • the figures are not to scale. Like or similar components are given the same reference numbers in the different Figures, and the corresponding description is not repeated.
  • CMOS process results in a semiconductor device having a substrate 10 with transistors and other devices formed within and on it. For clarity, these are not shown.
  • a number of interconnection layers are then formed.
  • a first interconnection layer is formed of insulator 12, typically silicon dioxide, having a via 14 formed through the insulator filled with a plug 16, here tungsten.
  • a first layer of aluminium interconnect 18 is provided above the plug 16. The aluminium interconnect 18 extends across the substrate 10.
  • a second interconnection layer is formed in the same way, namely with insulator 22, via 24, plug 26 and interconnect 28.
  • the interconnect 28 in the second layer is the highest level of interconnect and so will be referred to as the upper interconnect layer.
  • a passivation layer 30 is then formed over the second interconnection layer with upper surface 31.
  • the passivation layer 30 is insulating, and may be of silicon dioxide, silicon nitride, silicon carbide or a combination.
  • the passivation layer is in fact a stack of SiC, followed by SiO 2 followed by Si3N 4 ; this stack may be referred to as the passivation stack. This results in the arrangement shown in Figure 1.
  • Processing to form the biocompatible electrode then begins by forming a via 32 through the passivation layer to the upper interconnect layer 28. This involves a lithographic step, to define the via. Typically, photoresist may be deposited and patterned to expose part of the passivation layer and a dry etching step carried out to etch through to the aluminium. Then, the photoresist is removed, as illustrated in Figure 2.
  • a barrier layer 34 is then deposited over the whole surface of passivation layer 30 and in the via 32, using a process with good step coverage.
  • the barrier layer 34 may be, for example a Ti/TiN barrier layer or a Ti/W barrier layer, both of which are fully compatible with CMOS processing.
  • filling metal 36 in the embodiment tungsten, is deposited over the whole surface, including in the via 34.
  • a conventional chemical mechanical polishing (CMP) step using a CMP tool then planarises the surface by etching and polishing away the filling metal 36 and barrier layer 34 above the passivation layer 30, leaving the barrier layer 34 and filling metal present only in the via. This step leaves the top of the filling metal plug 36 level with the top of the passivation layer 30 as illustrated in Figure 3.
  • CMP chemical mechanical polishing
  • a further selective etch is then carried out to etch away the filling metal in the via, creating a recess 38 as illustrated in Figure 4, below the level of the upper surface 31.
  • the selective etch does not etch away the barrier layer 34.
  • the particular etch selected in the embodiment is a H 2 O 2 (hydrogen peroxide) etch. Normally, this would give a low etch rate which would reduce the process speed excessively.
  • the H 2 O 2 is supplied in the CMP tool previously used for the CMP step.
  • the use of the CMP tool allows constant fresh H 2 O 2 to be delivered to the surface of the wafer and allows constant removal of the dissolved W.
  • the inventors have accordingly been able to achieve etch rates of 90nm/min and up using this H 2 O 2 etch, much higher than would be expected by a conventional wet etch step using H 2 O 2 .
  • the use of the same tool as in the previous step is extremely efficient since it does not require moving the device at all.
  • the electrode metal 40 is deposited over the full surface of the device, including over the passivation layer 30 and in the recess 38, as illustrated in Figure 5.
  • the electrode metal may be a single layer, for example of Ta or Ti, a nitride for example TaN or TiN, or a multilayer for example Ta/TaN or Ti/TiN.
  • Another CMP process is used to etch and/or polish away the electrode metal 40 from above the passivation layer 30 and hence to leave the electrode metal only in the recess 38 at the top of the via, flush (level) with the surface of the passivation layer 30 as shown in Figure 6, forming the finished electrode 42.
  • a biocompatible dielectric layer 44 is then deposited over the complete surface.
  • the dielectric layer may be, for example, of TiO 2 , Ta 2 O 5 , SiO 2 , SiN or HfO 2 or combinations of these or other materials.
  • a damascene process is used to form the biocompatible electrode in the recess at the top of the via.
  • This process is a self-aligned process and this therefore ensures that the electrode 42 has exactly the same dimensions as the underlying W contact. This avoids the possibility of contamination caused by misalignment of the biocompatible electrode and the plug.
  • Figures 7 and 8 illustrate a second embodiment.
  • the method of manufacturing a semiconductor device according to the second embodiment proceeds in the same way as in the first embodiment to the stage illustrated in Figure 3.
  • the next step is to carry out a selective etch to form recess 38, but in the process illustrated with reference to Figures 7 and 8 the selective etch etches both the barrier layer 34 and the filling metal 36 to form recess 38.
  • Processing then proceeds as in the first embodiment to form electrode 42 and dielectric 44 to result in the finished semiconductor device illustrated in Figure 8.
  • Figure 9 illustrates a third embodiment using a copper interconnect.
  • the manufacture proceeds essentially as in the embodiment of Figure 1 to 6, except that the material of the first and second interconnects 18, 28 is copper.
  • the second interconnect 28 is used to fill additionally the second via 24 and there is no separate plug in the second interconnect layer (this is the so-called dual damascene processing).
  • the material of the filling metal 36 is also copper.
  • the choices for the barrier layer 34 include not merely Ti or TiN but Ta, or TaN/Ta.
  • a Cu filling metal 36 is used with copper interconnects, other possibilities for filling metal 36 exist, such as tungsten.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A biocompatible electrode is manufactured by depositing filling metal 36 and etching back the filling metal to the surface of the surrounding insulator 30. Then, a further etch forms a recess 38 at the top of the via 32. An electrode metal 40 is then deposited and etched back to fill the recess 38 and form biocompatible electrode 42. In this way, a planar biocompatible electrode is achieved. The step of etching to form the recess may be carried out in the same CMP tool as is used to etch back the filling metal 36. A hydrogen peroxide etch may be used.

Description

DESCRIPTION
BIOCOMPATIBLE ELECTRODES
The invention relates to biocompatible electrodes and to a method of making them.
Electrodes for biological applications increasingly need to be included in semiconductor devices manufactured with modern semiconductor processing, especially complementary metal oxide semiconductor (CMOS) devices manufactured using CMOS processing techniques.
An existing process for manufacturing an electrode for a biosensor is described in Eversmann et al, CMOS Biosensor Array for Extracellular Recording of Neural Activity, IEEE Journal of Sol id-State Circuits, volume 38 number 12 (December 2003), After completing a standard CMOS process to form devices, two metal layers, with a nitride passivation and a tungsten via, an additional process is used to form the additional sensor electrode. The surface is planarised, and a 50nm thick Ti/Pt stack is deposited and patterned using a liftoff process. The stack is used both as the sensor electrodes and as an adhesion layer for the bond pads. A 40nm sensor dielectric of TiO2 , ZrO2, TiO2, ZrO2, and TiO2 is formed by sputtering to protect the biocompatible electrode. The sensor dielectric is removed over the bond pads.
An alternative process for the manufacture of electrodes is proposed in Franz Hofmann et al, Technology Aspects of a CMOS Neuro-Sensor: Back End Process and Packaging, 33rd European conference on European Solid-State Device Research, 2003, 16-18 September 2003, pages 167 to 170.
In this process, the conventional CMOS process is used and ends with a nitride passivation layer over a silicon dioxide layer. Then, to manufacture the electrodes a via is formed to the top layer of metallization, and filled with a Ti/TiN barrier layer and tungsten. Then, a CMP process is used to etch back to the nitride passivation layer. A Cr adhesion layer is followed by a Pt electrode layer and patterned using a lift-off process. TiO2 and/or ZrO2 are then deposited by sputtering. At the contact pads, but not the biocompatible electrodes, the TiO2 is etched away and a gold contact evaporated.
A downside with both of these processes is that additional lithography and etching steps are required to manufacture the biocompatible electrodes which leads to expensive manufacturing costs.
Further, the use of some metals are not compatible with modern CMOS processing. This applies in particular to platinum and gold. In particular, processing using platinum is normally only possible in older fabs intended for bipolar processing with wafer diameters up to 6 inch. Accordingly, there is a need for alternative processes for manufacturing biocompatible electrodes which is compatible with CMOS processing.
According to the invention there is provided a method according to claim 1.
By using the method according to the invention, the biocompatible electrode is formed with no lithography steps at all (after forming the via) and so the process is cheaper than those proposed before.
The inventors have realized that a further problem occurs with the lithography step used to pattern the biocompatible electrode in the prior art approaches discussed above. If the lithography is slightly misaligned with the contact then some of the contact may be exposed after the manufacture of the electrode which can lead to contamination issues. In contrast, using the method proposed, the method is self aligned. This minimises contamination and overlay issues.
The method is compatible with modern CMOS processes, including both processes with copper-based interconnects and aluminium-based interconnects. A further benefit is that the electrode is completely planar. This avoids stress at corners where subsequent dielectrics are deposited, improving reliability.
The invention also relates to a semiconductor device according to claim 6.
Embodiments of the invention will now be described, purely by way of example, with reference to the accompanying drawings, in which:
Figures 1 to 6 illustrate steps in the manufacture of a semiconductor device according to a first embodiment of the invention; Figures 7 and 8 illustrate steps in the manufacture of a semiconductor device according to a second embodiment of the invention; and
Figure 9 illustrates a semiconductor device according to a third embodiment of the invention. The figures are not to scale. Like or similar components are given the same reference numbers in the different Figures, and the corresponding description is not repeated.
Referring to Figure 1 , a conventional CMOS process results in a semiconductor device having a substrate 10 with transistors and other devices formed within and on it. For clarity, these are not shown.
A number of interconnection layers are then formed. A first interconnection layer is formed of insulator 12, typically silicon dioxide, having a via 14 formed through the insulator filled with a plug 16, here tungsten. A first layer of aluminium interconnect 18 is provided above the plug 16. The aluminium interconnect 18 extends across the substrate 10.
Similarly, a second interconnection layer is formed in the same way, namely with insulator 22, via 24, plug 26 and interconnect 28. In the embodiment, the interconnect 28 in the second layer is the highest level of interconnect and so will be referred to as the upper interconnect layer.
A passivation layer 30 is then formed over the second interconnection layer with upper surface 31. The passivation layer 30 is insulating, and may be of silicon dioxide, silicon nitride, silicon carbide or a combination. In the preferred embodiment, the passivation layer is in fact a stack of SiC, followed by SiO2 followed by Si3N4; this stack may be referred to as the passivation stack. This results in the arrangement shown in Figure 1.
Processing to form the biocompatible electrode then begins by forming a via 32 through the passivation layer to the upper interconnect layer 28. This involves a lithographic step, to define the via. Typically, photoresist may be deposited and patterned to expose part of the passivation layer and a dry etching step carried out to etch through to the aluminium. Then, the photoresist is removed, as illustrated in Figure 2. A barrier layer 34 is then deposited over the whole surface of passivation layer 30 and in the via 32, using a process with good step coverage. The barrier layer 34 may be, for example a Ti/TiN barrier layer or a Ti/W barrier layer, both of which are fully compatible with CMOS processing. Then, filling metal 36, in the embodiment tungsten, is deposited over the whole surface, including in the via 34. A conventional chemical mechanical polishing (CMP) step using a CMP tool then planarises the surface by etching and polishing away the filling metal 36 and barrier layer 34 above the passivation layer 30, leaving the barrier layer 34 and filling metal present only in the via. This step leaves the top of the filling metal plug 36 level with the top of the passivation layer 30 as illustrated in Figure 3.
A further selective etch is then carried out to etch away the filling metal in the via, creating a recess 38 as illustrated in Figure 4, below the level of the upper surface 31. In this embodiment, the selective etch does not etch away the barrier layer 34.
The particular etch selected in the embodiment is a H2O2 (hydrogen peroxide) etch. Normally, this would give a low etch rate which would reduce the process speed excessively. However, in the embodiment the H2O2 is supplied in the CMP tool previously used for the CMP step. The use of the CMP tool allows constant fresh H2O2 to be delivered to the surface of the wafer and allows constant removal of the dissolved W. The inventors have accordingly been able to achieve etch rates of 90nm/min and up using this H2O2 etch, much higher than would be expected by a conventional wet etch step using H2O2. Moreover, the use of the same tool as in the previous step is extremely efficient since it does not require moving the device at all.
Further, note that by avoiding a dry etch at this stage there is no risk of damaging the dielectric in the passivation layer 30. Next, the electrode metal 40 is deposited over the full surface of the device, including over the passivation layer 30 and in the recess 38, as illustrated in Figure 5. The electrode metal may be a single layer, for example of Ta or Ti, a nitride for example TaN or TiN, or a multilayer for example Ta/TaN or Ti/TiN.
After depositing the electrode metal 40 another CMP process is used to etch and/or polish away the electrode metal 40 from above the passivation layer 30 and hence to leave the electrode metal only in the recess 38 at the top of the via, flush (level) with the surface of the passivation layer 30 as shown in Figure 6, forming the finished electrode 42.
A biocompatible dielectric layer 44 is then deposited over the complete surface. The dielectric layer may be, for example, of TiO2, Ta2O5, SiO2, SiN or HfO2 or combinations of these or other materials.
Thus, a damascene process is used to form the biocompatible electrode in the recess at the top of the via. This process is a self-aligned process and this therefore ensures that the electrode 42 has exactly the same dimensions as the underlying W contact. This avoids the possibility of contamination caused by misalignment of the biocompatible electrode and the plug.
The possibility of avoiding the use of Au and Pt enables integration of the method on existing CMOS processing fabs, including those using copper interconnect.
Figures 7 and 8 illustrate a second embodiment. The method of manufacturing a semiconductor device according to the second embodiment proceeds in the same way as in the first embodiment to the stage illustrated in Figure 3.
The next step is to carry out a selective etch to form recess 38, but in the process illustrated with reference to Figures 7 and 8 the selective etch etches both the barrier layer 34 and the filling metal 36 to form recess 38.
Processing then proceeds as in the first embodiment to form electrode 42 and dielectric 44 to result in the finished semiconductor device illustrated in Figure 8.
The embodiments describe above relate to semiconductor devices using aluminium interconnect. However, the invention is also applicable to CMOS devices using other forms of interconnect, such as copper.
Figure 9 illustrates a third embodiment using a copper interconnect. In this embodiment, the manufacture proceeds essentially as in the embodiment of Figure 1 to 6, except that the material of the first and second interconnects 18, 28 is copper. Note however one difference; the second interconnect 28 is used to fill additionally the second via 24 and there is no separate plug in the second interconnect layer (this is the so-called dual damascene processing). In the embodiment illustrated in Figure 9, the material of the filling metal 36 is also copper. In this case, the choices for the barrier layer 34 include not merely Ti or TiN but Ta, or TaN/Ta. Although in the Figure 9 embodiment a Cu filling metal 36 is used with copper interconnects, other possibilities for filling metal 36 exist, such as tungsten.
The above embodiments are all described with reference to a semiconductor device with two metallisation layers. However, the invention is equally applicable to semiconductor devices with only a single metallisation layer, as well as to semiconductor devices with more than two metallisation layers.

Claims

1. A method of manufacturing a biocompatible electrode on a semiconductor device having a dielectric layer above at least one metallisation layer, the method comprising: etching a via (32) in the dielectric layer exposing the metallisation layer (28); depositing filling metal (36); etching back the filling metal using chemical mechanical polishing to remove the metal from the surface of the dielectric layer and to leave the metal in the via; carrying out a further etch to etch back the filling metal (36) in the via to form a recess (38) in the via; depositing an electrode metal (40) over the surface of the dielectric and in the recess in the via; and etching back the electrode metal (40) using chemical mechanical polishing to remove the electrode metal from the surface of the dielectric layer and to leave the electrode metal in the via to form the biocompatible electrode (42).
2. A method according to claim 1 wherein the step of carrying out a further etch to etch back the filling metal (36) in the via includes carrying out a wet etch.
3. A method according to claim 2 using a wet etch solution of hydrogen peroxide.
4. A method according to claim 2 or 3 wherein the wet etch is carried out on a chemical mechanical polishing tool.
5. A method according to any of claims 1 to 3 wherein the step of etching back the filling metal (36) using chemical mechanical polishing uses a chemical mechanical polishing tool; and the step of carrying out a further etch to etch back the metal in the via includes supplying a wet etch solution through the said chemical mechanical polishing tool.
6. A method according to any preceding claim further comprising forming a dielectric layer (44) over the biocompatible electrode (42).
7. A method according to any preceding claim wherein the electrode metal (40) is of at least one of Ta, Ti, TaN and TiN.
8. A method according to any preceding claim wherein the at least one metallisation layer (28) is of copper or an alloy of copper and the filling metal (36) is tungsten or copper.
9. A method according to any of claims 1 to 7 wherein the at least one metallisation layer (28) is of aluminium or an alloy of aluminium and the filling metal (36) is tungsten.
10. A semiconductor device comprising: an upper metallisation layer (28); an insulating layer (30) covering the metallisation layer (28), the insulating layer having an upper surface (31 ); a via (32) extending through the insulating layer to the metallisation layer; a filling metal (36) in the via; a biocompatible electrode (42) of metal in the via above the filling metal, the biocompatible electrode (42) having an upper surface (43) level with the upper surface of the insulating layer; and a dielectric layer (44) above the insulating layer and the electrode metal.
1 1. A semiconductor device according to claim 10, wherein the semiconductor device is a complementary metal oxide semiconductor device.
12. A semiconductor device according to claim 11 , further comprising: a barrier metal (34) in the via, extending to the upper surface (31 ) of the insulating layer.
13. A semiconductor device according to claim 12, wherein the barrier metal comprises of at least one of Ti, Ta, W, TiN, and TaN.
14. A semiconductor device according to claim 10, 1 1 , 12 or 13 wherein the electrode metal is of at least one of Ta, Ti, TaN and TiN.
15. A semiconductor device according to any of claims 10 to 14 wherein the semiconductor device has a plurality of metallisation layers (18,28) including the upper metallisation layer (28).
EP09756821.6A 2008-10-27 2009-10-26 Method of manufacturing a biocompatible electrode Not-in-force EP2345069B1 (en)

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EP08105674 2008-10-27
PCT/IB2009/054736 WO2010049881A1 (en) 2008-10-27 2009-10-26 Biocompatible electrodes
EP09756821.6A EP2345069B1 (en) 2008-10-27 2009-10-26 Method of manufacturing a biocompatible electrode

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EP2345069B1 EP2345069B1 (en) 2016-02-17

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US9281239B2 (en) 2016-03-08
WO2010049881A1 (en) 2010-05-06
CN102203935A (en) 2011-09-28
EP2345069B1 (en) 2016-02-17
US20110207239A1 (en) 2011-08-25

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