EP2339794A3 - A packet communication control device, a memory access control device, and an information-processing system - Google Patents

A packet communication control device, a memory access control device, and an information-processing system Download PDF

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Publication number
EP2339794A3
EP2339794A3 EP20100195977 EP10195977A EP2339794A3 EP 2339794 A3 EP2339794 A3 EP 2339794A3 EP 20100195977 EP20100195977 EP 20100195977 EP 10195977 A EP10195977 A EP 10195977A EP 2339794 A3 EP2339794 A3 EP 2339794A3
Authority
EP
Grant status
Application
Patent type
Prior art keywords
control
control device
packet
communication
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20100195977
Other languages
German (de)
French (fr)
Other versions
EP2339794B1 (en )
EP2339794A2 (en )
Inventor
Takashi Toyoshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/109Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0682Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0685Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697Synchronisation in a packet node
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/101Crossbar or matrix

Abstract

A packet communication control device transfers a control packet and a data packet and includes a plurality of sending units and a multiplexer which separates a data communication path and a control communication path, multiplexes the control packets and transfers the multiplexed control packets by the control communication path and the data packet by the data control path. The average Round-Trip communication time can be shortened and the hardware cost can be reduced because the Shortest-Job-First control is implemented by separating data communication pathway from control communication pathway logistically or physically, and also multiplexing the control communication pathway with control packet.
EP20100195977 2009-12-25 2010-12-20 A packet communication control device, a memory access control device, and an information-processing system Active EP2339794B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009294281A JP5333200B2 (en) 2009-12-25 2009-12-25 Packet communication control device, a memory access control device and the information processing system

Publications (3)

Publication Number Publication Date
EP2339794A2 true EP2339794A2 (en) 2011-06-29
EP2339794A3 true true EP2339794A3 (en) 2011-12-07
EP2339794B1 EP2339794B1 (en) 2017-04-26

Family

ID=43921037

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20100195977 Active EP2339794B1 (en) 2009-12-25 2010-12-20 A packet communication control device, a memory access control device, and an information-processing system

Country Status (3)

Country Link
US (1) US8472474B2 (en)
EP (1) EP2339794B1 (en)
JP (1) JP5333200B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120250640A1 (en) * 2011-03-30 2012-10-04 Sony Corporation Communication device, and communication system
EP2932398B1 (en) * 2012-12-13 2016-07-13 Coherent Logix, Incorporated Multiprocessor system with improved secondary interconnection network
US9860841B2 (en) * 2015-08-20 2018-01-02 Apple Inc. Communications fabric with split paths for control and data packets

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233242B1 (en) * 1996-12-30 2001-05-15 Compaq Computer Corporation Network switch with shared memory system
US6320859B1 (en) * 1997-10-31 2001-11-20 Nortel Networks Limited Early availability of forwarding control information
US20060155938A1 (en) * 2005-01-12 2006-07-13 Fulcrum Microsystems, Inc. Shared-memory switch fabric architecture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744728B1 (en) * 1997-09-17 2004-06-01 Sony Corporation & Sony Electronics, Inc. Data pipeline timing optimization technique in a multi-port bridge for a local area network
JP3365705B2 (en) * 1995-05-24 2003-01-14 インターナショナル・ビジネス・マシーンズ・コーポレーション Distributed data processing system
JPH09181774A (en) * 1995-12-23 1997-07-11 Nec Corp Optical switch device and optical switch control system
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device
US6345345B1 (en) * 1999-01-26 2002-02-05 Advanced Micro Devices, Inc. Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers
US6922390B1 (en) * 1999-06-15 2005-07-26 Nortel Networks Limited Method and apparatus for forecasting and controlling congestion in a data transport network
JP3387464B2 (en) * 1999-11-25 2003-03-17 日本電気株式会社 A communication control system and its control method
JP2002182875A (en) 2000-12-19 2002-06-28 Dainippon Screen Mfg Co Ltd Printing controller, printing control method and recording medium
JP4213517B2 (en) * 2003-02-28 2009-01-21 富士通株式会社 Packet processing system
JP4029790B2 (en) * 2003-07-09 2008-01-09 ブラザー工業株式会社 Packet communication control apparatus and a packet communication control method
US7957379B2 (en) * 2004-10-19 2011-06-07 Nvidia Corporation System and method for processing RX packets in high speed network applications using an RX FIFO buffer
JP2008245011A (en) 2007-03-28 2008-10-09 Advanced Telecommunication Research Institute International Wireless unit and radio network equipped therewith
US7779189B2 (en) * 2008-02-21 2010-08-17 International Business Machines Corporation Method, system, and computer program product for pipeline arbitration

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233242B1 (en) * 1996-12-30 2001-05-15 Compaq Computer Corporation Network switch with shared memory system
US6320859B1 (en) * 1997-10-31 2001-11-20 Nortel Networks Limited Early availability of forwarding control information
US20060155938A1 (en) * 2005-01-12 2006-07-13 Fulcrum Microsystems, Inc. Shared-memory switch fabric architecture

Also Published As

Publication number Publication date Type
US20110158247A1 (en) 2011-06-30 application
EP2339794B1 (en) 2017-04-26 grant
JP5333200B2 (en) 2013-11-06 grant
JP2011135433A (en) 2011-07-07 application
US8472474B2 (en) 2013-06-25 grant
EP2339794A2 (en) 2011-06-29 application

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