EP2053487A3 - Electric circuit and method for designing electric circuit - Google Patents

Electric circuit and method for designing electric circuit Download PDF

Info

Publication number
EP2053487A3
EP2053487A3 EP08166289A EP08166289A EP2053487A3 EP 2053487 A3 EP2053487 A3 EP 2053487A3 EP 08166289 A EP08166289 A EP 08166289A EP 08166289 A EP08166289 A EP 08166289A EP 2053487 A3 EP2053487 A3 EP 2053487A3
Authority
EP
European Patent Office
Prior art keywords
wirings
length
designing
electric circuit
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08166289A
Other languages
German (de)
French (fr)
Other versions
EP2053487A2 (en
Inventor
Shigeki FUNAI ELECTRIC CO. LTD. Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Funai Electric Co Ltd
Original Assignee
Funai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Funai Electric Co Ltd filed Critical Funai Electric Co Ltd
Publication of EP2053487A2 publication Critical patent/EP2053487A2/en
Publication of EP2053487A3 publication Critical patent/EP2053487A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a "first point") so that the wirings have substantially the same length (as a "first length"), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.
EP08166289A 2007-10-25 2008-10-09 Electric circuit and method for designing electric circuit Withdrawn EP2053487A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007277209A JP2009104503A (en) 2007-10-25 2007-10-25 Electric circuit and design method of electric circuit

Publications (2)

Publication Number Publication Date
EP2053487A2 EP2053487A2 (en) 2009-04-29
EP2053487A3 true EP2053487A3 (en) 2013-03-27

Family

ID=40091334

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08166289A Withdrawn EP2053487A3 (en) 2007-10-25 2008-10-09 Electric circuit and method for designing electric circuit

Country Status (4)

Country Link
US (1) US8001507B2 (en)
EP (1) EP2053487A3 (en)
JP (1) JP2009104503A (en)
CN (1) CN101419482B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101808460B (en) * 2010-03-25 2014-06-11 中兴通讯股份有限公司 Routing method for PCB and PCB
JP6028867B2 (en) * 2014-07-11 2016-11-24 富士通株式会社 Design program, apparatus and method
KR101589949B1 (en) * 2015-07-28 2016-01-29 주식회사 대성글로벌코리아 Pattern for impedance matching between processor unit and memory unit and uhd display board including the same
KR101593375B1 (en) * 2015-07-28 2016-02-11 박웅기 Array structure of uhd display board for error and uhd display board therewith
US10796728B2 (en) * 2018-08-17 2020-10-06 Micron Technology, Inc. Wiring with external terminal
KR20220048735A (en) * 2020-10-13 2022-04-20 삼성전자주식회사 Test method of memory device, memory built-in self test(MBIST) circuit and memory device for short test time
CN113220622A (en) * 2021-05-27 2021-08-06 浪潮电子信息产业股份有限公司 Mainboard and time sequence control method and device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6088253A (en) * 1998-11-12 2000-07-11 Nec Corporation Semiconductor memory device and method for forming same
US6223328B1 (en) * 1996-12-03 2001-04-24 Fujitsu, Limited Wire processing method, wire processing equipment, and recording medium for wire processing program used in designing a large scale integrated circuit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0588776A (en) 1991-09-26 1993-04-09 Nec Corp System for distributing lsi clock
US5784600A (en) * 1996-07-01 1998-07-21 Sun Microsystems, Inc. Method of generating exact-length wires for routing critical signals
KR100296452B1 (en) * 1997-12-29 2001-10-24 윤종용 Synchronous semiconductor memory device having data input buffers
US6305001B1 (en) * 1998-06-18 2001-10-16 Lsi Logic Corporation Clock distribution network planning and method therefor
JP2000122751A (en) 1998-10-16 2000-04-28 Matsushita Electric Ind Co Ltd Clock distributor and clock distributing method
JP2000148282A (en) 1998-11-10 2000-05-26 Hitachi Ltd Semiconductor device and module loading the semiconductor device
JP2000267756A (en) 1999-03-18 2000-09-29 Nec Corp Clock distributing circuit and clock distributing method
JP2001177046A (en) 1999-12-21 2001-06-29 Hitachi Ltd Semiconductor device and method for manufacturing the same
JP2004110103A (en) 2002-09-13 2004-04-08 Canon Inc Timing control circuit unit for clock
JP2006054348A (en) 2004-08-12 2006-02-23 Fujitsu Ltd Semiconductor device, clock distributing method and program
JP2006179112A (en) 2004-12-22 2006-07-06 Seiko Epson Corp Semiconductor memory device
EP1701279A1 (en) * 2005-03-11 2006-09-13 STMicroelectronics (Research & Development) Limited Manufacturing a clock distribution network in an integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6223328B1 (en) * 1996-12-03 2001-04-24 Fujitsu, Limited Wire processing method, wire processing equipment, and recording medium for wire processing program used in designing a large scale integrated circuit
US6088253A (en) * 1998-11-12 2000-07-11 Nec Corporation Semiconductor memory device and method for forming same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIPMAN J: "GROWING YOUR OWN IC CLOCK TREE", EDN ELECTRICAL DESIGN NEWS, REED BUSINESS INFORMATION, HIGHLANDS RANCH, CO, US, vol. 42, no. 6, 14 March 1997 (1997-03-14), pages 40 - 46,48, XP000695232, ISSN: 0012-7515 *

Also Published As

Publication number Publication date
CN101419482B (en) 2013-01-02
US20090108893A1 (en) 2009-04-30
CN101419482A (en) 2009-04-29
EP2053487A2 (en) 2009-04-29
JP2009104503A (en) 2009-05-14
US8001507B2 (en) 2011-08-16

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