EP1955223A2 - Verfahren zur computergestützten simulation technischer prozesse - Google Patents
Verfahren zur computergestützten simulation technischer prozesseInfo
- Publication number
- EP1955223A2 EP1955223A2 EP06829094A EP06829094A EP1955223A2 EP 1955223 A2 EP1955223 A2 EP 1955223A2 EP 06829094 A EP06829094 A EP 06829094A EP 06829094 A EP06829094 A EP 06829094A EP 1955223 A2 EP1955223 A2 EP 1955223A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- graph
- nodes
- propagation
- edges
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Definitions
- the present invention relates to a method for the computer-aided simulation of technical processes. Such methods are needed in particular for evolution simulation models of technical, in particular physical and / or chemical processes which are to be propagated in time (evolution).
- the additional level of abstraction of the method according to the invention permits a generic optimization of the propagation of evolutionary problems on a wide variety of hardware architectures, while concealing the optimization behind a general interface which does not depend on the specific evolutionary problems and not on hardware architectures.
- optimizations are limited to monolithic approaches to specific evolutionary problems and special hardware architectures, so these approaches always only experts are accessible for special hardware architectures.
- This type of optimization is thus not generically available to new evolutionary problems or new hardware architectures. In most cases, this costly optimization strategy does not make economic sense either, since considerable effort in the maintenance and porting of implemented evolutionary problems would be inherent in this approach.
- the present invention abstracts the necessary expert knowledge for hardware-specific optimization and thus secures the portability with high performance of various evolution problems that have been implemented by the method according to the invention.
- This new optimization is also generically available to non-experts for specific hardware architectures and represents a major economic benefit.
- the FEMLAB program package goes a step further here, but again only a set of coupling algorithms is available for finite element-based methods. However, the individual methods must be based on the finite element method.
- At least two different mathematical models which are based on different discrimination units, are combined to form a common evolutionary problem in that an additional level of abstraction, which is superordinate to the mathematical models, is introduced.
- This level of abstraction consists of a graph onto which the mathematical models are mapped as general evolutionary problems.
- the discretization units such as finite elements, wavelets or particles and the like, as well as their neighborhood relations, are represented as nodes and edges (links) of the graph. They are therefore the basic elements of the geometry of the evolutionary problem.
- the evolutionary algorithms describing the temporal propagation of the discretization units as well as their neighborhood relations, ie the nodes and the edges, are traced back to generic operators.
- evolution operators are provided gen- erally and uniformly for the nodes which are uniform with respect to the associated discretization unit.
- Generic evolution operators are also provided for the edges of the graph, ie unified operators are provided for the edges connecting between nodes of the same discretization unit, which are then applied equally to all such nodes.
- generic evolution operators are provided in each case with which these edges are uniformly distributed in the Time can be propagated.
- a criterion is assigned to each of the nodes and the edges, which determines the associated discretization unit or the type of by the
- Characterized edges connected nodes As a mark, for example, a color can be selected. If the entire evolution problem consists of two mathematical models, for example a model based on finite elements and a model based on particles, then all nodes representing finite elements get one color, for example blue, while all the nodes to which particles have been imaged, for example get the color red. The edges between two nodes on which particles have been imaged are then also red, the color of the edges connecting nodes to which finite elements have been imaged are then blue, while the color of those edges which have a node on the a finite element has been imaged, and a node onto which a particle is imaged was connect as bicolor blue-red.
- the two different mathematical models can not only describe the technical process in different spatial or temporal domains, but that the models can co-exist in the same spatial and temporal domain of a technical process. This means that for the same spatial and / or temporal range the technical process is described by both mathematical models.
- the graph does not have to remain static because nodes can change color, for example, when a particle moves out of the range described by a molecular dynamics model in a region described by finite elements. In this case, then the nodes and / or edges change color. It is also possible to dynamically create or destroy nodes and / or edges.
- the hardware-specific decomposition and parallelization The graph can now be prepared for the graph itself without knowledge of the technical processes and mathematical models implemented in the graph.
- the present invention thus makes it possible to optimize the simulation methods on hardware architectures and at the same time enables portability to fundamentally different architectures.
- the graph serves as an abstract interface.
- the present invention thus makes it possible to decompose and partition the graph generically into individual problems and thereby to parallelize them without knowing the specific technical process.
- This additional level of abstraction of the graph thus allows a generic and automatic parallelization, for example taking into account the hardware specifics.
- the simulation can therefore be completely described starting from the graph as a method, and the user only has to determine the respective graph structure as a function of the technical process to be simulated by him.
- the concrete decomposition of the problem and partitioning or parallelization of the concrete problem and the mathematical models used for its simulation and description are decoupled.
- Graphs are provided and general communication patterns are implemented. Again, the abstraction of the graph allows an architecture-specific optimization in which the internal process of these mechanisms is adapted to the hardware. For example, at each time step of computing the evolution problem, memory accesses can be reduced by maximized vector lengths or cache reuse.
- the parallel communication patterns can also be optimized by a chromatically ordered communication graph (communication pattern), which can be used here according to the invention.
- a chromatically ordered communication graph is described in "Peter Klein, Activity Report of the Institute of Industrial Mathematics 1999, pages 28, 29, available at the Press Office of the Fraunhofer ITWM, Gott Kunststoff Daimler Strasse, 76857 Kaiserslautern.” This document is fully incorporated in the Revelation of the present application.
- the present invention allows the user to define and use any of their own data structures and also evolution operators.
- the implementation of parallelization remains with the user behind the general interface, the graph, which implements the method of propagating the graph in a hardware-dependent and generic manner, ie independent of the concrete data structure and the concrete evolution operators.
- the present invention is thus not limited to individual methods and problems, but can generally be used in simulation and evolution models. It has particular advantages in the field of multiphysics simulation models, in which various mathematical models with different discretization units are used on a domain and / or part of a time basis.
- the present invention thus realizes a generic optimization on all hardware levels adapted to architecture-specific characteristics.
- the use of the memory hierarchies can be optimized particularly advantageously by dividing the GJraph into individual subgraphs and the individual subgraphs in the main memory in each case approximately or exactly in the size of one n memory areas (L2 blocks) are stored. Then all node operators and link operators (propagations of nodes and edges) that access the same memory area, as blockwise as possible directly after each other. Thus, first all node operators and then all link operators accessing the same memory area are executed, and then the node operators and link operators are accessed which access the next memory area. In this way it is possible to make optimal use of the cache memory. In the prior art, it has hitherto been customary to carry out first all node operators and then only all link operators. In contrast, the logical pipelining according to the invention leads to a considerably improved performance with a constant hardware specification.
- L2 cache can also be applied to other storage hierarchies (cache hierarchies).
- cache hierarchies In the case of multiple (k is a natural number) cache memory levels, the subdivision into subgraphs can therefore be made so that each one
- Subgraph is stored in the main memory respectively in a memory area whose size corresponds to the size of a memory block of one of the k cache memory.
- the m-th storage level can be selected for optimization, for example. If this is realized by an n-fold associative memory with n memory blocks, with each memory block having a size of x kbytes, the graph is subdivided into sub-graphs so that each sub-graph in the main memory occupies a memory area of x kbytes. However, it is also sufficient already to store each subgraph in the main memory in a memory area with approximately or approximately, but not exactly x kbyte, in order to achieve a performance improvement. For more than two cache hierarchy levels (k> 2) can be used by Selection of the appropriate m-th memory level, the inventive method can be optimized.
- FIG. 1 shows a graph according to the invention
- FIGS. 2a to 2c show the parallelization of a graph
- FIG. 3 shows the decomposition of a graph
- FIG. 4 shows the optimization of the cache utilization by the method according to the invention
- Figure 5 shows the results of the process according to the invention using a four-associative L2-cache memory
- FIG. 1 shows a graph according to the invention of a multi-physics application according to the present invention.
- a first physical computing area A (shown in light) the finite element method is used to simulate the physical problem in order to implement a continuum mechanical description of the behavior of a material.
- a second computing area B (shaded in gray) the so-called molecular dynamics is used to propagate atoms in time.
- finite elements are used as the discriminating element, while particles are used in the area B as the discretizing element.
- the particles have as their data their coordinates, velocities and a particle identifier.
- the coordinates are propagated using velocity in time.
- a node operator is implemented as an evolution operator.
- the velocities are propagated with forces, whereby the forces depend on neighboring atoms. This was implemented as a link operator.
- the discretization unit consists of a finite element, whereby the displacement of the finite element is solved by means of standard methods, which are implemented as node and edge operators of the finite elements.
- the finite elements 2a are interconnected via intra-links (intra-nodes) 3a.
- the particles 2b in the region B are interconnected by intra-nodes 3b.
- the connection between the particles 2b and the finite elements 2a takes place via inter-links 3c.
- areas A and B do not necessarily have to be spatially different areas. These can also be temporally different areas or even overlapping or even congruent areas. In the latter case, the technical process is then described twice by two different mathematical models.
- the node 2a and the edges 3a can be assigned the color red, the node 2b and the edges 3b the color blue, while the edges 3c are red-blue or blue are red.
- colors instead of colors, however, any other type of license plate is possible. Colors are suitable but especially good for the intuitive representation of the different areas of a total graph 1.
- FIGS. 2A to 2C show the steps that are performed in the parallelization of the graph 1 after the geometry and the algorithms of the mathematical models, as shown in FIG. 1, have been mapped onto the graph 1.
- Figure 3 shows the decomposition into sub-problems, in which a graph is shown representing nodes 2a and 2b of different discretization units.
- a graph is shown representing nodes 2a and 2b of different discretization units.
- the decomposition of the total graph into subproblems and then another
- Disassembly on the processors By disassembling the processors and breaking them down into the subproblems, the hardware can be taken into account, such as adjusting memory usage and loops to an existing L2 cache. Finally, the parallelized problem initia- llabor and calculates and so simulated the technical process.
- FIG. 4 shows the logical pipeline which has been optimized for an n-times associated L2 cache. Instead of first propagating all nodes (Note_Operator (.)) And then propagating all edges (Link operator (.)) As usual in FIG. 4A and in the state of the art, a different procedure is now selected as shown in FIG , For this purpose, the information for a graph section, for example 4a in FIG. 2C, is stored in a respective memory area and subsequently all nodes and edges of this graph area are propagated. In this case, access to the information in a memory area of the cache memory takes place primarily. Only then are the nodes and edges propagated, whose propagation requires access to the second area of the cache memory. The use of the cache memory is thereby optimized.
- Figure 5 shows the results achieved by this procedure. For a four-associative L2 cache (with a memory block size of
- each subgraph in the main memory was assigned a container size of 256 KB, and then, as described for FIG. 4, the respective processor first assigned all nodes and edges whose propagation was assigned to it and for those required Information stored in the associated container (memory block) were calculated. Only then was the propagation of the overall graph determined.
- the container size of 256 KB results in exactly one storage area of the four 1024 KB associative L2 cache, performs optimally compared to container sizes that are smaller or larger. The method according to the invention thus results in a very efficient use of resources when using an L2 cache-based computer system.
- FIGS. 6 to 8 now show the pseudocode for the initialization and use of the method according to the invention.
- FIG. 6 shows the use of the method only with a mathematical model, in this case molecular dynamics.
- FIG. 7 likewise uses only a mathematical model using finite elements as the discretization unit.
- FIGS. 8A and 8B which must be read continuously, now connect these two elements from FIGS. 6 and 7 to a method according to the invention.
- the nodes are created first with R. register_BDE and the edges of the graph with R. register_Link, which are intended to map a molecular dynamics model.
- InteractionForce Force, Liouville_V UV and Liouville_Q UQ define the propagation routines for calculating the forces between the individual nodes, for the propagation of the velocity V and the propagation of the coordinates Q of the nodes.
- These general routines (propagation operators) apply to all nodes and edges of type MD (belonging to the molecular dynamics model). With the time loop indicated in the pseudocode, the propagation is then carried out by applying the abovementioned propagation operators to all nodes and edges for one period of time.
- FIG. 7 shows the same system for finite elements as a discretization unit. Again, the nodes and edges of the graph that map the finite element model are defined via R.register_BDE and R. register_Link.
- the method according to the invention now combines both models and first provides a graph in which the edges and nodes of the finite element model as well as the edges and nodes are defined according to the molecular dynamics model.
- the corresponding propagation operators are defined as in FIGS. 6 and 7.
- join operators are now defined that couple together nodes connected via edges of the molecular dynamics subgraph and the finite element subgraph. This follows as an operator, which calculates the displacement of the adjacent finite element from the molecular dynamics model (CalcDisplacementMD) and on the other hand an operator, which calculates from the finite element model, the force acting on a particle in the molecular particle model (CalcForceFE).
- the user has then completely defined the graph, and the graph is then subsequently propagated in time (see section "Time Loop"), in which the mentioned propagation operators and coupling operators are applied to the nodes and edges according to their respective properties.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Processing Or Creating Images (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP13178570.1A EP2660741A1 (de) | 2005-12-02 | 2006-11-22 | Verfahren zur computergestützen Simulation technischer Prozesse |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102005057697A DE102005057697A1 (de) | 2005-12-02 | 2005-12-02 | Verfahren zur computergestützten Simulation technischer Prozesse |
| PCT/EP2006/011197 WO2007062769A2 (de) | 2005-12-02 | 2006-11-22 | Verfahren zur computergestützten simulation technischer prozesse |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1955223A2 true EP1955223A2 (de) | 2008-08-13 |
Family
ID=37762588
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP13178570.1A Withdrawn EP2660741A1 (de) | 2005-12-02 | 2006-11-22 | Verfahren zur computergestützen Simulation technischer Prozesse |
| EP06829094A Ceased EP1955223A2 (de) | 2005-12-02 | 2006-11-22 | Verfahren zur computergestützten simulation technischer prozesse |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP13178570.1A Withdrawn EP2660741A1 (de) | 2005-12-02 | 2006-11-22 | Verfahren zur computergestützen Simulation technischer Prozesse |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8214180B2 (de) |
| EP (2) | EP2660741A1 (de) |
| DE (1) | DE102005057697A1 (de) |
| NO (1) | NO20082885L (de) |
| WO (1) | WO2007062769A2 (de) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8086609B2 (en) * | 2007-11-01 | 2011-12-27 | Cavium, Inc. | Graph caching |
| DE102008019478A1 (de) | 2008-04-17 | 2009-10-22 | Wincor Nixdorf International Gmbh | Verfahren und Vorrichtung zur Steuerung von Benutzerdialogen an einer technischen Einrichtung |
| CN109902366B (zh) * | 2019-02-14 | 2020-05-05 | 中国水利水电科学研究院 | 一种分布式水文模型汇流并行方法 |
| CN115312143B (zh) * | 2022-07-15 | 2026-02-03 | 重庆科技学院 | 基于有限元的电磁脉冲微焊点微观组织演化的模拟方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6353768B1 (en) * | 1998-02-02 | 2002-03-05 | General Electric Company | Method and apparatus for designing a manufacturing process for sheet metal parts |
| US6685772B2 (en) * | 2001-03-28 | 2004-02-03 | California Institute Of Technology | De novo processing of electronic materials |
| EP1318453A1 (de) * | 2001-12-07 | 2003-06-11 | Hewlett-Packard Company | Sytem, Verfahren und Vorrichtung zum Planen einer Rechnergruppe |
| US7000211B2 (en) | 2003-03-31 | 2006-02-14 | Stretch, Inc. | System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources |
| US8117288B2 (en) * | 2004-10-12 | 2012-02-14 | International Business Machines Corporation | Optimizing layout of an application on a massively parallel supercomputer |
-
2005
- 2005-12-02 DE DE102005057697A patent/DE102005057697A1/de not_active Withdrawn
-
2006
- 2006-11-22 EP EP13178570.1A patent/EP2660741A1/de not_active Withdrawn
- 2006-11-22 US US12/085,926 patent/US8214180B2/en active Active
- 2006-11-22 EP EP06829094A patent/EP1955223A2/de not_active Ceased
- 2006-11-22 WO PCT/EP2006/011197 patent/WO2007062769A2/de not_active Ceased
-
2008
- 2008-06-25 NO NO20082885A patent/NO20082885L/no not_active Application Discontinuation
Non-Patent Citations (1)
| Title |
|---|
| W R KRIGER ET AL: "Multi-Disciplinary Simulation of Vehicle System Dynamics Multi-Disciplinary Simulation of Vehicle System Dynamics", RTO AVT SYMPOSIUM ON "REDUCTION OF'MILITARY VEHICLE ACQUISITION TIME AND COST THROUGH ADVANCED MODELLING AND VIRTUAL SIMULATION", 25 April 2002 (2002-04-25), XP055367830 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090228248A1 (en) | 2009-09-10 |
| WO2007062769A3 (de) | 2007-08-09 |
| US8214180B2 (en) | 2012-07-03 |
| WO2007062769A2 (de) | 2007-06-07 |
| DE102005057697A1 (de) | 2007-06-06 |
| EP2660741A1 (de) | 2013-11-06 |
| NO20082885L (no) | 2008-09-02 |
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