EP1875733A1

EP1875733A1 - Apparatus and method for processing data in digital broadcasting receiver

Info

Publication number: EP1875733A1
Application number: EP06732884A
Authority: EP
Inventors: Jeong-Wook Seo; Wei-Jin Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2005-04-28
Filing date: 2006-04-28
Publication date: 2008-01-09
Also published as: EP1875733A4; WO2006115388A1

Abstract

Disclosed is a digital broadcasting receiver including a tuner for selecting a channel of received digital broadcasting signals by channel selection of a controller, a demodulator for de¬ modulating signals of the selected digital broadcasting channel, the controller for establishing identifiers for multiple channels, generating distribution control signals of data, and generating output control signals, a demultiplexer for receiving packet data of the established identifiers, analyzing a type of the received packet data, transferring the identifiers and the type of the data to the controller, storing the received packet data in a buffer as ES data, and demultiplexing the buffered ES data and outputting the demultiplexd data to decoders, a video decoder for decoding the demultiplexd video ES, an audio decoder for decoding the demultiplexd audio ES, a data decoder for decoding the demultiplexd service data ES, and a display unit for displaying the decoded video, audio and service data.

Description

APPARATUS AND METHOD FOR PROCESSING DATA IN DIGITAL BROADCASTING RECEIVER

Technical Field

[1] The present invention relates to an apparatus and a method for processing data in a digital broadcasting receiver, and more particularly to an apparatus and a method for processing multiple broadcast data in a digital broadcasting receiver. Background Art

[2] In general, a current wireless terminal shows a tendency to mount a dedicated multimedia processor therein or to reinforce a multimedia function. At the present time, a technology for allowing a wireless terminal to have a television function has been published, and research for allowing a digital broadcasting receiver to be mounted in a wireless terminal has been conducted. Accordingly, a current wireless terminal must have a construction for providing various multimedia functions. Therefore, the construction and processing procedure of a wireless terminal becomes more complicated.

[3] At the present time, standardization for digital broadcasting has been actively accomplished throughout the world. In the case of digital broadcasting, there exist a DMB scheme used in USA and a DVB scheme used in Europe. A wireless terminal equipped with the digital broadcasting receiver as described above includes a tuner, a demodulator, a decoder, etc. Herein, the tuner for receiving digital broadcasting, the demodulator and the decoder have different constructions as those of a Radio Frequency (RF) unit, a demodulator and a decoder of a wireless terminal, respectively. That is, the digital broadcasting receiver uses a frequency different from a communication frequency of a wireless terminal, and also uses different demodulation and decoding schemes. Since the digital broadcasting receiver must be additionally provided as described above, the size of a wireless terminal inevitably increases.

[4] FIG. 1 is a block diagram illustrating the construction of a digital broadcasting receiver. In FIG. 1, the digital broadcasting receiver includes an RF unit 110, a demodulator 120, a decoder 130, etc.

[5] Referring to FIG. 1, digital broadcasting signals may include signals of a VHF (174 to 230 MHz: C5 to C12) band and/or signals of a UHF (470 to 862 MHz: C21 to C69) band and/or signals of an L-band (1452 to 1492 MHz). Herein, if a user selects a broadcast channel, a controller 100 outputs control data corresponding to a channel selected by the RF unit 110. The RF unit 110 generates and mixes RF frequencies according to the channel data, thereby generating Intermediate Frequency (IF) signals of the selected channel. The IF may be 36.17 MHz. The IF signals as described above are applied to the demodulator 120. Then, the demodulator 120 demodulates the received signals by means of a predetermined modulation scheme, and outputs the demodulated signals. Herein, it is assumed that the signals output from the demodulator 120 correspond to MPEG-2 Transport Stream (TS) signals. These signals are applied to the decoder 130. Then, the decoder 130 divides the received MPEG-2 TS signals into video, audio and data, decodes the video, audio and data, respectively, and outputs video signals and voice signals. The video signals may include signals such as RGB signals and YUV signals, and the voice signals are generally output as PCM stereo sound. The video signals output from the decoder 130 are output to a display unit 150 for display, and the voice signals are applied to a speaker 160 for reproduction.

[6] Hereinafter, the construction of the decoder 130 in the digital broadcasting receiver will be described. FIG. 2 is a block diagram illustrating the construction of the decoder 130.

[7] Referring to FIG. 2, a demultiplexer 210 receives the demodulated MPEG-2 TS data output from the demodulator 120, and divides respective data into audio, video and other data. Herein, the controller 100 selects information, i.e. service PID (Product ID), of broadcasting, which is to be selected by the demultiplexer 210, and informs the demultiplexer 210 of the selected information. Then, the demultiplexer 210 selects target data from various data, which are output from the demodulator 120, according to the selected PID, and divides the target data into video and audio. An input buffer 220 corresponds to a general queue (similar to an FIFO structure and may be a circular buffer in which input and output are inversely accomplished), and stores data demultiplexed in realtime by the amount of data which may be processed by a video decoder 230 and an audio decoder 250. The video decoder 230 decodes the video data. Herein, it is common that the digital broadcasting receiver receives a MPEG-2 video Elementary Stream (ES), and converts the MPEG-2 video ES into YUV 4:2:0 data. However, since the video signals must be output as data proper for the display unit (LCD) of the digital broadcasting receiver, the video data may also be converted into RGB data. Likewise, the audio decoder 250 decodes audio signals, and converts the received MPEG-2 audio ES into PCM audio signals. The converted PCM audio signals are stored in an audio output buffer 260 and then output at a corresponding output time point.

[8] In the digital broadcasting receiver having the construction as described above, the video decoder 230, the audio decoder 250 and other data decoders (not shown) perform decoding operations in the unit of frame data, respectively. Herein, the decoders 230 and 250 buffer the video or audio data, which are output from the demultiplexer 210, in the unit of frame, and perform the decoding operations, respectively. [9] FIG. 3 is a block diagram illustrating the construction of the demodulator 120 in the decoder 130.

[10] Referring to FIG. 3, a sync search unit 311 detects a sync byte of a packet header in the received TS signals, and stores the received TS signals in an input buffer 321 when the sync byte is detected. Then, the input buffer 321 buffers data of a packet size, a packet header processor 313 extracts a packet header from the input buffer 321, processes the extracted packet header, and outputs remaining data except for the packet header to a buffer 323. An adaptation processor 315 extracts an adaptation from the buffer 323, processes the extracted adaptation, and outputs remaining data except for the adaptation to a buffer 325. A PES header processor 317 extracts PES header information from the buffer 325, processes the extracted PES header information, and outputs remaining information except for the PES header to a buffer 327. A data processor 319 extracts data from the buffer 327 and outputs the extracted data to a video ES or an audio ES.

[11] FIG. 4 is a block diagram illustrating the construction of the data processor 319 in

FIG. 3.

[12] Referring to FIG. 4, the ES data output from the PES header processor 317 are input to a distributor 411 of the data processor 319 through the buffer 327, and the distributor 411 distributes ES data, which are input through audio/video selection signals, to a video buffer 413 or an audio buffer 415. The audio/video selection signals may be the PID of a broadcast channel/service of a channel selected by a user. The PID represents an identifier for identifying the type of a packet, corresponds to information on a channel/service selected by a user, and is identified by the packet header processor 313. Further, the PES header processor 317 analyzes the PES header of received data and determines the type of data. Herein, the selected channel/service may include a broadcast channel, a digital broadcasting service, etc., and the data are used for identifying if input data correspond to video data, audio data or data (broadcast data).

[13] In the digital broadcasting receiver as described above, the output of the demultiplexer 210 may include a video ES, an audio ES, a data ES, etc. Herein, the digital broadcasting receiver may display various types of screens. For example, the digital broadcasting receiver may display a Picture In Picture (PIP) screen, a multivision screen, etc. Disclosure of Invention Technical Problem

[14] The screen display method using the PIP, the multivision, etc., corresponds to a method for receiving and displaying data of at least two channels. That is, it is necessary to receive data of at least two channels. However, in the case of using the demultiplexer 210 having the construction as illustrated in FIG. 4, it is impossible to receive and demultiplex data of more than two channels.

[15] According to the prior art, in the case of displaying a screen such as the PIP screen and the multivision screen, a decoder must demultiplex ES data and decode such ES data while time-divisionally changing PIDs. For example, when data of two channels are received, it is necessary to time-divide and demultiplex channel data having different PIDs set in two frame intervals. Therefore, when the method as described above is used, a frame rate of received data may deteriorate and the quality of a display screen may also deteriorate. Technical Solution

[16] Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide an apparatus and a method for decoding data of multiple received channels in a digital broadcasting receiver.

[17] It is another object of the present invention to provide an apparatus and a method for sequentially demultiplexing and decoding data of multiple received channels in a digital broadcasting receiver.

[18] It is further another object of the present invention to provide an apparatus and a method for sequentially demultiplexing data of multiple received channels, buffering the demultiplexed data according to corresponding channels, and decoding the buffered data in a digital broadcasting receiver.

[19] In order to accomplish the aforementioned object, according to one aspect of the present, there is provided a digital broadcasting receiver including: a tuner for selecting a channel of received digital broadcasting signals by channel selection of a controller; a demodulator for demodulating signals of the selected digital broadcasting channel; the controller for establishing identifiers for multiple channels according to setup of a user, generating distribution control signals of data when the data of the established identifiers are received, and generating output control signals for outputting the distributed data; a demultiplexer for receiving packet data of the established identifiers from the demodulated digital broadcasting signals, analyzing a type of the received packet data, transferring the identifiers and the type of the data to the controller, storing the received packet data in a buffer, which is set by the distribution control signals, as ES data, and demultiplexing the buffered ES data and outputting the demultiplexd data to corresponding decoders by the output control signals; a video decoder for decoding the demultiplexd video ES; an audio decoder for decoding the demultiplexd audio ES; a data decoder for decoding the demultiplexd service data ES; and a display unit for displaying the decoded video data, audio data and service data.

Advantageous Effects

[20] a digital broadcasting receiver of the present invention as described above, a data processor of a demultiplexer includes a plurality of output buffers, and can analyze PIDs for multiple channels/services established by a user, demultiplex the input ESs of multiple channels/services, and transfer the demultiplexed ESs to corresponding decoders. Consequently, it is possible to process the ESs of multiple channels in one frame interval, and to support a service, such as a PIP and a multivision, a plurality of data broadcasting and contents, etc., without deterioration in a frame rate. Brief Description of the Drawings

[21] The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[22] FIG. 1 is a block diagram illustrating the construction of a digital broadcasting receiver;

[23] FIG. 2 is a block diagram illustrating the construction of the decoder in FIG. 1;

[24] FIG. 3 is a block diagram illustrating the construction of the conventional demodulator for demultiplexing input packet data in FIG. 1 ;

[25] FIG. 4 is a block diagram illustrating the construction of the data processor in FIG.

3;

[26] FIG. 5 is a block diagram illustrating the construction of a demultiplexer according to an embodiment of the present invention;

[27] FIGs. 6a to 6c are diagrams illustrating the configuration of a received packet;

[28] FIGs. 7a to 7c are diagrams illustrating the configuration of an adaptation included in a received packet;

[29] FIGs. 8a to 8d are diagrams illustrating the configuration of PES information included in a received packet;

[30] FIG. 9 is a block diagram illustrating the configuration of a data processor according to an embodiment of the present invention;

[31] FIG. 10 is a flow diagram illustrating a procedure by which the data processor of

FIG. 9 processes ES data;

[32] FIG. 11 is a flow diagram illustrating a procedure for distributing the output of a demultiplexer to decoders in a digital broadcasting receiver according to an embodiment of the present invention; and

[33] FIG. 12 is a block diagram illustrating the construction of a demultiplexer according to another embodiment of the present invention. Best Mode for Carrying Out the Invention [34] Hereinafter, preferred embodiments according to the present invention will be described with reference to the accompanying drawings. It should be noted that the same reference numerals are used to designate the same elements as those shown in other drawings.

[35] In the following description, particular items, such as the MPEG 2-TS data structure of a digital broadcasting receiver, are shown, but these are provided for aiding the general understanding of the present invention. It will be understood by those skilled in the art that the present invention can be easily embodied without these particular items or through the modification of these particular items.

[36] An embodiment of the present invention proposes an apparatus and a method in which a demultiplexer, which analyzes packet data received in a digital broadcasting receiver and distributes the packet data to corresponding decoders before the digital broadcasting receiver performs a decoding operation, has buffers of multiple channels, distributes and buffers data of multiple received channels according to corresponding channels, decodes the buffered data of each channel, and can display the decoded data on a single screen.

[37] In an embodiment of the present invention, it is assumed that TS signals input to the digital broadcasting receiver correspond to MPEG 2-TS signals. An operation according to an embodiment of the present invention can be applied in the same way, regardless of a case in which the TS signals conform to the system standard of a MPEG-4, video signals included as detail data conform to an H.261 to an H. 264 or a MPEG-4, or audio signals conform to a MPEG-I to a MPEG-4, or an AAC⁺.

[38] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[39] A digital broadcasting receiver of a wireless terminal according to an embodiment of the present invention has the construction as illustrated in FIG. 1, and performs an operation equal to that described in FIG. 1. In the digital broadcasting receiver having the construction, the decoder 130 may have the construction as illustrated in FIG. 2.

[40] FIG. 5 is a block diagram illustrating the construction of the demultiplexer 210 according to an embodiment of the present invention.

[41] Referring to FIG. 5, the sync search unit 311 detects a sync byte of a packet header in received TS signals, and stores the received TS signals in the input buffer 321 when the sync byte is detected. Then, the input buffer 321 buffers data of a packet size, the packet header processor 313 extracts a packet header from the input buffer 321, processes the extracted packet header, and outputs remaining data except for the packet header to the buffer 323. The adaptation processor 315 extracts an adaptation from the buffer 323, processes the extracted adaptation, and outputs remaining data except for the adaptation to the buffer 325. The PES header processor 317 extracts PES header in- formation from the buffer 325, processes the extracted PES header information, and outputs remaining information except for the PES header to The buffer 327. The data processor 319 has multiple preliminary buffers, distributes the ES data, which are output from the PES header processor 317, according to received channels, buffers the distributed data, selects the buffered ES data of each channel, and outputs the selected data to corresponding decoders.

[42] Accordingly, the demultiplexer 210 based on the embodiment of the present invention distributes data of multiple channels according to channels, buffers the distributed data, selects the buffered data, and outputs the selected data to the video decoder 230, the audio decoder 250 or the data decoder 270 according to the type of data. Accordingly, the decoder 130 based on the embodiment of the present invention stores multiple received channel/service data according to corresponding channels/ services, and decodes the stored data of each channel according to the type of data. In this way, multiple channel data can be displayed on a single screen (frame) video. Herein, when displaying videos of multiple channels, it is preferred to display only audio channel data of a channel corresponding to a main screen video. Accordingly, a user can watch videos or service information of multiple channels displayed on the display unit 150, and can hear data of a selected audio channel through the speaker 160.

[43] Before describing the operations of the processors 313, 315, 317 and 319 in the demultiplexer 210, the configuration of the input TS signals will be described. The TS signals correspond to a packet stream, and has video packets, audio packets and data packets {e.g. Multiprotocol Encapsulation (MPE), Internet Protocol (IP)} as illustrated in FIG. 6a. The packets are randomly multiplexed and transmitted in the digital broadcasting receiver. The video packet or audio packet of FIG. 6a is comprised of a packet header and a payload as illustrated in FIG. 6b, and the packet header and the payload are comprised of 188 bytes. That is, one packet data is comprised of 188 bytes. The packet header has a size of four bytes as illustrated in FIG. 6c, and each parameter of the packet header has the function as illustrated in table 1 below.

[44] Table 1

[45]

[46] That is, the packet data starts with the sync byte, and one packet is distinguished from another packet on the basis of the sync byte. The sync search unit 311 searches for the input packet data and delays data input until the sync byte is detected. If the sync byte is detected, the sync search unit 311 allows subsequent input packet data to be buffered in the buffer 321. The packet headers of four bytes as illustrated in table 1 are buffered in the first to fourth byte position of the buffer 321.

[47] Then, the packet header processor 313 has a construction for processing the packet header as illustrated in FIG. 6c and table 1, compares an identifier PID, which represents the stream information of video/audio signals of an established broadcast channel, with the PID of the TS signals output from the buffer 321, and determines whether to process received packets. In the case of a packet having no established PID, the packet header processor 313 prevents the packet buffered in the buffer 321 from being processed. Further, if the packet buffered in the buffer 321 has a value equal to the established PID, the packet header processor 313 transfers the packet data stored in the buffer 321 to the buffer 323. That is, the packet header processor 313 analyzes the received packets, transfers only packets having the established PID information to the buffer 323, and prevents packets having different PIDs from being demultiplexed, i.e. discards undesired packets.

[48] Herein, it is necessary to establish PIDs for multiple channels/services such as the

PIP and the multivision as described above. Accordingly, the packet header processor 313 receives the PIDs for multiple channels/services from the controller 100, analyzes the received packets, and processes packet headers for the multiple established PIDs. If the PIDs of multiple channels/services are established, the packet header processor 313 according to the embodiment of the present invention analyzes and processes packets corresponding to the established PIDs, and prevents packets having unestablished PIDs from being processed.

[49] The packet header processor 313 analyzes the packet header, and determines if the packet header includes adaptation field control. In the case of a packet not including the adaptation field control, i.e. a packet having a PES header and/or actual data (ES), it is also possible to omit the operation of the adaptation processor 315 and transfer the packet data stored in the buffer 323 to the PES header processor 317. In the case of the packet not including the adaptation field control as described above, in the packet data having the configuration as illustrated in FIG. 6c, the PES header and/or the actual data (ES) is stored in the adaptation field. However, if the packet data include the adaptation field control, the packet data has the configuration as illustrated in FIG. 6c. Herein, an adaptation or an adaptation and the PES header and/or the actual data (ES) may be included in the adaptation field. Then, the packet header processor 313 may transfer the data buffered in the buffer 321 to the adaptation processor 315. Herein, the packet header of four bytes is removed from the data transferred to the buffer 323.

[50] The adaptation processor 315 processes the data included in the adaptation field of

FIG. 6c, and the data in the adaptation field have a configuration as illustrated in FIGs. 7a to 7c. FIG. 7a is a diagram illustrating the configuration of an adaptation header. The adaptation includes an adaptation field length, an ES priority indicator, etc., and has 5 flags indicating if the header includes an optional field 1. Herein, if the header includes the optional field 1, the adaptation processor 315 sets a flag (or flags) corresponding to the 5 flags as illustrated in FIG. 7a, and adaptations corresponding to the set flag are included in the optional field 1 of FIG. 7a. The adaptation included in the optional field 1 may have a configuration as illustrated in FIG. 7b.

[51] Referring to FIG. 7b, the optional field 1 includes adaptations, which may be used for decoding, in addition to a Program Clock Reference (PCR). Table 1 shows data of the optional field 1 corresponding to each of 5 flags. Herein, two or more flags or all of the 5 flags may also be set. For example, if the 5 flags are set to " 10100", the optional field 1 includes the PCR and splice countdown data.

[52] Further, the optional field 1 as illustrated in FIG. 7b has 3 flags indicating if data of an optional field 2 are included. When the optional field 2 is included, a corresponding flag is set in the 3 flags of FIG. 7b, and adaptations are included in the optional field 2. The optional field 2 has a configuration as illustrated in FIG. 7c. FIGs. 7a to 7c illustrate adaptations for decoding the received packet data, and the adaptations are included only if the situation requires.

[53] Further, packets, which are determined as packets having no adaptations by the packet header processor 313, or packets, which remain after the adaptation processor 315 processes adaptations, are processed by the PES header processor 317 and the data processor 319. The PES header processor 317 processes PES header information as illustrated in FIGs. 8a to 8d. FIG. 8a is a diagram illustrating the configuration of a PES header. The PES header includes a PES scrambling control, a PES priority, a copyright, an original/copy, 7 flags, a PES data length, etc., and additionally has a PES optional field 1 if the situation requires. FIG. 8b is a diagram illustrating the configuration of the PES optional field 1. The PES optional field 1 includes a Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS). The PTS is a time stamp for displaying data decoded by the video decoder 230 or the audio decoder 250 on the display unit 150. At the time specified by the PTS, the decoder outputs the decoded data to the display unit 150. The DTS is a time stamp in which the video decoder 230 or the audio decoder 250 starts decoding, and the decoder starts to decode the input packet data at the time specified by the DTS.

[54] The PES optional field 1 may further include a PES extension as illustrated in FIG.

8b if the situation requires. FIG. 8c is a diagram illustrating the configuration of the PES extension. The PES extension may further include 5 flags, and a PES optional field 2 if the situation requires. FIG. 8d is a diagram illustrating the configuration of the PES optional field 2. This is determined by the 5 flags of the PES extension as illustrated in FIG. 8c. The 5 flags of FIG. 8c determine the content of the PES optional field 2. The PES header processor 317 processes the PES header having the configurations as illustrated in FIGs. 8a to 8d, and transfers the actual data ES except for the PES header to the data processor 319. Further, the PES header processor 317 transfers the type (video, audio and data) of a packet analyzed according to the PES header to the controller 100. The data ES transferred to the data processor 319 correspond to raw ESs in which all header information included in the packet data has been removed. The data processor 319 distributes the transferred ES to a video ES or an audio ES.

[55] After the PES header processor 317 processes the PES header, if remaining data except for the PES header include Multiprotocol Encapsulation (MPE) data, the PES header processor 317 outputs the remaining data including the MPE data to a first corresponding buffer (not shown). An MPE data processor (not shown) extracts the MPE data from the first corresponding buffer, and processes the extracted MPE data, thereby generating IP data. Then, the MPE data processor outputs the generated IP data to a second corresponding buffer (not shown). An IP data processor (not shown) extracts the IP data from the second corresponding buffer, processes the extracted IP data, thereby generating User Define Protocol (UDP) data. Then, the IP data processor outputs the generated UDP data to a third corresponding buffer (not shown). A UDP data processor (not shown) extracts the UDP data from the third corresponding buffer, processes the extracted UDP data, thereby generating File Delivery over Unidirectional Transport Protocol (FLUTE) data and Real-time Transport Protocol (RTP) data. Then, the UDP data processor outputs the generated FLUTE data and RTP data to a fourth corresponding buffer (not shown). A FLUTE data processor (not shown) extracts the FLUTE data from the fourth corresponding buffer, processes the extracted FLUTE data, thereby generating ESG data and/or file data. An RTP data processor (not shown) extracts the RTP data from the fourth corresponding buffer, processes the extracted RTP data, thereby generating Audio/Video (AfV) raw data. Further, the FLUTE data processor and the RTP data processor output the generated ESG data and/or file data and the A/V raw data to the buffer 327. Then, the data processor having multiple preliminary buffers distributes the ESG data and/or file data and the A/V raw data, which are output to the buffer 327, according to received channels, buffers the distributed data, selects the buffered ES data of each channel, and outputs the selected data to corresponding decoders. The data processor includes a distributor 511, a selector 513 and a buffer 515, which will be described in detail with reference to FIG. 9. Further, the data processor having multiple preliminary buffers may buffer the IP data, which are output to the second corresponding buffer, the UDP data, which are output to the third corresponding buffer, and/or the FLUTE data and RTP data, which are output to the fourth corresponding buffer, in the multiple preliminary buffers.

[56] The controller 100 receives the established PID from the packet header processor

313, and receives the information on the type of data from the PES header processor 317. Further, the controller 100 receives channels or service selected signals, which are selected by a user, through the key input unit 170, controls the RF tuner 110 in order to provide the channels or service functions, which are selected by a user, establishes a PID for a corresponding channel/service, and notifies the demultiplexer 210 of the established PID. Herein, the controller 100 may establish a PID so that two or more channels/services can be received by the selection of a user. Herein, in the case of the audio, the controller 100 controls only audio of a main channel set by a user to be demultiplexed. Then, if the channel/service function selected by a user begins, the controller 100 checks the PID and the type of data notified from the packet header processor 313 and the PES header processor 317 as described above, and outputs distribution control signals CTL 1 and output control signals CTL 2 to the data processor.

[57] The data processor 319 includes the distributor 511, the selector 513 and the buffer

515 as illustrated in FIG. 5. The distributor 511 distributes the ES data output from the PES header processor 317 by means of the distribution control signals CTL 1, and allows the distributed data to be buffered in a corresponding area of the buffer 515. Accordingly, the buffer 515 classifies and buffers the ES data according to corresponding PIDs and data type. The selector 513 accesses the data, which are buffered by the buffer 515, by means of the output control signals CTL 2, and selectively outputs the accessed data to corresponding decoders.

[58] FIG. 9 is a block diagram illustrating the detailed configuration of the data processor.

[59] Referring to FIG. 9, the buffer 515 includes a video buffer 521, an audio buffer 523 and a data buffer 525 of a selected main channel, and preliminary buffers 531 to 53N for storing information of multiple channels. The distributor 511 applies the received ES signals to the corresponding buffers 521, 523, 525 and 531 to 53N by means of the distribution control signals CTL 1 output from the controller 100 so that the ES signals can be buffered. That is, the distributor 511 distributes the received ES signals to buffers, which have been set to corresponding channels, by means of the distribution control signals CTL 1, respectively. Herein, the distributor 511 may be realized by a multiplexer, a switch, etc. Then, the buffers 521, 523, 525 and 531 to 53N buffer the ES signals distributed by and received from the distributor 511, respectively. The ES signals may be Network Access Layer (NAL) data in the case of an H.264 video, or AU data in the case of an AAC⁺ audio, according to the basic raw data type of video/ audio. Further, the ES signals may be data (e.g. MPE data, IP data, UDP data, FLUTE data and/or RTP data) of an intermediate step. Each of the buffers 521, 523, 525 and 531 to 53N is set to have a maintainable size while the selector 513 outputs the buffered data. It is assumed that each of the buffers 521, 523, 525 and 531 to 53N has a frame size in the embodiment of the present invention. Herein, the buffers 521, 523, 525 and 531 to 53N may be constructed by a plurality of memories as illustrated in FIG. 9, and may also be realized through area division of a single memory. In a case of using a method for dividing an area of the single memory, the entire memory space can be efficiently used. The ES signals buffered in the buffers 521, 523, 525 and 531 to 53N are selected by the selector 513, and are output to the corresponding decoders 230, 250 and 270, respectively. Herein, the output control signals CTL 2 are generated by the controller 100, and allow the data buffered in the buffers 521, 523, 525 and 531 to 53N to be output during one frame interval.

[60] The preliminary buffers 531 to 53N are used in FIG. 9, so that a plurality of signals can be processed, as compared with a case of processing audio or video signals one by one. Herein, PIDs for data broadcasting as well as video PIDs and audio PIDs may also be processed as multiple signals. Further, the video buffer 521 and the audio buffer 523 are provided for basic broadcasting reception, and additional video ESs or ESs for data broadcasting are buffered through the preliminary buffers 531 to 53N. Herein, the data buffer 525 may be omitted. In such a case, the data received when a data channel service is provided may be processed through the preliminary buffer 531. The data buffer 525 (preliminary buffer when the data buffer is used as a preliminary buffer) may be used as a buffer for storing a Conditional Access Table (CAT), a Network Information Table (NIT) and a Service Information Table (SIT), which are proposed by a MPEG standard, or information for data broadcasting including the data (MPE data, IP data, UDP data, FLUTE data and/or RTP data) of the intermediate step.

[61] Further, the video buffer 521 and the audio buffer 523 store the video and audio of a selected main channel. When a user selects one channel, only the video buffer 521 and audio buffer 523 are used. When a user selects multiple channels, the video buffer 521, the audio buffer 523 and the preliminary buffers 531 to 53N are used. In such a case, the preliminary buffers 531 to 53N may store video information of the multiple selected channels. That is, when the PIP function or multivision function is provided, it is preferred to use a plurality of video ESs and only one audio ES. Accordingly, the preliminary buffers 531 to 53N may be mainly used as video buffers. When multiple channels are selected and audio signals of more than two channels are reproduced, it is impossible to normally hear audio signals. Accordingly, only the audio signals of the main channel selected by a user are allowed to be reproduced.

[62] However, when the current mode is not the reproduction mode as described above, it is also possible to control audio signals of more than two channels to be buffered. That is, when the signals of one channel are reproduced and the signals of the other channel are recorded, the controller 100 controls the data processor 319 so that the video buffer 521 and the audio buffer 523 can buffer the video and audio signals of a channel to be reproduced, and controls the preliminary buffers 531 to 53N to buffer the video and audio signals of a channel to be recorded.

[63] FIG. 10 is a flow diagram illustrating a performance procedure of multiple channels/services in the digital broadcasting receiver according to the embodiment of the present invention.

[64] Referring to FIG. 10, the controller 100 analyzes channel/service selection of a user, which occurs in the key input unit 170. If a channel/service selection command occurs, the controller 100 determines if functions for two or more channels/services have been selected. If one channel/service is selected, the controller 100 detects the selection of said one channel/service in step 611. In steps 623 and 625, the controller 100 controls the packet header processor 313 and the data processor 319 to select, receive and process an ES for the selected PID.

[65] However, if a user selects two or more channels/services, the controller 100 must establish corresponding PIDs in order to perform the functions of the selected two or more channels/services. Further, the controller 100 allocates the buffers of the data processor 319 in order to store the ESs of the selected channels/services. That is, the video and audio ESs of the selected main channel are allocated to be buffered in the video buffer 521 and the audio buffer 523, respectively, and the preliminary buffers 531 to 53N are allocated in order to buffer the ESs of the selected remaining channels/ services.

[66] Accordingly, if two or more channels/services are selected, the controller 100 detects the selection of said two or more channels/services in step 611. In step 613, the controller 100 establishes PIDs for the selected channels/services, and transfers the established PIDs to the packet header processor 313. Then, the packet header processor 313 processes the multiple set packet headers as described above, and transfers the processing results to the controller 100 if a set packet is received. Further, the PES header processor 317 analyzes the data type (audio, video and service data) of a packet received by the frame, and transfers the analysis results to the controller 100. In step 615, the controller 100 generates the distribution control signals CTL 1 for buffering an ES for a corresponding PID, and controls the data processor 319 to process the ES. The distribution control signals CTL 1 correspond to signals for applying the ES, which is input to the data processor 319, to a buffer allocated in advance, and are determined by the PID and the data type. That is, the controller 100 can determine the PID and the data type of the received packet by means of the output of the packet header processor 313 and the PES header processor 317. As a result of the determination, the controller 100 generates the distribution control signals CTL 1 for buffering an ES in the set buffer of the data processor 319. Then, the distributor 511 applies the input ES to the corresponding buffer by the distribution control signals CTL 1, and the corresponding buffer buffers the applied ES.

[67] The controller 100 controls the data processor 319 to process the ES of the set PID as described above. In step 617, the controller 100 determines if an ES of one frame has been received. If the ES of one frame has not been received, the controller 100 determines if the procedure ends in step 621. If the procedure does not end, step 611 is performed and the afore-described operation is repeated. However, if the ES of one frame has been received, the controller 100 detects the reception of the ES in step 617 and selects a subsequent ES in step 619. Then, the controller 100 controls the packet header processor 313 so that a subsequent ES can be received in a subsequent step. Herein, the selection of the subsequent ES becomes possible by selecting a subsequent PID from a preset list of the PIDs.

[68] As described above, the ESs of multiple channels/services are buffered in the buffers 521, 523, 525 and 531 to 53N of the data processor 319. Further, the controller 100 accesses the ESs stored in the buffers 521, 523, 525 and 531 to 53N and outputs the accessed ESs to corresponding decoders, respectively. To this end, the controller 100 outputs the output control signals CTL 2 to the selector 513 of the data processor 319. The output control signals CTL 2 correspond to signals for selectively outputting the ESs stored in the buffers 521, 523, 525 and 531 to 53N to the decoders. That is, the output control signals CTL 2 allow the video ES to be output to the video decoder 230, allow the audio ES to be output to the audio decoder 250, and allow the service data ES to be output to the data decoder 270.

[69] FIG. 11 is a flow diagram illustrating a procedure for distributing the output of the demultiplexer 210 to decoders in the digital broadcasting receiver performing the functions of multiple channels/services according to the embodiment of the present invention.

[70] Referring to FIG. 11, the controller 100 determines if an ES has been added in step 651. If the ES has been added, the controller 100 adds the ES to an ES list, registers the ES and updates the ES list in step 655. However, if the ES has not been added, the controller 100 receives a current ES list in step 653. In step 657, the controller 100 determines if output selection has changed. If the output connection must change, the controller 100 changes the output control signals CTL 2, and controls the buffered ES to be output to a corresponding decoder in step 659. Herein, if the output control signals CTL 2 change, the selector 513 of the data processor 319 connects a buffer, which stores the currently selected ES, to a decoder for decoding a corresponding ES by means of the output control signals CTL 2, and outputs the ES to the decoder. However, if the output selection does not change, the controller 100 maintains the current output control signals CTL 2 intact, and the selector 513 of the data processor 319 controls the output of the buffer selected by the output control signals CTL 2 to be output to a set decoder. While repeating the operation as described above, the controller 100 changes the ES list and the output control signals CTL 2, and the data processor 319 transfers the ESs buffered in the buffers 521, 523, 525 and 531 to 53N to corresponding decoders under the control of the controller 100. The operation is repeated until the procedure ends. If the procedure ends, the controller 100 detects the end of the procedure in step 663, and terminates the routine.

[71] In the embodiment of the present invention, it is assumed that the decoders 230, 250 and 270 are separately formed. In such a case, the controller 100 must time-divide the output control signals CTL 2, properly distribute the divided signals in a frame interval, and transfer the ESs to corresponding decoders. Further, the decoders, particularly, the video decoder, must sequentially decode the ESs received through two or more channels, and output the decoded ESs to the display unit 150. Furthermore, two or more decoders, particularly, video decoders, are disposed in parallel, so that it is also possible to process the ESs of multiple channels. In such a case, it is possible to sufficiently maintain the decoding time of the decoders.

[72] FIG. 12 is a block diagram illustrating the construction of the demultiplexer 210 having a parallel structure, which is different from the demultiplexer having a serial structure as illustrated in FIG. 5.

[73] Referring to FIG. 12, a sync search unit 711 searches for sync signals included in each packet data of input TS signals, and transfers the input packet data to a buffer 713. The sync search unit 711 according to the embodiment of the present invention makes synchronization by means of a difference value delay scheme. The buffer 713 buffers serial data, which are output from the sync search unit 711, in the unit of packet.

[74] A packet header processor 715 searches for parallel packet header information output from the packet data of the buffer 713, and determines if the packet header in- formation includes an adaptation. If the packet header information does not include the adaptation, the packet header processor 715 operates only a PES header processor 719. However, if the packet header information includes the adaptation, the packet header processor 715 operates an adaptation processor 717. The packet header processor 715 extracts the packet header information from the input packet, processes the extracted packet header information. If the packet header information includes the adaptation, the packet header processor 715 transfers the packet data except for the packet header to the adaptation processor 717. However, if the packet header information does not include the adaptation, the packet header processor 715 transfers the packet data except for the packet header to the PES header processor 719.

[75] The adaptation processor 717 operates under the control of the packet header processor 715. If the packet data are transferred from the packet header processor 715, the adaptation processor 717 analyzes and processes the adaptation included in the packet data, and transfers remaining packet data except for the adaptation to the PES header processor 719.

[76] The PES header processor 719 extracts header information included in the packet data transferred from the packet header processor 715 or the adaptation processor 717, processes extracted header information, and transfers remaining packet data except for the PES header information to a data processor 721. Herein, the data processor 721 includes the distributor 511, the video buffer 521, the audio buffer 523, the data buffer 525, the preliminary buffers 531 to 53N and the selector 513, as illustrated in FIG. 12.

[77] After the PES header processor 717 processes the PES header, if remaining data except for the PES header include MPE data, an MPE data processor (not shown) extracts the MPE data, and processes the extracted MPE data, thereby generating IP data. Then, an IP data processor (not shown) extracts the IP data, processes the extracted IP data, thereby generating UDP data. Then, a UDP data processor (not shown) extracts the UDP data, processes the extracted UDP data, thereby generating FLUTE data and RTP data. Then, a FLUTE data processor (not shown) extracts the FLUTE data, processes the extracted FLUTE data, thereby generating ESG data and/or file data. An RTP data processor (not shown) extracts the RTP data, processes the extracted RTP data, thereby generating A/V raw data. Further, the FLUTE data processor and the RTP data processor transfer the generated ESG data and/or file data and the A/V raw data to the data processor 721.

[78] The data processor 721 may have the construction as illustrated in FIG. 9. The data processor buffers input ESs in the buffers 521, 523, 525 and 531 to 53N by means of the distribution control signals CTL 1 output from the controller 100, and transfers the ESs, which have been buffered in the buffers 521, 523, 525 and 531 to 53N, to corresponding decoders by means of the output control signals CTL 2. [79] As described above, the demultiplexer 210 includes four processors, i.e. the packet header processor, the adaptation processor, the PES header processor and the data processor. Each processor sequentially analyzes the packet data buffered in the buffer 713, and accesses and processes the packet data of the buffer 713 only if the packet data include information which must be processed by said each processor. Herein, the packet data may include a packet header, an adaptation header and a PES header. The header information may be included in the packet header, and vice versa. Accordingly, each of the processors 715, 717, 719 and 721 operates only if the packet data include information which must be processed by the processors 715, 717, 719 and 721, and processes the packet data. Herein, the data processing may be performed in parallel.

[80] In a case in which the digital broadcasting receiver includes the demultiplexer 210 having the parallel structure as illustrated in FIG. 12, corresponding processors analyze buffered packets and process in parallel information included in the packets, so that it is possible to improve a demultiplexing speed. Further, each processor accesses and processes packets stored in one buffer, so that the buffer can have a simplified construction and data transfer time can also be reduced. Herein, the data processor 721 includes a plurality of output buffers, processes ESs for multiple channels/services, and transfers the processed ESs to decoders. Accordingly, it is possible to process the ESs of multiple channels in one frame interval, and to support a service, such as a PIP and a multi vision, a plurality of data broadcasting and contents, etc., without deterioration in a frame rate.

[81] According to a digital broadcasting receiver of the present invention as described above, a data processor of a demultiplexer includes a plurality of output buffers, and can analyze PIDs for multiple channels/services established by a user, demultiplex the input ESs of multiple channels/services, and transfer the demultiplexed ESs to corresponding decoders. Consequently, it is possible to process the ESs of multiple channels in one frame interval, and to support a service, such as a PIP and a multi vision, a plurality of data broadcasting and contents, etc., without deterioration in a frame rate.

[82] Although preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims, including the full scope of equivalents thereof.

Claims

[ 1 ] A digital broadcasting receiver comprising: a tuner for selecting a channel of received digital broadcasting signals by channel selection of a controller; a demodulator for demodulating signals of the selected digital broadcasting channel; the controller for establishing identifiers for multiple channels according to setup of a user, generating distribution control signals of data when the data of the established identifiers are received, and generating output control signals for outputting the distributed data; a demultiplexer for receiving packet data of the established identifiers from the demodulated digital broadcasting signals, analyzing a type of the received packet data, transferring the identifiers and the type of the data to the controller, storing the received packet data in a buffer, which is set by the distribution control signals, as ES data, and demultiplexing the buffered ES data and outputting the demultiplexd data to corresponding decoders by the output control signals; a video decoder for decoding the demultiplexd video ES; an audio decoder for decoding the demultiplexd audio ES; a data decoder for decoding the demultiplexd service data ES; and a display unit for displaying the decoded video data, audio data and service data.

[2] The digital broadcasting receiver as claimed in claim 1, wherein the demultiplexer comprises: a packet header processor for analyzing a packet header of a stream output from the demodulator, bypassing a packet except for the packet header of the stream in a case of a stream of the established identifier, and transferring identifier information to the controller; an adaptation processor for processing an adaptation included in the packet output from the packet header processor, and bypassing a remaining packet except for the adaptation; a PES header processor for processing PES header information included in the packet output from the adaptation processor, bypassing a packet except for the PES header information and transferring the type of data to the controller when the packet includes the PES header information, and bypassing the ES data when the packet does not include the PES header information; and a data processor for buffering the ES data, which are output from the PES header processor, in the buffer selected by the distribution control signals, and outputting the buffered data to the corresponding decoders by the output control signals.

[3] The digital broadcasting receiver as claimed in claim 1, wherein the demultiplexer comprises: a packet header processor for analyzing a packet header of a stream output from the demodulator, analyzing a header of the buffered packet in a case of a stream of the established identifier, operating a corresponding decoder according to whether the packet includes an adaptation and/or a PES header, and transferring identifier information to the controller; an adaptation processor for processing the adaptation included in the buffered packet, the adaptation processor being driven by the packet header processor; a PES header processor for processing PES header information included in the packet output from the adaptation processor or the packet header processor, bypassing ES data except for the PES header information and transferring the type of data to the controller when the packet includes the PES header information, and bypassing the ES data when the packet does not include the PES header information; and a data processor for generating actual data included in the packet, which have been buffered in the buffer, as ES data, and outputting the ES data to a corresponding decoder, the data processor being driven by the PES header processor.

[4] The digital broadcasting receiver as claimed in claim 2 or 3, wherein the data processor comprises: buffers including a video buffer, an audio buffer and multiple preliminary buffers; a distributor for receiving the ES data and distributing the ES data to the buffer having been set by the distribution control signals; and a selector for outputting the ES data, which are stored in the buffer selected by the output control signals, to a set decoder.

[5] A decoding method in a digital broadcasting receiver, the method comprising the steps of: when multiple channels are selected, establishing corresponding identifier information; when data of the established identifier are received, receiving demodulated packet data, analyzing a type of the received packet data, and analyzing the identifier and the type of the packet data; storing ES data of the received packet in a buffer set by the analyzed identifier and type of the packet data; transferring the ES data stored in the buffer to a corresponding decoder, and allowing the ES data to be decoded; and displaying the decoded video and audio data.