EP1784975A1 - Bildverarbeitungseinrichtung und entsprechendes betriebsverfahren - Google Patents
Bildverarbeitungseinrichtung und entsprechendes betriebsverfahrenInfo
- Publication number
- EP1784975A1 EP1784975A1 EP05779122A EP05779122A EP1784975A1 EP 1784975 A1 EP1784975 A1 EP 1784975A1 EP 05779122 A EP05779122 A EP 05779122A EP 05779122 A EP05779122 A EP 05779122A EP 1784975 A1 EP1784975 A1 EP 1784975A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- image
- signal
- image processing
- processing device
- synchronizers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000012545 processing Methods 0.000 title claims abstract description 95
- 238000011017 operating method Methods 0.000 title claims abstract description 11
- 230000001360 synchronised effect Effects 0.000 claims description 15
- 230000008859 change Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims description 3
- 230000010363 phase shift Effects 0.000 claims description 2
- 108090000623 proteins and genes Proteins 0.000 claims 1
- 238000012937 correction Methods 0.000 description 11
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 241000721701 Lynx Species 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012800 visualization Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000033458 reproduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
- H04N5/067—Arrangements or circuits at the transmitter end
- H04N5/073—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
- H04N5/0736—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations using digital storage buffer techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2624—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3141—Constructional details thereof
- H04N9/3147—Multi-projection systems
Definitions
- Image processing device and corresponding
- the invention relates to an image processing device and a corresponding operating method according to the preamble of the independent claims.
- Image impression the combined graphic signal can then be distorted to compensate for the curvature of the screen.
- a disadvantage of the known graphics systems for combining various graphics signals is the fact that they require synchronized graphic signals on the input side.
- the graphics signals to be combined with one another are often asynchronous, which makes the combination with the known graphics systems more difficult or makes specially synchronized graphics systems necessary.
- an image processing ⁇ processing device is known, the input side different unsynchronized image input signals can record and synchronized to ⁇ next, whereupon the synchronized image ⁇ input signals then combined with a combiner to form an image output signal.
- This known image processing device thus advantageously enables the combination of unsynchronized image input signals.
- a disadvantage of the known image processing devices described above is the unsatisfactory image quality if a plurality of unsynchronized image input signals are to be combined with one another and subsequently geometrically distorted or equalized.
- the invention is therefore based on the object, an image processing device and a corresponding ⁇ Radiowave ⁇ drive to provide the output signals in the combination of several Schmein ⁇ and a geometric distortion correction processing or provides an improved image quality.
- the invention comprises an image processing device with a plurality of image signal inputs for receiving in each case one input image signal, wherein the individual image input signals generally reproduce one image or one image sequence in each case.
- the invention is not limited to a specific number of image ⁇ signal inputs, but the image processing device according to the invention preferably eight Stammsignalein ⁇ courses, so that a total of eight different image input signals can be recorded.
- the invention can also be implemented with a different number of image signal inputs, for example with two, four, six or more image signal inputs.
- the invention is preferably at least one image signal output for outputting an image output signal, wherein the Rickaus ⁇ input signal is an image or a sequence of images usually again ⁇ .
- the invention is also not limited to a single image signal output with regard to the number of image signal outputs. Rather, it is also possible to provide several image signal outputs in order to output a corresponding number of image output signals.
- the single image output signals can hereby derwe different images or image sequences as ⁇ .
- the different image signal outputs output image output signals in different data formats, wherein the different image output signals then the same image or the same
- the image processing device preferably ⁇ a combiner on to the ver ⁇ different image input signals with each other to the Schmaus- signal or to combine the individual image output signals.
- the image processing device permits each receiving unsynchronized input image signals so that the individual image signal inputs, a synchronizer is connected downstream of each chronisierer, the syn the unsynchronized image input signals for the subsequent combining ⁇ chronized.
- the combiner of Rickgnacsein ⁇ inventive device preferably comprises a programmable or confi ⁇ gurierbares switching circuit that supplies the various Rickein ⁇ output signals according to a predetermined, preferably variable programming combined with each other to the Schmausgangssig ⁇ nal and via a serial and / or parallel Pro ⁇ programming interface programmable or is configurable.
- the combination of the various image input signals can thus be adjusted at the pixel level by a corresponding programming of the programmable switching network, so that any combinations of the image input signals recorded on the input side are possible.
- the programmable switch network for combination discrimination of the different image input signals an FPGA (Field Programmable Gate Array) to, but in principle it is also possible that the combiner in the Inventive ⁇ image processing device according to a PLD (Programmable Logic Device) or a PAL (Programmable Array Logic).
- a PLD Programmable Logic Device
- PAL Programmable Array Logic
- the combiner of the image processing device according to the invention is connected to a read-write memory whose content determines the combination of the image input signals.
- a read-write memory whose content determines the combination of the image input signals.
- This may be, for example, a DDR RAM, which may for example have a memory capacity of 128 MBit.
- the combiner is connected to a read-only memory which holds a start configuration for the combiner, wherein the start combination is loaded into the combiner when switched on.
- This read-only memory may be, for example, a JTAG flash memory, but the invention is not restricted to this type of memory with regard to the memory type for the read-only memory for storing the start configuration.
- the image processing means comprises a Signalver ⁇ splitter on the input side signal inputs having at least one of the image ⁇ and on the output side to at least two of the synchronizer is connected, said signal splitter, the input side image input signal from ⁇ input side to the signal distributor distributed Synchroni ⁇ sierer distributed.
- This distribution of an image input signal to a plurality of synchronizers may be expedient in order to circumvent bandwidth limitations of the synchronizers and to process image input signals with very high bandwidth requirements by synchronizing and distorting in common a plurality of synchronizers, the synchronized component signals then from the combiner again be combined accordingly.
- the signal distributors are programmable in order, depending on the programming, to supply each image input signal in each case to one of the synchronizers or to apply the individual image input signals to a plurality of the respective ones
- the Schmverar ⁇ invention beitungs shark has in this case at least two operating modes, wherein the signal distribution in a type of operation are inactive and can be activated in a different mode, wells to distribute the individual image input signals depending ⁇ several of the synchronizer.
- a signal distributor is connected in pairs to the individual image signal inputs, wherein the individual signal distributors are preferably individually programmable.
- the individual signal distributors are preferably individually programmable.
- the invention preferably processing means comprises a central clock which on the output side with all synchronizers connected is. This makes it possible for the individual image input signals to be synchronized by the individual synchronizers independently of their frequency and resolution, so that they are available in pixel-precise synchronized form at the outputs of the synchronizers.
- the image processing device can have an external synchronization connection in order to synchronize the image processing device with other image processing devices.
- the invention trains kausein ⁇ direction on at least one or distortion equalizer to the individual image input signals before the combining to the image output signal individually each to distort or pull ⁇ to ent.
- the distortion or equalizer is formed by the individual synchronizers, which thus have two functions, namely, on the one hand the synchronization of the image input signals and, on the other hand, their distortion or equalization.
- This is done, for example, by the chip type sxTl from Silicon Optix, which also has the nickname "Reon".
- the invention is not limited to chips of this type in terms of synchronization, but in principle also feasible with other types of chips.
- the synchronizers are biofunctional in that, in addition to the synchronization of the input signals, they also enable their distortion or equalization.
- the synchronizer as loading recorded in this description blocks can also be called a correction modules due to their bi-functionality, the Cor ⁇ rekturbausteine or th synchronizer following advantages bie ⁇ .
- the combination of several correction blocks or synchronizers using a uniform clock allows the synchronization of different inputs.
- each correction module or synchronizer can correct different resolutions or clock rates of the image signal inputs, so that a uniform image signal is output at the output of each correction module or synchronizer and forwarded to the combiner.
- the individual correction modules or Synchro ⁇ can rigieren kor ⁇ the brightness and / or color of the image signal individually nisierer geometric and / or with respect to.
- the individual correction modules or synchronizers can individually crop and resize the respective image signal (enlargement and reduction), whereby only a part of the respective image signal is forwarded to the combiner.
- a distortion or equalization of image signals is therefore meant geometrically and not telecommunications technology and includes not only the geometric correction of the image content and the correction of the brightness and the color information.
- the individual synchronizers preferably each have a control input, via which a picture change can be triggered, wherein the control inputs of the individual synchronizers are preferably connected together with the combiner in order to record a common trigger signal from the combiner.
- This joint control of the individual synchronizers by the combiner allows a synchronous picture change, which is usually a prerequisite for the subsequent combination.
- the individual synchronizers are vorzugswei- se via a respective configuration input configurable, wherein each of the configuration inputs of Synchronisie ⁇ rer are connected via a multiplexer to the combiner.
- the combiner can address and configure all synchronizers via the multiplexer.
- the image signal output of the image processing device can be connected to a picture display device, such as a projector or a monitor.
- An advantageous field of application of the image processing device according to the invention consists in the distributed Slo ⁇ calculation in a plurality of nodes of a graphics cluster, if the computational capacity of the individual nodes in each case only be ⁇ seeks not sufficient.
- the image calculation is distributed in the form of multiple graphing machines that each edited only a part of the image.
- the coordination of these pa ⁇ rallelen image calculation can for example be taken over by a computer Steuer ⁇ .
- the partial signals processed by the individual graphics computers are then supplied to the image signal inputs of the image processing device according to the invention, synchronized and then combined again.
- the invention also includes an operating method for an image processing device according to the invention, which already appears from the above description.
- Figure 1 is a simplified block diagram of an OF INVENTION ⁇ to the invention image processing means for combining eight input image signals to four image output signals,
- FIG. 2 shows the signal distributors of the image processing device from FIG. 1,
- FIG. 3 is a more detailed block diagram of a portion of the image processor of FIG. 1;
- FIG. 4 shows a graphics system according to the invention with a graphics cluster for parallel processing of graphics signals
- FIG. 5 shows a graphics system for the projection of image signals
- Figure 6 is a simplified block diagram of an OF INVENTION ⁇ to the invention the image processing system with several graphics computers as an image signal sources and the image processing device according to the invention for combining this image input signals so as ⁇ Figure 7A, 7B, a timing diagram according to FIG interpreting light the coarse synchronization of the image signals input in the graphics computers the image processing system 6 ⁇ ver.
- FIG. 1 shows an exporting ⁇ insurance for a Schmakusein ⁇ inventive device 1 for combining eight unsynchronized Scheme ⁇ input signals Video In 1, ..., Video 8, gang signals to four Schmaus- Video Out 1, ..., Video Out 4.
- Video In 1 For receiving the individual unsynchronized Jardineingangs ⁇ signals Video In 1, ..., Video In 8 has ⁇ use image processing device 1 a plurality of digital input interface 9 2- (DVI-D: Digital Video Interface).
- DVI-D Digital Video Interface
- the individual pixel information is transmitted in each case in the form of an 8-bit value, the image value for the primary colors red, yellow and blue being transmitted in parallel for each pixel.
- the individual input interfaces 2-9 are connected on the output side in pairs to a plurality of signal distributors 10-13, the structure of which is shown in greater detail in FIG. 2 and will be described in detail later.
- the individual signal distributors 10-13 are connected to eight synchronizers 14-21 which receive two image signals from the individual signal distributors 10-13 and synchronize them.
- the synchronizers 14-21 are in this embodiment, to the chips of the type sxTl by Silicon Optix, also referred to as "Reon" ⁇ the.
- the image signals synchronized by the synchronizers 14-21 are then supplied to a combiner 22, where it is a FPGA (Field Programmable Gate Array) of the Virtex-II type from XILINX.
- the combiner 22 combinatorial ⁇ nes the input side captured image signals entspre ⁇ accordingly a given programming (not shown here provides) to the image output signals Video Out 1, ..., Video Out 4 and outputs it to multiple output interfaces 23-26.
- the image processing device 1 has a parallel interface 27 and a serial interface 28 in order to configure the image processing device 1.
- the image processing device 1 has a central clock generator 29, which is connected on the output side to the synchronizers 14-21.
- This common timing of the individual synchronizers 14-21 allows the video input signals Video In 1, ..., Video In 8 to be synchronized independently of their frequency and resolution so that they are pixel-exactly synchronized at the outputs of the synchronizers 14-21 be available.
- the combiner 22 is connected via a multiplexer 30 to the individual synchronizers 14-21 in order to configure them individually.
- the combiner 22 is connected to the individual signal splitters 10-13 in order to be able to switch over between two operating modes.
- the signal distributor ⁇ 10-13 are inactive, so that the two respectively adjacent the input side image input signals to the accompanying
- Synchronizers are switched through.
- the signal distributors 10-13 are actively switched so that only the image input signal applied to one of the two signal inputs is output to the two connected synchronizer is distributed.
- Triebsart in this Be ⁇ can also image input signals to be processed, whose bandwidth is greater than the maximum processing ⁇ bandwidth of the synchronizer 14-21.
- the signal distributor 10 On the input side, the signal distributor 10 includes two TMDS receivers 31, 32 on the input side gear interfaced with the two A ⁇ 2, 3 are connected and a 48-bit brei ⁇ generate tes RGB signal.
- the TMDS receiver 32 in the one of the two parallel branches can be switched inactive by the combiner 22 via a control line 33 and an inverter 34 so that the TMDS receiver 32 does not output an image signal.
- an amplifier 35 is further arranged REN outputted from the TMDS receiver 31 image signal to the synchronizer 15 of the walls ⁇ signal processing branch may pass.
- the amplifier 35 can likewise be switched inactive by the combiner 22 via the control line 33, the inverter 34 and a further inverter 36.
- the two inverters 34, 36 thus ensure that either the TMDS receiver 32 or the amplifier 35 is actively switched. This means that, depending on the control via the control line 33, either the two image input signals taken in on the input side Video I 1 Video In 2 are forwarded to the downstream synchronizers 14, 15 without any further change or that only the input side divided image input signal Video In 1 is divided and distributed to the two synchronizers 14, 15.
- This division of the image input signals recorded on the input side makes it possible to circumvent bandwidth limitations of the synchronizers 14-21 and to process image input signals of high bandwidth.
- each of the synchronizers 14, 15 is connected to a random access memory 39, 40 in which the image data is buffered.
- the combiner 22 is further connected to a memory 41 in which the start configuration for the combiner 22 is stored, the start configuration being loaded from the memory 41 into the combiner 22 when the system is switched on.
- the memory 41 is a JTAG flash memory. Below the Ausure ⁇ shown in Figure 4 will be approximately for a graphics system according to the invention beschrie ⁇ ben.
- the individual graphics computers 44-47 are with egg ⁇ ner inventive image processing device 48 connectedness, which synchronizes the unsynchronized output signals of ein ⁇ individual graphics computers 44-47 and brings together so that the output of the image processing device 48, a combined image output signal is Video Out.
- This image output signal Video Out is fed to a projector 49, which projects an image onto a curved projection surface 50.
- the curvature of the projection surface 50 is compensated by a correspondingly complementary distortion in the synchronizers of the image processing device 48, so that the image on the projection surface 50 appears undistorted despite the curvature of the projection surface 50.
- FIG. 5 The embodiment of a graphics system according to the invention shown in FIG. 5 will now be described below, in which two image input signals Video In 1, Video In 2 are fed to an image processing device 51 according to the invention, which supplies the image input signals Video In I 1 Vi ⁇ deo In 2 geometrically distorted to compensate for the curvature of a projecting surface 52, and in the brightness and Corrected color to compensate for differences between the projectors 53, 54.
- the image processing device 51 is connected to two projectors 53, 54, which project the two image output signals Video Out 1, Video Out 2 onto the projection surface 52.
- the two images projected by the projectors 53 and 54 overlap.
- the image processing device ermög ⁇ light for the image signals in this area a brightness ⁇ correction, allowing a so-called "edge blending".
- Figure 6 shows a simplified block diagram of an OF INVENTION ⁇ to the invention the image processing system with multiple graphics ⁇ computers 60, 61, 62, 63, each providing an image input signal, wherein the provided from the graphics computers 60-63 ge presented image input signals are unsynchronized.
- the illustrated image processing system has an image processing device 64 according to the invention with a plurality of image signal inputs 65-72 and a plurality of image signal outputs 73-76.
- the image signal inputs 65-72 are fed by the graphics computers 60-63 with the unsynchronized image input signals.
- the individual image signal inputs 65-72 is beitungs addressed in the Syndromeverar ⁇ 64 each a so-called chip WARP 77- 84 downstream, wherein it is in each case substantially to a synchronizer which synchronizes the input side up ⁇ recessed unsynchronized image input signals with each other.
- WARP output side, the chips are rer with a Kombinie ⁇ 77-84 85 connected in the form of a FPGA.
- the combiner 85 is in turn connected on the output side via several TMDS transmitters 86-89 to the image signal outputs 73-76.
- the image processing device 64 in this embodiment a plurality of analog output Thomasseilen 90-93.
- phase difference between the image input signals recorded by the graphics computers 60-63 is determined in the image processing device 64 and fed back to the graphics computer 60-63 via an interface 94.
- the Gardnerrech ⁇ ner 60-63 then perform a coarse synchronization of the fed into the image processing device 64 Schmdeangs ⁇ signals, so that the image processing device 64 then has to make only a fine synchronization of the Schmendessigna ⁇ le.
- the image processing device 64 makes use of an synchronization opportunity, which can synchronize the image signals pixel accuracy, so that the captured via the image signal inputs 65-72 image input signals synchronously up pixel ( "the GENLOCK”) available Müs ⁇ sen.
- the image input signals are already roughly synchronized available. It is only important here that the time of each frame start (“FRAMESYNC”) is not more than 5-10 ° out of phase with the other image input signals (“FRAMELOCK”).
- the output signals (“GENLOCK”) are then passed through the WARP chips 77-84 of the image processing device 64.
- the coarse synchronization of the image input signals fed into the image processing device 64 can be realized in the graphics computers 60-63 by a software routine which lengthens or shortens the length of the vertical blanking interval of the image signals, as can be seen from the time diagrams in FIGS. 7A and 7B , For this purpose, only the information about the actual phase shift of
- VIDEO IN 1 1, ..., VIDEO IN 8 video input signals
- VIDEO OUT 1 VIDEO OUT 1
- ... r VIDEO OUT4 Video output signals
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004042166A DE102004042166A1 (de) | 2004-08-31 | 2004-08-31 | Bildverarbeitungseinrichtung und entsprechendes Betriebsverfahren |
PCT/EP2005/054282 WO2006024646A1 (de) | 2004-08-31 | 2005-08-31 | Bildverarbeitungseinrichtung und entsprechendes betriebsverfahren |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1784975A1 true EP1784975A1 (de) | 2007-05-16 |
Family
ID=35169538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05779122A Ceased EP1784975A1 (de) | 2004-08-31 | 2005-08-31 | Bildverarbeitungseinrichtung und entsprechendes betriebsverfahren |
Country Status (4)
Country | Link |
---|---|
US (1) | US8045052B2 (de) |
EP (1) | EP1784975A1 (de) |
DE (1) | DE102004042166A1 (de) |
WO (1) | WO2006024646A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7986217B2 (en) * | 2007-09-27 | 2011-07-26 | Intel Corporation | Mitigating processing latency in RFID exchanges |
TWI457877B (zh) * | 2010-01-07 | 2014-10-21 | Univ Nat Taipei Technology | 顯示牆系統及高解析度影像生成顯示方法 |
US20130324874A1 (en) * | 2012-06-01 | 2013-12-05 | Xerox Corporation | Minute ventilation estimation based on chest volume |
Citations (3)
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US20010035912A1 (en) * | 1993-07-26 | 2001-11-01 | Pixel Instruments Corp. | Apparatus and method for processing television signals |
US6340991B1 (en) * | 1998-12-31 | 2002-01-22 | At&T Corporation | Frame synchronization in a multi-camera system |
US6507370B1 (en) * | 2000-03-20 | 2003-01-14 | International Business Machines Corporation | Highly adjustable video composite sync separator and variable gain pixel clock frequency locking apparatus and method |
Family Cites Families (17)
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DD228136A1 (de) * | 1982-09-23 | 1985-10-02 | Post Rundfunk U Fernsehtechnis | Schaltungsanordnung zur erzeugung eines gemischten videosignals |
US5057910A (en) * | 1987-02-20 | 1991-10-15 | Magni Systems, Inc. | Method of displaying video signal phase characteristics |
US5136390A (en) * | 1990-11-05 | 1992-08-04 | Metavision Corporation | Adjustable multiple image display smoothing method and apparatus |
US5499375A (en) * | 1993-06-03 | 1996-03-12 | Texas Instruments Incorporated | Feedback register configuration for a synchronous vector processor employing delayed and non-delayed algorithms |
US5550594A (en) * | 1993-07-26 | 1996-08-27 | Pixel Instruments Corp. | Apparatus and method for synchronizing asynchronous signals |
US5760729A (en) * | 1995-05-01 | 1998-06-02 | Thomson Consumer Electronics, Inc. | Flash analog-to-digital converter comparator reference arrangement |
US6215898B1 (en) * | 1997-04-15 | 2001-04-10 | Interval Research Corporation | Data processing system and method |
US7299405B1 (en) * | 2000-03-08 | 2007-11-20 | Ricoh Company, Ltd. | Method and system for information management to facilitate the exchange of ideas during a collaborative effort |
US7405734B2 (en) * | 2000-07-18 | 2008-07-29 | Silicon Graphics, Inc. | Method and system for presenting three-dimensional computer graphics images using multiple graphics processing units |
FR2815805B1 (fr) * | 2000-10-23 | 2005-09-02 | Telediffusion De France Tdf | Procede de synchronisation de signaux numeriques |
EP1449357A4 (de) | 2001-06-19 | 2006-10-04 | Ecole Polytech | Verfahren und system zum kombinieren von videosignalen mit räumlich-zeitlicher ausrichtung |
WO2003019512A2 (en) * | 2001-08-22 | 2003-03-06 | Gary Alfred Demos | Method and apparatus for providing computer-compatible fully synchronized audio/video information |
US7308059B2 (en) * | 2002-02-06 | 2007-12-11 | Broadcom Corporation | Synchronization of data links in a multiple link receiver |
US20030222987A1 (en) * | 2002-05-30 | 2003-12-04 | Karazuba Paul M. | Line scan image recording device with internal system for delaying signals from multiple photosensor arrays |
EP1427197A1 (de) | 2002-12-03 | 2004-06-09 | Ming-Ho Yu | Vorrichtung zur Erzeugung von Fernsehwerbeinhalten und zur Einfügung von interstitiellen Werbungen in Fernsehprogrammen |
US20040131276A1 (en) | 2002-12-23 | 2004-07-08 | John Hudson | Region-based image processor |
DE10314105A1 (de) * | 2003-03-28 | 2004-01-08 | Bts Media Solutions Gmbh | Verfahren zur Steuerung einer Einrichtung zur Verteilung und Bearbeitung von Videosignalen |
-
2004
- 2004-08-31 DE DE102004042166A patent/DE102004042166A1/de not_active Withdrawn
-
2005
- 2005-08-31 EP EP05779122A patent/EP1784975A1/de not_active Ceased
- 2005-08-31 US US11/574,458 patent/US8045052B2/en not_active Expired - Fee Related
- 2005-08-31 WO PCT/EP2005/054282 patent/WO2006024646A1/de active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20010035912A1 (en) * | 1993-07-26 | 2001-11-01 | Pixel Instruments Corp. | Apparatus and method for processing television signals |
US6340991B1 (en) * | 1998-12-31 | 2002-01-22 | At&T Corporation | Frame synchronization in a multi-camera system |
US6507370B1 (en) * | 2000-03-20 | 2003-01-14 | International Business Machines Corporation | Highly adjustable video composite sync separator and variable gain pixel clock frequency locking apparatus and method |
Non-Patent Citations (1)
Title |
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See also references of WO2006024646A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006024646A1 (de) | 2006-03-09 |
US8045052B2 (en) | 2011-10-25 |
DE102004042166A1 (de) | 2006-03-16 |
US20090040394A1 (en) | 2009-02-12 |
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