EP1776766A2 - Consumer device comprising a signal converter - Google Patents
Consumer device comprising a signal converterInfo
- Publication number
- EP1776766A2 EP1776766A2 EP05759918A EP05759918A EP1776766A2 EP 1776766 A2 EP1776766 A2 EP 1776766A2 EP 05759918 A EP05759918 A EP 05759918A EP 05759918 A EP05759918 A EP 05759918A EP 1776766 A2 EP1776766 A2 EP 1776766A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- signal
- input
- coupled
- transistor
- consumer device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B29/00—Generation of noise currents and voltages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
- H03M3/33—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither the dither being a random signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
- H03M7/3008—Compensating for, or preventing of, undesired influence of physical parameters by averaging out the errors, e.g. using dither
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
Definitions
- the invention relates to a consumer device comprising a signal converter, and also relates to a signal converter for use in a consumer device, and to a method for converting signals in a consumer device, and to a processor program product for converting signals in a consumer device.
- Examples of such a consumer device are HiFi systems, CD players/recorders, MP3 players/recorders, wired and/or wireless and/or mobile telephones, televisions, video players/recorders, DVD players/recorders and computers.
- a prior art consumer device is known from US 6,326,911, which discloses a signal converter in the form of a delta-sigma modulator for converting an input signal into an output signal.
- this input signal being a slowly varying signal or having a small amplitude or comprising a DC component
- the output signal will comprise noise known as pattern noise or idle tones.
- a dither generator is used.
- This dither generator comprises a pseudo random number generator coupled to a digital-to-analog converter, and generates a dither signal which is added to (a derivation of) the input signal.
- This dither signal decorrelates the pattern noise or idle tones. As a result, the pattern noise or idle tones are attenuated or reduced.
- the known consumer device is disadvantageous, inter alia, owing to the fact that the dither generator generates a dither signal based on a pseudo random sequence.
- the pseudo random sequence will be relatively short. As a result, the noise pattern or idle tones are decorrelated insufficiently.
- the consumer device according to the invention comprises a signal converter for converting an input signal into an output signal, which signal converter comprises a chaotic dither generator for generating a chaotic dither signal for reducing idle tones in the output signal. By introducing a chaotic dither generator, a dither signal is generated which is no longer based on a pseudo random sequence. As a result, the noise pattern or idle tones are decorrelated sufficiently.
- the consumer device according to the invention is further advantageous in that the signal converter has a good price/performance ratio.
- a chaotic dither generator for example comprises a relatively large resistor coupled to a high-gain high-bandwidth amplifier for amplifying the thermal noise of the relatively large resistor.
- US 6,404,260 discloses in its Figure 7 a chaotic circuit for generating a chaotic dither signal for dithering a clock signal. This is done to reduce the size of spikes of electromagnetic radiation generated by a circuit that uses this clock signal. Therefore, US 6,404,260 is related to protecting (performances of) other devices in the near environment. The invention is related to improving the performance of the consumer device itself and is not related to dithering clock signals.
- An embodiment of the consumer device according to the invention is defined by the signal converter constituting an oversampling converter. Especially in oversampling converters, the dither generator is of high importance.
- An embodiment of the consumer device according to the invention is defined by the signal converter constituting a sigma delta modulator or a delta sigma modulator. Especially in sigma delta modulators or a delta sigma modulators, the dither generator is of high importance.
- An embodiment of the consumer device according to the invention is defined by the signal converter further comprising a loop filter, a combiner and a quantizer, an output of the loop filter being coupled to a first input of the combiner, an output of the chaotic dither generator being coupled to a second input of the combiner, and an output of the combiner being coupled to an input of the quantizer.
- the combiner for example comprises an adder. Such an adder is a low cost circuit for adding a dither signal to (a derivation of) an input signal.
- An embodiment of the consumer device is defined by the loop filter being an analog loop filter, the combiner being an analog combiner, and the chaotic dither generator being coupled to the analog combiner via an interface.
- the interface for example comprises voltage controlled current sources for converting voltage signals originating from the chaotic dither generator into currents destined for the combiner.
- An embodiment of the consumer device according to the invention is defined by the loop filter being a digital loop filter, the combiner being a digital combiner, and an output of the quantizer being fed back to an input of the loop filter via a feedback circuit. This is a digital solution.
- An embodiment of the consumer device is defined by the chaotic dither generator comprising a transistor circuit and an amplifier, an output of the transistor circuit being coupled via a first switch to an input of the amplifier and an output of the amplifier being coupled via a second switch to an input of the transistor circuit.
- this chaotic dither generator comprising the transistor circuit and the amplifier will have a lower power consumption and will be less expensive owing to the fact that the amplifier does not need to be a high-gain high-bandwidth amplifier.
- An embodiment of the consumer device according to the invention is defined by the chaotic dither generator further comprising a first capacitor coupled to the input of the transistor circuit and a first reference terminal and a second capacitor coupled to the input of the amplifier and a second reference terminal. Both capacitors have storage functions.
- An embodiment of the consumer device is defined by the transistor circuit comprising a first transistor comprising a control electrode constituting the input of the transistor circuit and coupled to a control electrode of a second transistor, a first main electrode of the second transistor being coupled to a third reference terminal and a second main electrode of the second transistor constituting the output of the transistor circuit and being coupled to a first main electrode of the first transistor, a second main electrode of the first transistor being coupled to a fourth reference terminal, which fourth reference terminal is further coupled to a first main electrode of a third transistor, a second main electrode of the third transistor being coupled to the second main electrode of the second transistor, and a control electrode of the third transistor constituting a biasing input of the transistor circuit.
- the signal converter according to the invention for use in a consumer device for converting an input signal into an output signal is defined by comprising a chaotic dither generator for generating a chaotic dither signal for reducing idle tones in the output signal.
- the method according to the invention for converting an input signal into an output signal in a consumer device is defined by comprising the step of generating a chaotic dither signal for reducing idle tones in the output signal.
- the processor program product according to the invention for converting an input signal into an output signal in a consumer device is defined by comprising the function of generating a chaotic dither signal for reducing idle tones in the output signal.
- Embodiments of the signal converter according to the invention and of the method according to the invention and of the processor program product according to the invention correspond with the embodiments of the consumer device according to the invention, whereby a filter corresponds with a filtering step/function, a combiner corresponds with a combining step/function and a quantizer corresponds with a quantizing step/function etc.
- the invention is based upon an insight, inter alia, that dither signals based on pseudo random sequences decorrelate idle tones insufficiently, unless the pseudo random sequences are sufficiently long, which makes the signal converter expensive, and is based upon a basic idea, inter alia, that a chaotic dither generator for generating a chaotic dither signal for reducing idle tones in the output signal is to be used.
- the invention solves the problem, inter alia, to provide a consumer device comprising a low cost signal converter in which the idle tones are decorrelated sufficiently, and is advantageous, inter alia, in that this signal converter has a good price/performance ratio.
- Fig. 1 shows diagrammatically a first embodiment of a consumer device according to the invention comprising a signal converter according to the invention
- Fig. 2 shows diagrammatically a second embodiment of a consumer device according to the invention comprising a signal converter according to the invention
- Fig. 3 shows diagrammatically a first embodiment of a chaotic dither generator
- Fig 4 shows diagrammatically a second embodiment of a chaotic dither generator
- Fig. 5 shows a non-linear input-output characteristic of a transistor circuit for the dither generator shown in Fig. 4; and Fig. 6 shows diagrammatically the transistor circuit for the dither generator shown in Fig. 4.
- the consumer device 1 comprises a signal converter 2 for converting an input signal into an output signal, which signal converter 2 comprises a chaotic dither generator 3 for generating a chaotic dither signal for reducing idle tones in the output signal.
- the signal converter 2 for example constitutes an oversampling converter.
- the signal converter 2 further comprises an analog loop filter 4, an analog combiner 5,6 and an analog quantizer 7.
- An output of the analog loop filter 4 is coupled to a first input of the analog combiner 5,6, an output of the chaotic dither generator 3 is coupled to a second input of the analog combiner 5,6 via an interafce 8, and an output of the analog combiner 5,6 is coupled to an input of the analog quantizer 7.
- the output of the analog loop filter 4 comprises two sub-outputs
- the input of the analog quantizer 7 comprises two sub-inputs
- the analog combiner 5,6 comprises two analog adders 5 and 6, each one having a first sub- input which first sub- inputs together constitute the first input of the combiner 5,6 and each one having a second sub- input which second sub-inputs together constitute the second input of the combiner.
- the interface 8 couples an output of the chaotic dither generator 3 to the second sub-inputs of the analog adders 5 and 6.
- the interface 8 for example comprises voltage controlled current sources for converting voltage signals originating from the chaotic dither generator 3 into currents destined for the combiner 5,6.
- the consumer device 11 comprises a signal converter 12 for converting an input signal into an output signal, which signal converter 12 comprises a chaotic dither generator 13 for generating a chaotic dither signal for reducing idle tones in the output signal.
- the signal converter 12 for example constitutes a sigma delta modulator or a delta sigma modulator.
- the signal converter 12 further comprises a digital loop filter 14, a digital combiner 15 and a digital quantizer 17.
- An output of the digital loop filter 14 is coupled to a first input of the digital combiner 15, an output of the chaotic dither generator 13 is coupled to a second input of the digital combiner 15, and an output of the digital combiner 15 is coupled to an input of the digital quantizer 17.
- the digital combiner 15 comprises a digital adder.
- the digital quantizer is fed back to a first input of a digital adder 16 via a feedback circuit 18.
- a second input of this digital adder 16 forms the input of the signal converter 12, and an output of the digital adder 16 is coupled to an input of the loop filter
- the output signal will comprise noise known as pattern noise or idle tones.
- the chaotic dither generator 3,13 is used to reduce or attenuate such pattern noise or idle tones.
- This chaotic dither generator 3,13 generates a dither signal which is added to (a derivation of) the input signal.
- This dither signal decorrelates the pattern noise or idle tones. As a result, the pattern noise or idle tones are attenuated or reduced.
- the chaotic dither generator 23 shown in Fig. 3 comprises a relatively large resistor 24 coupled to ground and to an input of a high-gain high-bandwidth amplifier 25.
- An output of this high-gain high-bandwidth amplifier 25 is coupled to a (positive or non-inverting) input of an amplifier 26, a (negative or inverting) input of this amplifier 26 is coupled to ground.
- the amplifier 26 receives a clock signal at its input 27 and generates a chaotic dither signal at its output 28.
- the chaotic dither generator 33 further comprises a first capacitor 38 coupled to the input 44 of the transistor circuit 34 and ground and a second capacitor 39 coupled to the input of the amplifier 35 and ground. Both capacitors have storage functions.
- the chaotic dither generator 33 At its output 40 corresponding with the input 44 of the transistor circuit 34, the chaotic dither generator 33 generates a chaotic dither signal.
- the transistor circuit 34 for the dither generator 33 shown in Fig. 6 the transistor circuit 34 for the dither generator 33 shown in Fig.
- NMOS first transistor 41
- NMOS complementary metal-oxide-semiconductor
- a first main electrode (source) of the second transistor 42 is coupled to ground and a second main electrode (drain) of the second transistor 42 constitutes the output 45 of the transistor circuit 34 and is coupled to a first main electrode (source) of the first transistor 41.
- a second main electrode (drain) of the first transistor 41 is coupled to a fourth reference terminal 47 constituting a supply voltage, which fourth reference terminal 47 is further coupled to a first main electrode (source) of a third transistor 43 (PMOS).
- a second main electrode (drain) of the third transistor 43 is coupled to the second main electrode (drain) of the second transistor 42.
- a control electrode (gate) of the third transistor 43 constitutes a biasing input 46 of the transistor circuit 34.
- Other kinds of transistors and transistor circuits are not to be excluded.
- the non- linear input-output characteristic of the transistor circuit 34 for the dither generator 33 is shown in Fig. 5.
- the shape of the curve is changed.
- the consumer device 1,11 according to the invention further comprises for example stages not shown. These stages comprise for example an input stage for example comprising a receiver for receiving signals and/or a source for generating signals, a signal processing stage for processing signals and comprising, inter alia, the signal converter 2,12 according to the invention, and an output stage for example comprising a transmitter for transmitting signals and/or an amplifier for amplifying signals and/or a reproducer for reproducing signals etc.
- stages comprise for example an input stage for example comprising a receiver for receiving signals and/or a source for generating signals, a signal processing stage for processing signals and comprising, inter alia, the signal converter 2,12 according to the invention, and an output stage for example comprising a transmitter for transmitting signals and/or an amplifier for amplifying signals and/or a reproducer for reproducing signals etc.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05759918A EP1776766A2 (en) | 2004-07-22 | 2005-07-12 | Consumer device comprising a signal converter |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04300460 | 2004-07-22 | ||
| EP05759918A EP1776766A2 (en) | 2004-07-22 | 2005-07-12 | Consumer device comprising a signal converter |
| PCT/IB2005/052301 WO2006011083A2 (en) | 2004-07-22 | 2005-07-12 | Consumer device comprising a signal converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1776766A2 true EP1776766A2 (en) | 2007-04-25 |
Family
ID=35058974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP05759918A Withdrawn EP1776766A2 (en) | 2004-07-22 | 2005-07-12 | Consumer device comprising a signal converter |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1776766A2 (en) |
| JP (1) | JP2008507878A (en) |
| KR (1) | KR20070035099A (en) |
| CN (1) | CN101023584A (en) |
| WO (1) | WO2006011083A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2436178A (en) * | 2006-03-13 | 2007-09-19 | Matsushita Electric Industrial Co Ltd | A scheme to alleviate signal degradation caused by digital gain control loops. |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745061A (en) * | 1995-07-28 | 1998-04-28 | Lucent Technologies Inc. | Method of improving the stability of a sigma-delta modulator employing dither |
| US6326911B1 (en) * | 1997-11-19 | 2001-12-04 | Texas Instruments Incorporated | Method and apparatus for dithering idle channel tones in delta-sigma analog-to-digital converters |
-
2005
- 2005-07-12 CN CNA2005800318441A patent/CN101023584A/en active Pending
- 2005-07-12 EP EP05759918A patent/EP1776766A2/en not_active Withdrawn
- 2005-07-12 KR KR1020077004019A patent/KR20070035099A/en not_active Withdrawn
- 2005-07-12 JP JP2007522084A patent/JP2008507878A/en active Pending
- 2005-07-12 WO PCT/IB2005/052301 patent/WO2006011083A2/en not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2006011083A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070035099A (en) | 2007-03-29 |
| WO2006011083A3 (en) | 2006-06-08 |
| WO2006011083A2 (en) | 2006-02-02 |
| JP2008507878A (en) | 2008-03-13 |
| CN101023584A (en) | 2007-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6605991B2 (en) | Circuitry for creating a spectral null in a differential output switching amplifier and method therefor | |
| EP1590905B1 (en) | Signal processing system with baseband noise modulation and noise fold back reduction | |
| KR101131758B1 (en) | Dynamic slew rate control based on a feedback signal | |
| Fujimori et al. | A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter | |
| JP2007532033A (en) | Signal processing apparatus and method | |
| JP2014112866A (en) | Combined digital-to-analog converter and signal filter | |
| JP2006518131A (en) | Signal processing system with timing baseband noise modulation chopper circuit for noise reduction | |
| JP3425344B2 (en) | D / A converter | |
| US10116473B1 (en) | Controlling noise transfer function of signal path to reduce charge pump noise | |
| US8299866B2 (en) | Method and device including signal processing for pulse width modulation | |
| US7589590B2 (en) | Circuit architecture having differential processing for use in half bridges and full bridges and methods therefore | |
| US20110241919A1 (en) | System and method for generating shaped noise | |
| JP4644289B2 (en) | System and method for adjusting dither in a delta-sigma modulator | |
| EP1776766A2 (en) | Consumer device comprising a signal converter | |
| KR102895678B1 (en) | Efficient digital gain implementation in digital microphones | |
| US11600280B2 (en) | Analog-to-digital converter and method | |
| WO2002078194A2 (en) | Method and apparatus for conditioning an analog signal | |
| US7663525B2 (en) | Digital to analog converter and conversion method | |
| US8362833B2 (en) | Amplifier circuitry, integrated circuit and communication unit | |
| CN119109462A (en) | Jitter injection circuit, analog-to-digital converter, chip and electronic device | |
| US7734265B2 (en) | Audio muting circuit and audio muting method | |
| Yu | Feedback dithering for decorrelating quantization noise and enhancing SNDR | |
| CN100477506C (en) | Class D Amplifier Circuit | |
| US20250219603A1 (en) | Amplifying circuit and amplifying device | |
| TWI868652B (en) | Audio processing apparatus and method having noise reducing mechanism |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20070222 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR |
|
| AX | Request for extension of the european patent |
Extension state: AL BA HR MK YU |
|
| R17P | Request for examination filed (corrected) |
Effective date: 20070222 |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: NXP B.V. |
|
| 17Q | First examination report despatched |
Effective date: 20080109 |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: DSP GROUP SWITZERLAND AG |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20080722 |