EP1640966A1 - Frame refresh method and circuit - Google Patents

Frame refresh method and circuit Download PDF

Info

Publication number
EP1640966A1
EP1640966A1 EP04022686A EP04022686A EP1640966A1 EP 1640966 A1 EP1640966 A1 EP 1640966A1 EP 04022686 A EP04022686 A EP 04022686A EP 04022686 A EP04022686 A EP 04022686A EP 1640966 A1 EP1640966 A1 EP 1640966A1
Authority
EP
European Patent Office
Prior art keywords
physical address
state
pixel data
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04022686A
Other languages
German (de)
French (fr)
Other versions
EP1640966B1 (en
Inventor
Ping-Yeh Chen
Yung-Che Pao
Szu-Han Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HTC Corp
Original Assignee
HTC Corp
High Tech Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HTC Corp, High Tech Computer Corp filed Critical HTC Corp
Priority to EP20040022686 priority Critical patent/EP1640966B1/en
Publication of EP1640966A1 publication Critical patent/EP1640966A1/en
Application granted granted Critical
Publication of EP1640966B1 publication Critical patent/EP1640966B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/021Power management, e.g. power saving

Definitions

  • the present invention relates to a frame refresh method and circuit, and more particularly to a frame refresh method for use in a handheld electronic device.
  • System pixel data is saved to a random access memory (RAM) providing pixel data updates when the power of the video chip is turned off. Pixel data is copied by the central processing unit (CPU) and sent to a video frame buffer for refreshing pixel data.
  • RAM random access memory
  • FIG 1 is a flowchart of a traditional frame refresh method for a handheld electronic device.
  • FIG 2 shows the internal circuit of the handheld electronic device 1, which comprises an operating system 10(OS), a central processing unit (CPU) 11, a RAM 12 and a video frame buffer 13.
  • the frame refresh method comprises, first, in step S1, the operating system (OS) writes pixel data to the CPU.
  • step S2 the CPU 11 writes the pixel data to the RAM 12.
  • operating system 10 sends a memory copy command to the CPU 11.
  • step S4 according to the received copy command, the CPU 11 copies the pixel data stored in the RAM 12.
  • step S5 the copied pixel data is stored in the video frame buffer 13 .
  • the disadvantage of conventional refreshing method is the frequent updating of pixel data of the display by the operating system.
  • the CPU must write the pixel data into RAM and copy the pixel data out of RAM to the video frame buffer for every refresh.
  • the copy procedure consumes excessive CPU resources and power and degrades deteriorate system performance.
  • An embodiment of the invention provides a frame refresh method applied to a handheld electronic device.
  • the operating system instructs a CPU to write a pixel data, and then check the power state of a video chip.
  • the CPU then writes the pixel data into a RAM or a video frame buffer according to the power state.
  • An embodiment of the invention additionally provides a handheld electronic device, comprising an operating system, a CPU, at least an address lookup tables, a RAM, and a video frame buffer.
  • the central processing unit is instructed by the operating system;.
  • the at least one address lookup table is searched by the central processing unit.
  • the random access memory is coupled to the central processing unit.
  • the video frame buffer is installed in a video chip and coupled to the central processing unit and RAM.
  • FIG 3 is a circuit block diagram of an embodiment of the invention.
  • a handheld electronic device such as a mobile phone, a personal digital assistance or a portable computer, comprises an operating system 10, a central process unit (CPU) 11, an address lookup table 20, a RAM 12, and a video frame buffer 13.
  • CPU central process unit
  • RAM random access memory
  • video frame buffer 13 a circuit block buffer
  • the CPU 11 is instructed by the operating system 10 to write a pixel data and a virtual address.
  • the address lookup table 20 installed in a memory 2 stores the virtual address and a corresponding physical address, and can be read by the CPU 11 according to a power state of a video chip for searching out the corresponding physical address.
  • the physical address may be a first physical address or a second physical address.
  • the first physical address is inside a RAM 12.
  • the second physical address is inside a video frame buffer 13.
  • the RAM 12 is coupled to the CPU 11 for receiving the pixel data during an off state and receiving pixel data copied from the video frame buffer 13 when the power state of the video chip is turned from an on state to the off state.
  • the video frame buffer 13 is coupled to the CPU 11 and the RAM 12 for receiving the pixel data during an on state and receiving pixel data copied from the RAM 12 when the power state of the video chip is turned from the off state to the on state.
  • FIG 4 illustrates a frame refresh method.
  • step S1 a pixel data and a virtual address are written into the CPU by the operating system.
  • step S2 the power state of the video chip is determined by the CPU. If the power state is in an off state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding first physical address in step S3, wherein the first physical address is inside the RAM.
  • step S4 the pixel data is written to the first physical address of the RAM by the CPU.
  • step S5 If the power state of the video chip is in an on state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding second physical address in step S5.
  • the second physical address is inside the video frame buffer.
  • step S6 the pixel data is written to the second physical address of the video frame buffer by the CPU.
  • FIG 5 is a flowchart when the power of the video chip is turned from an off state to an on state.
  • step 4.1 when the CPU detects that the power state of the video chip is turned from an off state to an on state.
  • the video chip is turned on and the interrupt functions are then turned off for avoiding other interruptions.
  • step 4.3 the content of the address lookup table is changed by the CPU in step 4.3.
  • the first physical address which corresponds to the virtual address is changed to the second physical address.
  • the pixel data stored in the RAM is copied by the CPU and written to the video frame buffer.
  • step 4.5 the interrupt functions are recovered by the CPU.
  • FIG 6 is a flowchart showing when the power state of the video chip turned from an on state to an off state.
  • step 6.1 when CPU detects that the power of the video chip is turned from an on state to an off state.
  • step 6.2 the interrupt functions are turned off by the CPU to prevent other interruptions.
  • step 6.3 the pixel data stored in the video frame buffer is copied and written to the RAM.
  • step 6.4 the content of the address lookup table is changed by the CPU. The second physical address corresponding to the virtual address is changed to the first physical address.
  • step 4.5 the video chip is turned off and the interrupt functions are recovered by the CPU.
  • the frame refresh method and circuit of an embodiment of the invention eliminates the need to coping pixel data each time. Additionally, the video chip is turned off when the power of the video chip is in an off state, thus saving more power. Further, the content of the address lookup table can be changed according to the power state. When the power state is in an off state, the pixel data is written to the RAM directly. When the power state is in an on state, the pixel data is written to the video frame buffer directly, thus increasing the frame refresh performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

A frame refresh method, which is adapted to a handheld electronic device, comprising the following steps:
  • a. an operating system instructing a central processing unit to write a pixel data;
  • b. the central processing unit determining a power state of a video chip; and
  • c. the central processing unit writing the pixel data into either a random access memory or a video frame buffer according to the power state.

Description

    BACKGROUND
  • The present invention relates to a frame refresh method and circuit, and more particularly to a frame refresh method for use in a handheld electronic device.
  • Currently, handheld electronic devices such as mobile phones use an external video chip to enhance video performance and reduce power consumption. System pixel data is saved to a random access memory (RAM) providing pixel data updates when the power of the video chip is turned off. Pixel data is copied by the central processing unit (CPU) and sent to a video frame buffer for refreshing pixel data.
  • FIG 1 is a flowchart of a traditional frame refresh method for a handheld electronic device. FIG 2 shows the internal circuit of the handheld electronic device 1, which comprises an operating system 10(OS), a central processing unit (CPU) 11, a RAM 12 and a video frame buffer 13. The frame refresh method comprises, first, in step S1, the operating system (OS) writes pixel data to the CPU. In step S2, the CPU 11 writes the pixel data to the RAM 12. In step S3, operating system 10 sends a memory copy command to the CPU 11. In step S4, according to the received copy command, the CPU 11 copies the pixel data stored in the RAM 12. Finally, in step S5, the copied pixel data is stored in the video frame buffer 13 .
  • The disadvantage of conventional refreshing method is the frequent updating of pixel data of the display by the operating system. The CPU must write the pixel data into RAM and copy the pixel data out of RAM to the video frame buffer for every refresh. The copy procedure consumes excessive CPU resources and power and degrades deteriorate system performance.
  • SUMMARY
  • An embodiment of the invention provides a frame refresh method applied to a handheld electronic device. First, the operating system instructs a CPU to write a pixel data, and then check the power state of a video chip. The CPU then writes the pixel data into a RAM or a video frame buffer according to the power state.
  • An embodiment of the invention additionally provides a handheld electronic device, comprising an operating system, a CPU, at least an address lookup tables, a RAM, and a video frame buffer. The central processing unit is instructed by the operating system;. The at least one address lookup table is searched by the central processing unit. The random access memory is coupled to the central processing unit. The video frame buffer is installed in a video chip and coupled to the central processing unit and RAM. When the operating system instructs the central processing unit to write a pixel data, the central processing unit checking a power state of a video chip, and the central processing unit write the pixel data into the RAM or a video frame buffer according to the power state.
  • A detailed description is given in the following with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the present invention can be more fully understood by reading the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:
    • Fig 1 is a flowchart showing a conventional frame refresh method of a handheld electronic device;
    • Fig 2 is a block circuit diagram of a handheld device;
    • Fig 3 is a schematic diagram of an embodiment of the invention;
    • Fig 4 is a flowchart showing a frame refresh method of an embodiment of the invention;
    • Fig 5 is a flowchart according to one embodiment of the invention;
    • Fig 6 is a flowchart in according to one embodiment of the invention;
    DETAILED DESCRIPTION
  • FIG 3 is a circuit block diagram of an embodiment of the invention. A handheld electronic device 1, such as a mobile phone, a personal digital assistance or a portable computer, comprises an operating system 10, a central process unit (CPU) 11, an address lookup table 20, a RAM 12, and a video frame buffer 13.
  • The CPU 11 is instructed by the operating system 10 to write a pixel data and a virtual address. The address lookup table 20 installed in a memory 2 stores the virtual address and a corresponding physical address, and can be read by the CPU 11 according to a power state of a video chip for searching out the corresponding physical address. The physical address may be a first physical address or a second physical address. The first physical address is inside a RAM 12. The second physical address is inside a video frame buffer 13. The RAM 12 is coupled to the CPU 11 for receiving the pixel data during an off state and receiving pixel data copied from the video frame buffer 13 when the power state of the video chip is turned from an on state to the off state. The video frame buffer 13 is coupled to the CPU 11 and the RAM 12 for receiving the pixel data during an on state and receiving pixel data copied from the RAM 12 when the power state of the video chip is turned from the off state to the on state.
  • FIG 4 illustrates a frame refresh method. First, in step S1, a pixel data and a virtual address are written into the CPU by the operating system. Next, in step S2, the power state of the video chip is determined by the CPU. If the power state is in an off state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding first physical address in step S3, wherein the first physical address is inside the RAM. In step S4, the pixel data is written to the first physical address of the RAM by the CPU.
  • If the power state of the video chip is in an on state, the address lookup table is searched by the CPU for transforming the virtual address to a corresponding second physical address in step S5. The second physical address is inside the video frame buffer. In step S6, the pixel data is written to the second physical address of the video frame buffer by the CPU.
  • FIG 5 is a flowchart when the power of the video chip is turned from an off state to an on state. In step 4.1, when the CPU detects that the power state of the video chip is turned from an off state to an on state. The video chip is turned on and the interrupt functions are then turned off for avoiding other interruptions. Next, the content of the address lookup table is changed by the CPU in step 4.3. The first physical address which corresponds to the virtual address is changed to the second physical address. In step 4.4, the pixel data stored in the RAM is copied by the CPU and written to the video frame buffer. Finally, in step 4.5, the interrupt functions are recovered by the CPU.
  • FIG 6 is a flowchart showing when the power state of the video chip turned from an on state to an off state. In step 6.1, when CPU detects that the power of the video chip is turned from an on state to an off state. In step 6.2, the interrupt functions are turned off by the CPU to prevent other interruptions. In step 6.3, the pixel data stored in the video frame buffer is copied and written to the RAM. In step 6.4, the content of the address lookup table is changed by the CPU. The second physical address corresponding to the virtual address is changed to the first physical address. Finally, in step 4.5, the video chip is turned off and the interrupt functions are recovered by the CPU.
  • The frame refresh method and circuit of an embodiment of the invention eliminates the need to coping pixel data each time. Additionally, the video chip is turned off when the power of the video chip is in an off state, thus saving more power. Further, the content of the address lookup table can be changed according to the power state. When the power state is in an off state, the pixel data is written to the RAM directly. When the power state is in an on state, the pixel data is written to the video frame buffer directly, thus increasing the frame refresh performance.
  • While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (13)

  1. A frame refresh method, which is adapted to a handheld electronic device, comprising the following steps:
    a. an operating system instructing a central processing unit to write a pixel data;
    b. the central processing unit determining a power state of a video chip; and
    c. the central processing unit writing the pixel data into either a random access memory or a video frame buffer according to the power state.
  2. The frame refresh method as claimed in claim 1, wherein the operating system provides a virtual address corresponding to the pixel data, the virtual address corresponds to a first physical address or a second physical address, the first physical address is inside the random access memory, and the second physical address is inside the video frame buffer.
  3. The frame refresh method as claimed in claim 2, when the power state is in an off state, the virtual address corresponds to the first physical address, and the central processing unit writes the pixel data to the random access memory.
  4. The frame refresh method as claimed in claim 2, when the power state is in an on state, the virtual address corresponds to the first physical address, and the central processing unit writes the pixel data to the video frame buffer.
  5. The frame refresh method as claimed in claim 3, when the power state of the video chip is turned from an off state to an on state, further comprising the following steps:
    changing the first physical address corresponding to the virtual address to a second physical address; and
    copying the pixel data in the random access memory to the video frame buffer.
  6. The frame refresh method as claimed in claim 4, when the power state of the video chip is turned from an on state to an off state, further comprising the following steps:
    copying pixel data of the video frame buffer to the random access memory; and
    changing the second physical address corresponding to the virtual address to a first physical address.
  7. A hand held electronic device, comprising:
    an operating system;
    a central processing unit, instructed by the operating system;
    at least one address lookup table, searched by the central processing unit;
    a random access memory, coupled to the central processing unit; and
    a video frame buffer, installed in a video chip and coupled to the central processing unit and random access memory;
    when the operating system instructs the central processing unit to write a pixel data, the central processing unit checking a power state of a video chip, and the central processing unit write the pixel data into the random access memory or a video frame buffer according to the power state.
  8. The handheld device as claimed in claim 7, wherein the operating system providing a virtual address corresponding to the pixel data, the virtual address corresponding to a first physical address or a second physical address, the first physical address is inside the random access memory, and the second physical address is inside the video frame buffer.
  9. The handheld device as claimed in claim 7, when the power state is in an off state, the content in the address look up table is the virtual address corresponding to the first physical address.
  10. The handheld device as claimed in claim 8, when the power state is in an on state, the content in the address look up table is the virtual address corresponding to the second physical address.
  11. The handheld device as claimed in claim 8, when the power state of the video chip is turned from an off state to an on state, the content in the address look up table changing the first physical address corresponding to the virtual address to a second physical address, and then copying pixel data of the random access memory to the video frame buffer.
  12. The handheld device as claimed in claim 8, when the power state of the video chip is turned from an on state to an off state, copying pixel data of the video frame buffer to the random access memory; and then changing the second physical address corresponding to the virtual address to a first physical address.
  13. The handheld device as claimed in claim 7, wherein the handheld device is a cell phone, a personal digital assistance or a portable computer.
EP20040022686 2004-09-23 2004-09-23 Frame refresh method and circuit Expired - Lifetime EP1640966B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP20040022686 EP1640966B1 (en) 2004-09-23 2004-09-23 Frame refresh method and circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20040022686 EP1640966B1 (en) 2004-09-23 2004-09-23 Frame refresh method and circuit

Publications (2)

Publication Number Publication Date
EP1640966A1 true EP1640966A1 (en) 2006-03-29
EP1640966B1 EP1640966B1 (en) 2012-09-19

Family

ID=34926681

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20040022686 Expired - Lifetime EP1640966B1 (en) 2004-09-23 2004-09-23 Frame refresh method and circuit

Country Status (1)

Country Link
EP (1) EP1640966B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151025A (en) * 2011-12-07 2013-06-12 谱瑞科技股份有限公司 Frame buffer management and self-refresh control in a self-refresh display system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0584358A1 (en) * 1992-02-25 1994-03-02 Citizen Watch Co. Ltd. Liquid crystal display device
US5961617A (en) * 1997-08-18 1999-10-05 Vadem System and technique for reducing power consumed by a data transfer operations during periods of update inactivity
WO2001039164A1 (en) * 1999-11-24 2001-05-31 Koninklijke Philips Electronics N.V. Data processing unit with access to the memory of another data processing unit during standby
EP1262939A1 (en) * 2001-05-31 2002-12-04 Nokia Corporation Method and apparatus for updating a frame buffer with reduced power consumption

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0584358A1 (en) * 1992-02-25 1994-03-02 Citizen Watch Co. Ltd. Liquid crystal display device
US5961617A (en) * 1997-08-18 1999-10-05 Vadem System and technique for reducing power consumed by a data transfer operations during periods of update inactivity
WO2001039164A1 (en) * 1999-11-24 2001-05-31 Koninklijke Philips Electronics N.V. Data processing unit with access to the memory of another data processing unit during standby
EP1262939A1 (en) * 2001-05-31 2002-12-04 Nokia Corporation Method and apparatus for updating a frame buffer with reduced power consumption

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151025A (en) * 2011-12-07 2013-06-12 谱瑞科技股份有限公司 Frame buffer management and self-refresh control in a self-refresh display system
US9196216B2 (en) 2011-12-07 2015-11-24 Parade Technologies, Ltd. Frame buffer management and self-refresh control in a self-refresh display system
CN103151025B (en) * 2011-12-07 2016-01-13 谱瑞科技股份有限公司 Frame buffer management in self-refresh display system and self-refresh control

Also Published As

Publication number Publication date
EP1640966B1 (en) 2012-09-19

Similar Documents

Publication Publication Date Title
US7755633B2 (en) Loading an internal frame buffer from an external frame buffer
US20040233204A1 (en) Method and apparatus for pattern ram sharing color look up table
US20090219295A1 (en) Display System and Method for Reducing Power Consumption of Same
TW201435571A (en) Data processing device, display control device, semiconductor chip, method of controlling display device, and computer-readable medium
US20220417391A1 (en) Devices and methods for selective display frame fetch
KR100678047B1 (en) Mobile communication terminal with NAND flash memory and booting method thereof
US20090100242A1 (en) Data Processing Method for Use in Embedded System
JP2005018229A (en) Document browsing terminal, document display control method, and document display control program
CN102023941B (en) Laptop
US8823722B1 (en) SOC with integrated bistable display controller
EP1640966A1 (en) Frame refresh method and circuit
CN1504859A (en) Handheld device with sleep function and operation method thereof
US20050237315A1 (en) Frame refresh method and circuit
US6393498B1 (en) System for reducing processor workloads with memory remapping techniques
JP5464801B2 (en) Electronics
US20130207986A1 (en) Method and device for accessing buffer of display
CN116504167A (en) Page refreshing method, device, display device, storage medium and program product
US9164884B2 (en) Display controller and display device including the same
JP2003150283A (en) Power control device and power control method
US7093117B2 (en) Method for automatically getting control data from BIOS
US20040024970A1 (en) Methods and apparatuses for managing memory
US20250060983A1 (en) Method of Dynamic Channel Switch by Hypervisor
US20250173221A1 (en) Selective backup to persistent memory for volatile memory
US20240103602A1 (en) Power consumption control device applied to electronic device and associated method
US8692837B1 (en) Screen compression for mobile applications

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050722

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20090626

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HTC CORPORATION

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CHEN, PING-YEH

Inventor name: WU, SZU-HAN

Inventor name: PAO, YUNG-CHE

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 576354

Country of ref document: AT

Kind code of ref document: T

Effective date: 20121015

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602004039345

Country of ref document: DE

Effective date: 20121115

REG Reference to a national code

Ref country code: NL

Ref legal event code: T3

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 576354

Country of ref document: AT

Kind code of ref document: T

Effective date: 20120919

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20121220

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20121230

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120930

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130121

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20121219

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120923

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120930

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120930

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

26N No opposition filed

Effective date: 20130620

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602004039345

Country of ref document: DE

Effective date: 20130620

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120919

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120923

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20040923

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20180813

Year of fee payment: 15

Ref country code: DE

Payment date: 20180911

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20180919

Year of fee payment: 15

Ref country code: NL

Payment date: 20180912

Year of fee payment: 15

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602004039345

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: MM

Effective date: 20191001

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191001

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200401

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20190923

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190923

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190930