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EP1612940A3 - Application-specific integrated circuit equivalents of programmable logic and associated methods - Google Patents

Application-specific integrated circuit equivalents of programmable logic and associated methods

Info

Publication number
EP1612940A3
EP1612940A3 EP20050253922 EP05253922A EP1612940A3 EP 1612940 A3 EP1612940 A3 EP 1612940A3 EP 20050253922 EP20050253922 EP 20050253922 EP 05253922 A EP05253922 A EP 05253922A EP 1612940 A3 EP1612940 A3 EP 1612940A3
Authority
EP
Grant status
Application
Patent type
Prior art keywords
logic
le
hles
asic
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20050253922
Other languages
German (de)
French (fr)
Other versions
EP1612940A2 (en )
Inventor
Kar Keng c/o Blk P-2-04 Chua
Sammy Cheung
Hee Kong Phoon
Kim Pin Tan
Wei Lian Goay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1737Controllable logic circuits using multiplexers

Abstract

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ("HLEs"), each of which can provide a portion of the full functionality of an FPGA logic element ("LE"). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
EP20050253922 2004-07-02 2005-06-24 Application-specific integrated circuit equivalents of programmable logic and associated methods Withdrawn EP1612940A3 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10884460 US7243329B2 (en) 2004-07-02 2004-07-02 Application-specific integrated circuit equivalents of programmable logic and associated methods

Publications (2)

Publication Number Publication Date
EP1612940A2 true EP1612940A2 (en) 2006-01-04
EP1612940A3 true true EP1612940A3 (en) 2007-08-22

Family

ID=34993053

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20050253922 Withdrawn EP1612940A3 (en) 2004-07-02 2005-06-24 Application-specific integrated circuit equivalents of programmable logic and associated methods

Country Status (4)

Country Link
US (5) US7243329B2 (en)
EP (1) EP1612940A3 (en)
JP (5) JP5036146B2 (en)
CN (1) CN1716781A (en)

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US7373631B1 (en) * 2004-08-11 2008-05-13 Altera Corporation Methods of producing application-specific integrated circuit equivalents of programmable logic
US7392498B1 (en) * 2004-11-19 2008-06-24 Xilinx, Inc Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device
US7441223B1 (en) * 2005-01-07 2008-10-21 Altera Corporation Method and apparatus for performing synthesis to improve density on field programmable gate arrays
US7620924B2 (en) * 2005-03-14 2009-11-17 Lsi Corporation Base platforms with combined ASIC and FPGA features and process of using the same
US7275232B2 (en) * 2005-04-01 2007-09-25 Altera Corporation Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits
US7304497B2 (en) * 2005-04-29 2007-12-04 Altera Corporation Methods and apparatus for programmably powering down structured application-specific integrated circuits
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US7386819B1 (en) * 2005-07-28 2008-06-10 Altera Corporation Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
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US8037444B1 (en) 2006-07-20 2011-10-11 Altera Corporation Programmable control of mask-programmable integrated circuit devices
US7587686B1 (en) 2006-08-01 2009-09-08 Altera Corporation Clock gating in a structured ASIC
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US7451420B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining reachable pins of a network of a programmable logic device
US7451425B1 (en) 2006-08-11 2008-11-11 Xilinx, Inc. Determining controlling pins for a tile module of a programmable logic device
US7478359B1 (en) 2006-10-02 2009-01-13 Xilinx, Inc. Formation of columnar application specific circuitry using a columnar programmable logic device
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US7724031B2 (en) * 2007-03-21 2010-05-25 Altera Corporation Staggered logic array block architecture
US7924052B1 (en) 2008-01-30 2011-04-12 Actel Corporation Field programmable gate array architecture having Clos network-based input interconnect
US7586327B1 (en) 2008-03-25 2009-09-08 Altera Corporation Distributed memory circuitry on structured application-specific integrated circuit devices
US7622952B1 (en) 2008-05-28 2009-11-24 Altera Corporation Periphery clock signal distribution circuitry for structured ASIC devices
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US8105885B1 (en) * 2010-08-06 2012-01-31 Altera Corporation Hardened programmable devices
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US20180062654A9 (en) * 2011-11-30 2018-03-01 Agate Logic Inc. Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment
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US9418231B2 (en) * 2014-06-03 2016-08-16 Empire Technology Development Llc Perturbation of field programmable gate array code to prevent side channel attack

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Also Published As

Publication number Publication date Type
US8863061B2 (en) 2014-10-14 grant
JP2012235499A (en) 2012-11-29 application
US20110084727A1 (en) 2011-04-14 application
US7243329B2 (en) 2007-07-10 grant
US8291355B2 (en) 2012-10-16 grant
JP2006020329A (en) 2006-01-19 application
EP1612940A2 (en) 2006-01-04 application
US7870513B2 (en) 2011-01-11 grant
US8504963B2 (en) 2013-08-06 grant
US20130002295A1 (en) 2013-01-03 application
JP2015008539A (en) 2015-01-15 application
JP5475045B2 (en) 2014-04-16 grant
US20060001444A1 (en) 2006-01-05 application
JP5036146B2 (en) 2012-09-26 grant
US20130314122A1 (en) 2013-11-28 application
JP2014131365A (en) 2014-07-10 application
JP5859089B2 (en) 2016-02-10 grant
JP5623471B2 (en) 2014-11-12 grant
US20070210827A1 (en) 2007-09-13 application
JP2012157054A (en) 2012-08-16 application
CN1716781A (en) 2006-01-04 application

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