EP1535336A2 - High-density nrom-finfet - Google Patents

High-density nrom-finfet

Info

Publication number
EP1535336A2
EP1535336A2 EP20030793747 EP03793747A EP1535336A2 EP 1535336 A2 EP1535336 A2 EP 1535336A2 EP 20030793747 EP20030793747 EP 20030793747 EP 03793747 A EP03793747 A EP 03793747A EP 1535336 A2 EP1535336 A2 EP 1535336A2
Authority
EP
European Patent Office
Prior art keywords
layer
rib
fin
semiconductor memory
memory according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20030793747
Other languages
German (de)
French (fr)
Inventor
Franz Hofmann
Erhard Landgraf
Richard Johannes Luyken
Wolfgang RÖSNER
Michael Specht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE10241170 priority Critical
Priority to DE2002141170 priority patent/DE10241170A1/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to PCT/EP2003/009297 priority patent/WO2004023519A2/en
Publication of EP1535336A2 publication Critical patent/EP1535336A2/en
Application status is Withdrawn legal-status Critical

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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
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    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
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    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell
    • Y10S257/904FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905Plural dram cells share common contact or common trench

Abstract

The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1).

Description

High density NROM FinFET

description

The invention relates to a semiconductor memory according to claim 1 and a method for manufacturing a semiconductor memory according to claim 19th

Conventional non-volatile semiconductor memory elements exist depending on the application in a variety of different embodiments, including PROM, EPROM, EEPROM, FLASH EEPROM, SONOS, etc. These different embodiments differ in particular in the delete option, programmability and programming time, hold time, storage density as well as its manufacturing cost. A special need exists for high-density and low-cost flash semiconductor memories. Known designs are in particular so-called NAND and ETOX memory cells whose storage density, however, requires more than 4F 2 where F is the smallest occurring in the process dimension structure of the semiconductor memory. In the publication by B. Eitan et al. "NROM: A Novel Localized Trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Letters vol.21, n.ll, November 2000, describes a so-called NROM memory, which by means of a 2-bit cell is a memory cell having allows a 2F 2 square measure.

However, all the nonvolatile memory elements mentioned above require relatively high voltages of at least 10 V for programming or erase the data stored in a storage layer bits. For example, an NROM memory cell is dependent on the gate voltages in the range of 9 V. As in the typical application areas of flash memory elements external voltage of 10 V or more are available, such voltages must be generated "on-chip". Although necessary for this charge pumps (charge pumps) are generally known, but they require a considerable space requirement on the memory chip, whereby its degree of integration is curtailed and consequently increases the manufacturing costs adversely.

Object of the invention is accordingly to provide a semiconductor memory having a plurality of memory cells, which in particular smaller programming voltages required, and a high-density memory cell array allows. It is further object of the invention to provide a manufacturing method for such a semiconductor memory.

This object is achieved by a semiconductor memory having a plurality of memory cells according to claim 1 and by a method for manufacturing a semiconductor memory according to claim 19th Preferred embodiments are subject of the dependent claims.

According to the invention, a semiconductor memory includes a plurality of memory cells, each memory cell comprises: - a first conductively doped contact region, a second conductively doped contact region and an interposed channel region, which is formed in a web-like fin of semiconductor material and disposed in this order in the longitudinal direction of the rib after the other are, the rib in a direction perpendicular to the longitudinal direction of the rib section having a substantially rectangular shape with a rib top and opposed side surfaces of the ribs at least in the channel region; , A designed for programming the memory cell storage layer spaced apart by a first insulator layer is disposed on the rib top wherein the storage layer extends beyond at least one of the rib side surfaces in the normal direction of a rib side surface, so that a rib side surface and the rib top injection edge to the injection of charge carriers of forming the channel region in the storage layer; and - at least a gate electrode, which second by a

Insulator layer is a rib side surface and spaced by a third insulator layer from the storage layer, wherein the gate electrode over the channel region electrically isolated and is designed to control its electrical conductivity.

In the semiconductor memory is a nonvolatile semiconductor memory which electrically lδschbar is (EEPROM), in particular a FLASH semiconductor memory. The storage of binary information, that is, a "bit", in a known manner by means of a designed for programming the memory cell storage layer. This storage layer is designed for trapping and emitting charge carriers from and into the channel region of the transistor, which extends in the longitudinal direction of the rib between two doped contact regions (source and drain region of the transistor). The Tansistorlayout is thus similar to that of a so-called FinFET. The storage layer is opposite the doped contact regions and the gate electrode of the transistor is electrically insulated.

In the storage layer trapped electrons cause via the field effect in a known manner a displacement of the characteristic of the transistor, in particular of its threshold voltage (threshold voltage). Thus, at a predetermined gate voltage, and a predetermined source-drain voltage can be detected via the electrical conductivity of the transistor channel if carriers are trapped in the storage layer or not.

The storage layer to "program", for example, to store a logic "1", electrons must be injected from the channel region of the FinFET in the storage layer, for example. Conventionally, (Fowler-Nordheim tunneling) through hot electrons (channel hot electrons, CHE) or a field-assisted tunneling process () high voltage differences between the contact regions and the gate electrodes are needed for such injection process independently of the underlying physical injection mechanism.

The invention solves this problem by providing a special channel, insulator and gate geometry is used, which leads to the formation of an injection edge to the injection of charge carriers from the channel region into the storage layer. The injection edge is designed so that it comes into their immediate environment to a local field enhancement, so that effectively at a comparatively small electric potential differences between the channel region and the gate electrode into the charge carrier

Storage layer can be injected. Here, the injection process can be done by hot electrons (CHE) or field-supported tunneling (Fowler-Nordheim tunneling). The edge effect leads to a significant reduction in the necessary programming voltage of invention

Semiconductor memory compared to conventional non-volatile memory elements.

The channel region of the semiconductor memory is in a web-like fin of semiconductor material, in particular silicon, are formed. In the longitudinal direction of the rib are preferably evenly spaced conductively doped contact regions which later constitute the source and drain contacts of the transistors. Each contact area is a source contact and a drain contact of a transistor of an adjacent transistor. The rib has a substantially rechtecksformige shape in a sectional plane which is perpendicular to the fin longitudinal axis. In parallel with the semiconductor substrate, in which the rib is formed, the rib top runs, while the opposing rib side surfaces are arranged perpendicular to the substrate plane. In each channel portion of the rib is on the rib top, a first insulator layer, for example an oxide layer arranged. The

Memory layer is deposited on the first insulator layer. The storage layer protrudes beyond at least one of the rib side faces in a direction which is parallel to the normal direction of these ribs side surface.

The injection edge to the injection of charge carriers from the channel region into the storage layer is formed by the edge which is defined by these rib side surface and the rib top. The rib side surface is spaced from the gate electrode over which the conductivity of the channel region can be controlled by the field effect, through a second insulator layer. The gate electrode extends in the normal direction of the semiconductor substrate over the rib top addition of preferably up to the top of the storage layer. The gate electrode is spaced apart in this area through the third insulator layer from the storage layer.

An electrical potential difference between the channel region and the gate electrode results in such a geometry to a local field enhancement in the region of the injection edge, so that with relatively small potential differences charge carriers leave the channel region at the injection edge and can be trapped by the storage layer.

Preferably, the storage layer extends in a direction which is parallel to the normal directions of the rib side surfaces on both side surfaces of the rib ridge addition. In this transverse direction to the rib, the rib width is thus preferably smaller than the width of the storage layer. If - as described above - a gate electrode is arranged on the rib side, then, the edge portion between the rib top and the second-rib-side surface in the channel region, a second

Injection edge for charge carriers in the storage layer is.

Preferably, the second insulator layer has a greater layer thickness than the third insulator layer. For example, the third insulator layer a

Layer thickness of 3 nm to 6 nm, typically 5 nm, while the second insulator layer is thicker by about 2 nm to 5 nm. The first insulator layer typically has a layer thickness of 2 to 5 nm when it is formed of silicon dioxide.

Preferably, the second insulator layer on a disposed on at least one rib side surface internal oxide layer and, disposed on the inner oxide layer outer oxide layer.

Preferably, the third insulator layer is formed by the outer oxide layer. The outer oxide layer extends beyond in the normal direction of the semiconductor substrate over the inner oxide layer and separates the gate electrode by the storage layer. Preferably, the outwardly facing surface of the outer oxide layer forms a substantially planar surface, in particular in the area of ​​the rib top.

Preferably, the inner oxide layer is a thermal oxide, and the outer oxide layer, a HT-oxide (high temperature oxide, HTO). When the inner oxide layer is formed by oxidation of the semiconductor material of the rib, there is a particularly advantageous injection edge geometry. The oxidation process of the semiconductor material of the rib with already applied first insulator layer and storage layer is namely that the injection edge forms an internal angle in a direction perpendicular to the rib longitudinal axis sectional area which is smaller than 90 °. This injection edge geometry is due to the oxidation rate variation of the semiconductor material of the rib in the region of the first insulator layer. Such a tapered injection edge is particularly suitable to cause a local field increase, through which erSpannungen the program! Possibility of further reducing the storage layer.

Preferably, the first insulator layer of a thermal oxide is formed. The layer thickness of the thermal oxide is, for example 2 to 5 nm.

Preferably, the rib is arranged in a top silicon layer of an SOI substrate (silicon-on insulator). The rib top opposite surface of the rib adjacent to the "buried oxide", of the SOI substrate (burried oxide BOX). The top silicon layer (also called body-silicon layer) of the SOI substrate typically has a layer thickness of 20 nm to 50 nm. The width, which is also referred to as a fin structured in this top silicon layer rib is, for example between 40 and 100 nm. Alternatively, the rib may also be isolated by a highly doped well below the rib with respect to adjacent ribs. If the semiconductor material of the rib, for example, weakly p-doped, a highly doped p + can - tray for electrical insulation of the ribs to each other are used.

Preferably a plurality of equally spaced ribs are provided, extending mutually parallel their longitudinal axes, and in each of the ribs a plurality of memory cells is formed. The distances between the parallel extending ribs are restricted by the gate electrode to be patterned, as well as the available processing techniques.

Preferably, the storage layer is a so-called trapping layer (trapping layer) or a floating gate. In the trapping layer is an electrically non-conductive layer having a large number of so-called "trapping states", which charge carriers can be trapped. The floating gate, however, is electrically conductive.

Preferably, the trapping layer is a nitride layer, a silicon-rich oxide layer (Silicon Rich Oxide) or an undoped poly-silicon layer of the

Channel region and the gate electrode are separated by oxide layers. If the trapping layer is a through oxide, in particular silicon dioxide, silicon nitride coated, it is at the SpeieherSchichtanordnung a so-called ONO stack). Programming of such a trapping layer is preferably via channel hot electrons (channel hot electrons; CHE), which accelerated by a strong forward voltage and a positive gate voltage and will be pulled into the storage layer. Deleting the trapping layer is preferably carried out by injection of "hot holes" in the trapping layer (so-called "band-to-band tunneling enhanced hot hole injection") analogous to the erasing process at the above-mentioned NROM memory cells.

By the peak effect of the injection edge gate voltages in the range of 5 are to produce up to 7 V field strengths sufficient to bring electrons (or holes of a p-channel transistor) to the trapping layer. For deleting the trapping layer voltages of about 5 V are also sufficient.

Preferably two electrically mutually insulated gate electrodes are at least one rib provided for, wherein the gate electrodes extend in the direction of the ribs longitudinal axis and are spaced apart by second insulator layers from the opposing rib side surfaces. In this case each rib are two injection edge is preferably provided for each channel region represented by the edge between the opposite

Rib side surfaces and the rib top are formed. The gate electrodes extending along the flanks of the rib structure parallel to the fin longitudinal axis. They form the word lines of the semiconductor memory.

In such an arrangement, a maximum of 4 bits can be stored in each trapping layer above each channel region. Thus 2 bits in the storage layer adjacent the first contact area can be stored in each case close to the opposite edges injection.

Further 2 bits can be stored in the storage layer close to the second contact region in regions near the opposite edges injection. This arrangement thus permits formation of a 2-bit memory cell having a square measure 2 2F, where F is the smallest Strukturgrδße of the semiconductor memory. To read out the bits proposed by B. Eitan in the aforementioned publication is preferably used Leseverf lead, as is known in NROM Speieherelementen. In this respect to the disclosure of the aforementioned publica entlichung by B. Eitan et al. and reference is made to the international patent application WO 99/07000 (PCT / IL 98/00363) in its entirety, which are an integral part of the disclosure of the present application with respect to the described therein, reading, programming and erasing method.

Preferably, the gate electrode of highly doped polysilicon are formed. Such a gate electrode may be preferably made self-aligning manner by a so-called Spacerätzverfahren. Between the gate electrodes of adjacent ribs nitride is preferably provided to insulation. The doping of the two gate electrodes of each rib may be different to different characteristic curves for the left and right

to cause sidewall transistor.

Preferably, the ribs are provided for each two mutually insulated gate electrodes and word lines of the semiconductor memory having a plurality of equally spaced ribs are provided.

Preferably, the semiconductor memory includes a plurality of word lines perpendicular to the running bit lines, each of said bit lines to one of the contact portions of each rib is electrically connected. Word and bit lines result in a column and row-wise arrangement of a memory cell array, wherein each source and drain contact of the ribs transistors is selectively controlled so that a so-called "virtual ground array (VGA)" is formed.

Alternatively to a formed as a trapping layer storage layer, the storage layer can also be a floating gate made of metal or highly doped poly-silicon.

According to a preferred embodiment of the semiconductor memory comprises a plurality of gate electrodes, wherein each of the channel areas is that passes as the word line of the semiconductor memory perpendicular to the longitudinal axis of the rib a plurality of ribs in one of the ribs exactly one of the gate electrodes assigned. In contrast to the previously described embodiment extend in the present embodiment, the gate electrodes, ie the word lines perpendicular to the ribs. "Bit lines" in the strict sense are not present in this NAND arrangement, but are formed by a series circuit of the transistors ribs along each rib. The programming of the storage layers of such memory cells via field-supported tunneling, which is known as Fowler-Nordheim tunneling. Also in this case, the local field enhancement leads along the injection edge to a significant reduction of the required programming voltages.

Preferably, the floating gate on at least a deletion edge for injecting charge carriers from the floating gate to the (control) gate electrode through the third insulator layer. The erasure edge is preferably located in close proximity to the injection edge. The erasure edge of the floating gate is preferably adjacent to an edge portion, which is formed by the first insulator layer and the third insulator layer. In other words, the erasure edge is formed by that storage layer material which is adjacent to the edge which is defined by the first insulator layer and the third insulator layer. By a suitable forward voltage of the channel region opposite to the gate electrode of a field-assisted tunneling of electrons can be triggered by the deletion edge in the channel region and gate electrode portion starting.

The storage density of such a NAND arrangement is smaller than with the above described "Virtual ground array (VGA)" and is approximately 4 to 5 f 2. Compared to conventional NAND memories is, however, a noticeable reduction in the necessary programming and erase voltages expected. Thus, the time necessary for charge pump area decreases, whereby the degree of integration increased and thus the manufacturing cost can be reduced. is further enhanced

Readout rate achievable, since the read current of each memory cell is amplified by the side wall transistors over conventional planar devices.

According to the invention, a method for manufacturing a semiconductor memory according to the invention the following

Steps :

Providing an SOI substrate having a top silicon layer; - application of the first insulator layer on the top silicon layer;

Applying the recording layer on the first insulator layer; Patterning the top silicon layer, the first insulator layer and the memory layer in at least one web-like rib shape, the first insulator layer is disposed on the rib top the group consisting of silicon rib and the storage layer on the first insulator layer; Oxidizing the rib side faces of the rib to form an inner oxide layer of the second insulator layer; Applying the third insulator layer; Applying the at least one gate electrode; and - local doping of the rib to form doped contact regions.

According to the inventive method, the top silicon layer is initially structured with disposed thereon first insulator layer and the storage layer in a web-like rib shape. Transversely to the rib from

Semiconductor material, the first insulator layer and the storage layer in this process stage in the same width. Subsequently, an oxidation step of the rib side faces of the rib to form an inner oxide layer is carried out, showing a part of the second insulator layer. Due to the different edges in the region close to the first insulator layer oxidation rates an acute injection edge in the rib in the edge area of ​​the rib top is connected to each

Rib side surfaces produced, which is advantageous for efficient charge carrier injection. Thereafter, the third insulator layer is defined.

Preferably, the applying the third comprises

Insulator layer comprises applying an outer oxide layer which is arranged on the storage layer and the inner oxide layer. The third insulating layer that separates the gate electrode of the memory layer, for example, a CVD-deposited

High temperature oxide (HTO) exist, which is deposited on the outer surface surrounding the inner oxide layer and the exposed surfaces of the storage layer. The invention based accompanying drawings of preferred embodiments will be described by way of example. It shows:

Figure 1 is a simplified schematic plan view of a memory cell array of a preferred embodiment of the semiconductor memory according to the invention in a "virtual ground array" arrangement. Figure 2 is a schematic cross-sectional view taken along line AA of Fig. 1. Figure 3 is a schematic cross-sectional view taken along line BB in Fig 1, Fig 4 is a schematic plan view of a cell array to another preferred embodiment of a semiconductor memory according to the invention in a "NAND" arrangement...; Figure 5 is a schematic cross-sectional view taken along line AA of Fig. 4. Figs. 6-9 are schematic cross sectional views of

Intermediates of the preferred semiconductor memory shown in Figure 1 along the line AA. and Figs. 10-14 are schematic cross sectional views of intermediate products of the in Fig. 1 shown

Semiconductor memory taken along the line CC.

In Fig. 1 is a highly schematic plan view is shown on a memory cell array of a preferred embodiment of a semiconductor memory according to the invention. With WLl, WL2, WL3, and WL4 word lines are referred to, which extends along edges of two web-like ribs (fins) extending from silicon. The first web-like rib extends between the word line WLl and the word line WL2 in by the arrow (FIN) designated direction and is provided with the reference numeral FIN 1. The second rib extending between the word line WL3 and the word line WL4 and bears the reference numeral FIN2. It should be understood that FIG. 1 illustrates only a small part of a large memory cell array in which a plurality of mutually parallel ribs are provided uniformly spaced apart FIN.

In the ribs FIN are spaced by a distance F from each other, highly doped contact regions S / D provided, which are highlighted in FIG. 1 by a dot pattern. Each two adjacent contact regions S / D of each rib FIN form the source and drain of a FINFETs whose channel region is disposed in the rib FIN between these contact regions S / D. The contact regions S / D are contacted via bit lines BL which are substantially perpendicular to the word lines WL. Through each bit line WL, a contact area S / D is contacted per rib FIN. The bit lines BL are shown in Fig. 1 by dashed lines.

In Fig. 2 is a schematic cross-sectional view taken along line AA of Fig. 1 is shown. The ribs FIN 1, FIN2 have a substantially rectangular shape in this plane perpendicular to its longitudinal section plane. The ribs FIN are formed in a top silicon layer (body- silicon layer) of an SOI substrate, the buried oxide layer is denoted by BOX. Below the buried oxide layer BOX typically is a silicon wafer, which is not shown in more detail in Fig. 2. The ribs have a FIN buried oxide layer BOX facing away from rib top 10 and two opposed rib side surfaces 12, 14th The rib top 10 extends substantially parallel to the SOI substrate plane, that is parallel to the buried oxide layer BOX. The rib side surfaces 12, 14 are substantially perpendicular to the substrate plane. The rib side surfaces 12, 14 are preferably 40 - 200 nm, particularly preferably 40 - 60 nm apart from each other.

In the example shown in FIG. 2, inset region between the edges of the rib side surface 12 and the rib top 10 of the ridge FIN 1 is shown enlarged. The rib side surface 12 forms at its point of contact with the rib top 10 of an injection edge 16, whose effects are described in detail below. The rib top 10 of the ribs FIN is separated from a storage layer 18 through a first insulator layer twentieth In the illustrated in Fig. 2 embodiment 20, the first insulator layer of a silicon dioxide layer, preferably made of a thermal silicon dioxide layer. The storage layer 18 is designed as a so-called trapping layer having a large number of "trap" states for trapping charge carriers. For example, the storage layer 18 of silicon nitride.

In the example shown in FIG. 2, cross-section 18, the storage layer comprises a substantially rectangular cross-section, wherein the width of the storage layer 18 is greater than the width of the ribs FIN (distance between rib side surfaces 12 and 14). The channel region of the ribs FIN, which is shown in Fig. 2, through second insulator layers 22, 24 of the adjacent word lines WLl and WL2 and WL3, and WL4 are separated. The word lines WL form the gate electrodes of the

"Sidewall transistors" with FinFET similar structure. The first insulator layer 22 is preferably composed of an inner oxide layer 26 and an outer oxide layer 28. In an identical manner, the second insulator layer 24, which separates the rib side surface 14 of the word line WL2 and WL4, also made of an inner and an outer oxide layer. When the ribs FIN are formed of silicon, silicon dioxide is preferably used for the oxide layers are used. The inner oxide layer 26 and the outer oxide layer 28 preferably each have a layer thickness of about 2 - 5 nm.

The outer oxide layer 28 preferably extends from the buried oxide layer BOX along the outer surface of the inner oxide layer 26 and along the side surfaces of the storage layer 18. Thus, the storage layer 18 extends in a direction parallel to the normal direction of

Rib side surfaces 12, 14 to the thickness of the inner oxide layer 26 also. The word lines WL (gate electrodes) are adjacent the outer surfaces of the outer oxide layers 28th The portion of the outer oxide layer 28 which is angeorndet between a WL and the associated storage layer 18 is referred to as the third insulator layer 29th

Preferably, the word lines of heavily doped

formed of polysilicon, and it is possible to dope the a rib FIN allocated to two word lines WL different. For example, the "left" word line WLl the rib FIN 1 n + -doped while the "right" word line WL2 is p + -doped. This results in different threshold voltages (threshold voltages) can achieve the sidewall transistors. All other surfaces of the storage layer 18 also by insulator layers, preferably oxide, is limited so that the storage layer 18 is completely electrically isolated from its surroundings.

To "program" a "bit" in the storage layer 18 to an injection channel hot electron process is used for example. For this purpose, a strong forward voltage built up in the transistor channel, in the S / D (source contact) to 0 V and an adjacent, second contact region S / D (drain contact) placed, for example, a first contact portion depending on the channel length of 2 to 5 V becomes. In addition, for example, the word line WLl, which is associated with this rib FIN 1, to a potential of 5 - 7 V set. If it is the transistor is an n-channel transistor, generated channel hot electrons near the drain contact at these potential conditions in a known manner. Through the injection edge 16 occurs due to the edge effect to a local field enhancement between the channel region (ie, the rib FIN 1) and the word line WLl (gate electrode), the path with the greatest field strength of the injection edge 16 through the storage layer 18 extends to the gate electrode. Thus, the hot electrons near the second contact region (drain region) are injected from the injection edge 16 in a portion of the storage layer 18, which is close to the injection edge sixteenth In one designed as a trapping layer memory layer 18 to be so in the

Memory layer 18 introduced electrons "trapped" and held in the storage layer eighteenth

Such as in NROMs known, the trapped in the storage layer 18 charge carriers lead to a shift in the threshold voltage of the transistor associated side wall, which can be detected during read-out of the cell. Here, preferably, the reading method is used, which by B. Eitan et al. in "NROM: A Novel Localized Trapping, 2-bit nonvolatile memory cell" in IEEE Electron Device Letters vol. 21, n. 11, November 2000 and is described in WO 99/97000. With regard to the programming, erasing and reading process is made to the above publications in their entirety by reference, so that the disclosure of which is an integral part of the overall disclosure of the present application.

In Figs. 1 and 2 illustrated embodiment is particularly characterized in that the necessary

Program! ErSpannungen on the "Channel hot electron (CHE)" much lower than the known conventional EEPROM storing programming voltages, since a specifically constructed, local field enhancement between the injection edge 16 and the word lines WL for injection of charge carriers from the drain near the channel region takes place in the storage layer eighteenth Thus, less surface area for increased programming voltages must be provided on the memory chip, whereby a higher integration density of the memory and thus lower manufacturing costs are possible.

The ribs FIN are dimensioned with respect to their width such that a stored, for example, close to the word line WLl bit in the storage layer 18, only an influence on the conductivity of the channel

has side wall transistor on the rib side surface 12, but does not lead to a significant characteristic curve or threshold displacement of the side wall transistor, which is formed on the rib side surface fourteenth The "crosstalk" to the influence of the "left" and "right" bits in the storage layer 18 defines the minimum width of the ribs FIN.

To delete the inserted in the programming step in the storage layer 18 charge carriers (electrons or holes) (drain contact) 0 V, the first contact region (source contact) 5 V and is applied to the gate electrode of -5 V, for example, at the second contact area. Through these potential conditions of the n-channel transistor sidewall is driven into strong accumulation, leading to so-called "band to band tunneling enhanced hot hole injection". Injected from the injection edge 16 in the storage layer 18 hot holes neutralize the introduced during programming hot electrons. Programming and erasing a p-channel transistor requires reverse voltage conditions respectively.

Preferably, the ribs FIN have a height (distance between the adjacent to the buried oxide layer BOX rib bottom side to the rib top 10) of 20 to 50 nm. By separate control of the left and right side wall transistor (extending to the rib side surfaces 12 and 14, transistor channels) can be stored charges in the memory layer 18 on both sides. Using the known technique of NROMs read a total of 4 bits can thus in each storage layer 18 in the corner areas near the contact regions S / D to be stored. This allows the formation of a high-density 1F 2 - storage element with a 2F cell 2 with 2 bits. 2F 2 cells is shown schematically in FIG. 1.

Fig. 3 shows a schematic cross-sectional view taken along section line BB of Fig. 1. The sectional plane passing through the bit line BL1 and one of the contact regions S / D of the cell array. The gate electrodes WL from each other by an insulating sheath 30, preferably consisting of silicon nitride, electrically insulated. The longitudinal direction of the rib FIN 1 is schematically indicated in Fig. 3 by a labeled (FIN) arrow. The bit line BL1 is highly doped with a diffusion barrier 34

Contact region S / D electrically connected. The bit line BL1 is made of metal, preferably tungsten, and is in Fig. Cutting plane 3 illustrated by spacers 36, which preferably consists of a HTO oxide (high temperature oxide) which of the memory layer 18 and the word lines WL separately.

The reference to FIGS. 1 to 3 described preferred embodiment of a semiconductor memory according to the invention is characterized in particular by lower programming voltages than conventional NROM or ETOX cells. Further, there is a lesser area required for charge pumps, by reducing the required peak voltage. The separate control of the left and right flank of the FINFETs (left and right side wall transistor) further allows the excellent storage density of 1F 2 per bit.

Fig. 4 shows a schematic plan view of a further

Embodiment of an inventive semiconductor memory. In connection with Figs. 1 - the same or similar features described 3 are provided in Figures 4 and 5 with the same reference numerals, and a repeated description will be omitted.. While it is in reference to FIGS. 1 - 3 described embodiment is a so-called "virtual ground array (VGA)", is shown in Figs. 4 and 5, a memory cell array shown in a so-called NAND arrangement. The running direction of the web-like ribs FIN of semiconductor material is again represented by a labeled (FIN) arrow. In contrast to the embodiment shown in Fig. 1 arrangement, however, the word lines WL are substantially perpendicular to the longitudinal direction (FIN) of the ribs FIN. "Bit lines" in the narrower sense are in such an NAND array of memory cells not present, but consist of a series connection of a plurality of transistors having FinFET-like structure. Fig. 5 shows a schematic cross section along the section line AA of Fig. 4. The cutting plane passing through the ribs FIN 1 and FIN 2 along the word line WLl. In contrast to the previously described embodiment, the word lines WL extend, that is, the gate electrodes, perpendicular to the longitudinal axes of the ribs. The storage layer 18 is formed as an electrically conductive floating gate, which consists for example of heavily doped polysilicon. A strong positive charging of the word line WL over the channel region of the transistors leads to a field-assisted tunnel injection of electrons from the injection edge 16 to the floating gate 18 through the first insulator layer 20 (see FIG. Inset of Fig. 5). By the edge effect of the injection edge 16 of the charge carriers from the channel region are sufficient for this so-called Fowler-Nordheim tunneling in the storage layer 18 already potential differences of which are considerably lower than the known conventional NAND memory cell programming voltages.

To erase the floating gate conductive is preferably a deletion edge 32 is used, which is formed in the floating gate 18 in the edge region of the first insulator layer 20 with the outer oxide layer 28th The storage density of this embodiment is provided with 4 to 5 F 2 (see FIG. The drawn in Fig. 4 4 F 2 -Speicherzelle) are less than the in connection with Figs. 1 - described first embodiment. 3 Compared to conventional NAND memories is, however, a significant voltage reduction through the use of a peak or edge effect both for programming and for the deletion of the storage layer 18. Furthermore, a higher read rate achieved since the read current of the individual memory cells through the sidewall of transistors compared to expected is amplified conventional planar devices. Figs. 6-14 are schematic sectional views of a preferred Zwichenprodukten semiconductor memory according to the invention as described in connection with Figs. 1 - has been described. 3 Fig. 6 shows a schematic cross-sectional view of an intermediate product of the semiconductor memory of Fig. 1 along line AA. On an SOI wafer (silicon on insulator wafer), a thermal oxide is first formed, which later constitutes the first insulator layer twentieth a silicon nitride layer is deposited on the oxide layer 20, which later forms the storage layer 18 (trapping layer). Subsequently, a layer of TEOS is applied to the nitride layer eighteenth Means of optical lithography or electron beam lithography are opened in the resist between the ribs FIN window and removed by an etching step, the TEOS, nitride, oxide and top silicon layer, so that a web-like rib structure (Finne structure) is formed. Subsequently, the resist and the TEOS layer is removed. The obtained after this process step

Intermediate product is shown in Fig. 6.

Subsequently, the rib side surfaces 12, 14 are thermally oxidized to produce the injection edge sixteenth Due to the lower oxidation rate of the ribs FIN near the first insulator layer 20 have the rib side surfaces 12, 14 near the first insulator layer 20 on a curved course. The injection edges 16 are therefore not shown simplified in the figures have a rectangular edge profile. The different oxidation rates in the field of rib top 10 cause the injection edges 16 have an internal angle which is smaller than 90 °. Such injection edges 16 are for local field enhancements - and thus lower programming voltages necessary - particularly suitable. Following the thermal oxidation to produce the inner oxide layers 26, the deposition of a high temperature oxide is performed (high temperature oxide; HTO) as an outer oxide layer 28. The oxide layer 28 forms the "control gate oxide" so-called, which is the third insulator layer 29th The intermediate for this process step is shown in Fig. 7.

This is followed by deposition of poly-silicon which is highly doped in situ to form the word lines. As shown in Fig. 8, is the cross section of the word lines WL shown schematically obtained by a spacer etch, which self-aligned without any additional mask technique leads to the word lines WL, which extend along the sides of the ribs FIN. This state is shown in Fig. 8 schematically.

After filling the interstices by nitride (see. Fig. 9 shows the structure of the bit lines Figure 1 takes place.. 10 shows in a schematic cross-sectional view taken along the line CC of Fig. The later semiconductor memory is a section along the bit line BL1. The bit line BL1, which later, in parallel to the drawing plane of Figs. 10 - 14 passes, is formed by a photo step with subsequent etching steps of the insulation covering 30 forming the nitride layer, which is arranged on the memory layer 18 HTO film, the storage layer 18 (nitride layer), an etching-back the polysilicon wordline WL and etching the first insulator layer 20 (oxide layer) is prepared (see. Fig. 10). the mixture is subsequently filled into the etched-back word line space nitride and is etched back (FIG. 11). in the embodiment shown in Fig. 12 cross-sectional view, the following HTO can deposition and spacer etching the HTO oxide for preparing the S shown in Fig. 3 pacerschicht 36 not recognize. The HTO spacer 36 protects the storage layer 18 (nitride-trapping layer) on the wall to the word line WL and avoids a short circuit therewith.

Fig. 13 shows the intermediate product after the n + - implantation of the contact regions S / D. The contact regions S / D (source and drain contact regions of the FinFET) are electrically connected by perpendicular to the word lines WL extending bit lines BL via a diffusion barrier 34 with a metal bit line BL. For removing and planarizing the surface of the bit line BL, a CMP step (chemical mechanical polishing) is used. In this state, the semiconductor memory device in Fig. 14 is shown.

LIST OF REFERENCE NUMBERS

10 rib top

12 (left) side face of ribs

14 (right) side face of ribs

16 injection edge

18 memory layer, particularly trapping layer or floating gate

20 first insulator layer

22 (left) second insulator layer

24 second (right) insulator layer

26 inner oxide layer 28 outer oxide

29 third insulator layer (control gate oxide is preferably formed by outer oxide layer 28)

30 insulation cover

32 extinguishing edge for NAND cell via F / N tunneling 34 diffusion barrier

36 spacer from HTQ

BL bit line

FIN fin of semiconductor material word line WL

Claims

claims
1. A semiconductor memory comprising a plurality of memory cells, each memory cell comprising: a first conductively doped contact region (S / D), a second conductively doped contact region (S / D) and an interposed channel region, which in a web-like rib (FIN) from semiconductor material formed in this order in the longitudinal direction of the rib (FIN) are arranged one behind the other, wherein the fin (FIN) extending at least in the channel region in a perpendicular to the longitudinal direction of the rib (FIN) section, a substantially rechtsecksförmige shape with a rib top (10 ) and opposing rib side surfaces (12, 14); a designed for programming the memory cell storage layer (18) through a first insulator layer (20) spaced on the rib top (10) is arranged, wherein the storage layer (18) via at least one (12) of the rib side surfaces (12) in
Normal direction of the one rib side surface (12) protrudes, so that said one rib side surface (12) and the rib top (10) form an injection edge (16) for injection of charge carriers from the channel region into the storage layer (18); and at least one gate electrode (WLL), which is spaced apart from the one rib side surface (12) and through a third insulator layer (29) of the storage layer (18) through a second insulator layer (22), wherein the gate electrode (WLL) opposite the channel region electrically is insulated and adapted for controlling its electrical conductivity.
2. The semiconductor memory according to claim 1, wherein said second insulator layer (22) has a greater layer thickness than the third
Insulator layer (29).
3. The semiconductor memory according to claim 1 or 2, wherein said second insulator layer (22) disposed on at least one rib side surface (12) inner oxide layer (26) and on the inner oxide layer (26) arranged outer oxide layer (28).
4. The semiconductor memory according to claim 3, wherein the outer oxide layer (28) forms the third insulator layer (29).
5. The semiconductor memory according to one of claims 3 or 4, wherein the inner oxide layer (26), a thermal oxide, and the outer oxide layer (28) is a HT-oxide.
6. The semiconductor memory according to one of the preceding claims, wherein said first insulator layer (20) is formed of a thermal oxide.
7. The semiconductor memory according to one of the preceding
Claims, wherein the fin (FIN) is arranged in a top silicon layer of an SOI substrate.
8. The semiconductor memory according to one of the preceding claims, wherein a plurality of equally spaced ribs (FIN 1, FIN2) is provided extend to each other the longitudinal axes parallel, and in each of the fins (FIN 1, FIN2) is formed a plurality of memory cells.
9. The semiconductor memory according to one of the preceding claims, wherein the storage layer (18) is a trapping layer or floating gate.
10. The semiconductor memory according to claim 9, wherein the trapping layer comprises a nitride layer, a silicon-rich oxide layer (Silicon Rich Oxide) or an undoped poly-silicon layer is separated from the channel region and the gate electrode (WL) by oxide layers (20, 29) ,
Wherein the gate electrodes (WLl, WL2) extend 11. The semiconductor memory according to claim 10, wherein two mutually electrically insulated gate electrode (WLl, WL2) are provided for the at least one rib (FINL) in the direction of the ribs longitudinal axis and second insulator layers (22, 24) (from the opposing rib side surfaces 12, 14) are spaced apart.
12. The semiconductor memory according to claim 11, wherein the gate electrodes (WL) are formed of highly doped poly-silicon.
13. Semiconductor memory according to one of claims 11 or 12 and claim 8, wherein for each of the ribs (FINL; FIN2) of the semiconductor memory are provided two mutually insulated gate electrodes as word lines (WL3, WL4 WLl, WL2).
14. A semiconductor memory according to claim 13 extending to a plurality of perpendicular to the word lines (WL) bit lines (BL), each of said bit lines (BL) with one of the contact regions (S / D) of each fin (FIN) is electrically connected.
15. The semiconductor memory according to claim 9, wherein the floating gate made of metal or highly doped poly-silicon.
16. The semiconductor memory according to claim 15 and claim 8 with a plurality of the gate electrodes (WL), wherein each of the channel regions in one of the fins (FIN) exactly one of the gate electrodes (WL) is associated, which as a word line (WL) of the semiconductor memory perpendicular to the longitudinal axis of the fins (FIN) over a plurality of fins (FIN) extends.
17. A semiconductor memory according to any one of claims 15 or 16, wherein the floating gate has at least a deletion edge (32) for injection of charge carriers from the floating gate to the gate electrode (WL) through the third insulator layer (29).
18. A semiconductor memory according to claim 17, wherein the erasing edge (32) of the floating gate adjacent to an edge region defined by the first insulator layer (20) and the third insulator layer (29) is formed.
19. A method for manufacturing a semiconductor memory according to one of the preceding claims comprising the steps of: - providing an SOI substrate having a top silicon layer;
Depositing the first insulator layer (20) on the top silicon layer; Applying the storage layer (18) on the first insulator layer (20);
Patterning the top silicon layer, the first insulator layer (20) and the storage layer (18) in at least one web-like rib shape, the first insulator layer (20) on the rib top (10) the group consisting of silicon fin (FIN) and the storage layer (18 ) is disposed on the first insulator layer (20); Oxidizing the rib side surfaces (12, 14) of the fin (FIN) to form an inner oxide layer (26) of the second insulator layer (22, 24);
Applying the third insulator layer (29); Applying the at least one gate electrode (WL); and - local doping the fin (FIN) to form doped contact regions (S / D).
20. The method of claim 19, wherein the application of the third insulator layer (29) comprises applying an outer oxide layer (28), which is arranged on the storage layer (18) and of the inner oxide layer (26).
EP20030793747 2002-09-05 2003-08-21 High-density nrom-finfet Withdrawn EP1535336A2 (en)

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US20050186738A1 (en) 2005-08-25

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