EP1514303A2 - Layer assembly and method for producing a layer assembly - Google Patents

Layer assembly and method for producing a layer assembly

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Publication number
EP1514303A2
EP1514303A2 EP03760551A EP03760551A EP1514303A2 EP 1514303 A2 EP1514303 A2 EP 1514303A2 EP 03760551 A EP03760551 A EP 03760551A EP 03760551 A EP03760551 A EP 03760551A EP 1514303 A2 EP1514303 A2 EP 1514303A2
Authority
EP
European Patent Office
Prior art keywords
layer
material
useful
decomposable
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03760551A
Other languages
German (de)
French (fr)
Inventor
Hans-Joachim Barth
Recai Sezi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE10227615 priority Critical
Priority to DE2002127615 priority patent/DE10227615A1/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to PCT/DE2003/001827 priority patent/WO2004001842A2/en
Publication of EP1514303A2 publication Critical patent/EP1514303A2/en
Application status is Withdrawn legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a layer assembly and to a method for producing a layer assembly. This layer assembly comprises a layer that is placed on a substrate. Said layer comprises a first partial region, which is made of a decomposable material, and an adjacent second partial region with a useful structure made of a non-decomposable material. The layer assembly also has a top layer which is arranged on the layer made of a decomposable material and the useful structure. The layer assembly is designed so that the decomposable material can be removed from the layer assembly.

Description

description

Layer arrangement and method for manufacturing a layered arrangement

The invention relates to a layer arrangement and a method for producing a layer arrangement.

In the semiconductor technology, in particular in forming integrated circuits, electrically insulating layers are required for many applications. Insulating layers are formed in an integrated circuit, in which electrically conductive regions, in particular conductor tracks, are included, then a coupling capacitance between adjacent conductors and an interposed dielectric layer can result. The capacitance between two parallel conductive tracks whose adjoining surfaces designated A and are arranged at a distance d from each other, is found to be at a relative dielectric constant e of the dielectric:

C = eA / d (1)

With the progress of miniaturization of silicon microelectronics, that is, with decreasing distance d between adjacent interconnects concerns especially a large coupling capacitance C, when the adjoining faces A of the conductor tracks are large, that is if the conductor tracks over a large wavelength range in the integrated circuit away parallel to each other. Problems with coupling capacitances take progresses

Reduction to an integrated circuit. The

Transit time of a signal in a conductor increases with increasing coupling capacitance because this delay is determined by the product of the ohmic resistance R and capacity C (so-called "RC delay").

As can be seen from equation (1), a decrease in coupling capacitance C is at fixed structure dimensions A, d possible when the relative

E dielectric constant of the insulating material is reduced. It is therefore attempted, as materials for insulating layers in integrated circuits, those having a low relative dielectric constant e to use (so-called "low k materials").

As the dielectric for the electrical uncoupling of metal conductors from each other amorphous silicon dioxide (Si0 2) is often used with a relative dielectric constant of about 4.0.

The performance of advanced semiconductor chips (0.18μm technology and smaller) will become increasingly serious worsened by the RC delay of the traces. Therefore, silica is no longer suitable as a dielectric material for future high-performance requirements.

From the 0.13μm technology generation low-k dielectrics are used with dielectric constants of less than 3 typically increasingly. Examples include SiLK ™ k "2.7 OxD (oxazole dielectric material) with k = 2.5, Black Diamond ™ k" 2.9, Coral ™ with k = 2.9. A further reduction of the value of the relative

Dielectric constant of electrically insulating

Layers by introducing voids in "low-k

Material "possible because a (vacuum) has cavity in the ideal case a k value of k = l. Depending on the volume fraction of the

Voids or pores of the k-value of the porous material is reduced. For future technology generations porous materials are increasingly being used such as porous SiLK with k = 2.2, porous OxD k «2.1, Nanoglass with k = 2.2 and JSR LKD (low k dielectric JSR) with k '2.2.

Porous low-k materials are removed l (vacuum or approximately air) still far from the theoretical optimum k =.

[1], [2] it is known, so-called "air gaps" that is of solid material-free intermediate areas between interconnects, and a thorough understanding intermetallic dielectric material. However, this known structure has the particular

Disadvantage that they are on the non-conformal deposition of silicon dioxide or a CVD ( "Chemical Vapor Deposition") - low-k material (SiOC) based. Characterized Air-Gaps although may be formed, however, the silicon dioxide and SiOC remains partially received, so that the effective dielectric constant attainable is only slightly below the value k =. 2

[3] discloses a copper / air-hole structure which is fabricated using a sacrificial polymer and a silicon oxide layer. Semiconductor device, wherein above on a

Substrate conductor tracks formed an apertured

Layer is formed, located between the conductor tracks material is discharged through the holes.

[5] discloses a layer arrangement with conductor tracks on a substrate and a porous layer on the conductor tracks, wherein material of a sacrificial structure is evaporated between the conductor tracks and discharged through the porous layer.

[6] discloses an integrated circuit with air holes between the dielectric and electrically conductive lines.

The invention is based on the problem, a layer of - providing arrangement in which a parasitic capacitance of components of a useful structure over the prior art is reduced.

The problem is solved by a layer arrangement and by a method for producing a layer arrangement having the features according to the independent claims.

The layer arrangement of the invention comprises means disposed on a substrate layer having a first portion made of a decomposable material and arranged next to the second partial region with a useful structure of a non-degradable material. Further, the shift arrangement has a covering layer on the layer of decomposable material and the useful structure. The layer arrangement is arranged such that the degradable material consists of the layer arrangement is removable. Further, a method for producing a layer arrangement is provided according to the invention, in which a layer is formed on a substrate having a first portion made of a decomposable material and arranged next to the second partial region of a useful structure of a non-degradable material. Further, a covering layer on the layer of decomposable material and the useful structure is formed. The layer arrangement is set up such that the degradable material consists of the layer - assembly is removable.

Illustratively, a layer arrangement according to the invention is provided with an embedded between two layers layer having decomposable material and a useful structure. The useful structure may for example comprise conductive tracks of an integrated circuit. Between conductor tracks of the useful structure, parasitic capacitances may occur, according to equation (1) are greater, the greater is the relative permittivity of which is arranged between the conductor tracks decomposable material. The decomposable material in combination with the top layer according to the invention is arranged such that by means of suitable treatment of the Schich the decomposable material can be thermally decomposed or vaporized arrangement (e.g., via temporary perns Te). Characterized the decomposable material is removed from the layer arrangement by preferably diffuses through the topcoat. After such a treatment areas between the useful components of now decomposed decomposable material are free, so that a relative dielectric constant of ε = l is obtained in the ideal case. Thereby, the RC delay is significantly reduced, since the capacitance C in accordance with equation (1) is lowered. To this

Thus, it is possible to arrange adjacent conductor paths at a constant signal propagation time with a reduced distance from each other, which comes to meet the trend for miniaturization in semiconductor technology. The parasitic capacitive coupling between conductor tracks, in particular in

Metallization of an integrated circuit is therefore reduced according to the invention. A complex forming pores or a complex patterning of a dielectric layer for generating voids is thus avoided according to the invention.

Clearly, arranged between the conductor paths of a metallization level dielectric material is removable. The conductor tracks on both sides are mechanically stabilized in the vertical direction by a layer (covering layer or substrate). Ideally, at least the top layer of a material permeable to the decomposition products of the interposed layer of material is preferably itself a low-k material.

Preferred developments of the invention emerge from the dependent claims.

Preferably, the layer arrangement may have an intermediate layer between the substrate and the layer of decomposable material and the useful structure. The intermediate layer may be made of low-k material and / or may be configured such that the material of the useful structure is protected due to the functionality of the intermediate layer from diffusing from the layer arrangement. The substrate may preferably comprise silicon and may, in particular, a silicon wafer or a silicon chip to be.

Thereby, the processing of the layer arrangement in the

Standard processes of silicon microelectronics be integrated.

The cover layer and / or the intermediate layer may be made of dielectric material. In particular, the cover layer and / or the intermediate layer of silicon oxide, silicon nitride, SiLK, porous SiLK, oxazole, porous oxazole, Black Diamond, Coral, nano glass, JSR LKD, polybenzoxazoles, polybenzimidazoles, polyimides, polyquinolines, polyquinoxalines, polyarylenes and / or polyarylene ethers have.

The cover layer of the layer arrangement is preferably arranged such that it is permeable to decomposed decomposable material. More preferably, the top layer is arranged such that it is protected from destruction or damage in carrying out a decomposition process. In particular, the top layer should be protected from thermal decomposition or thermal damage when heated to a temperature range of about 250 ° C to about 400 ° C. This temperature range is typical for a thermal Zersetzverfahren to decompose the decomposable material. However, the exact Zersetztemperatur depends on the choice of material in individual cases.

The useful structure may be made of an electrically conductive material, in particular of aluminum and / or copper and / or a dielectric material such as silicon dioxide (Si0 2), silicon nitride (Si 3 N 4) or ceramic materials. In particular, copper is suitable as a material for conductor tracks of an integrated circuit, since it has a very low ohmic resistance, whereby the

RC delay can be kept low. Aluminum is both planar be deposited and then be structured and using a damascene method processable. When using copper as the material of the

Useful structure, it is advantageous to form a copper-structure by first a dielectric layer is deposited and patterned, and then using the damascene method in introducing copper material of dielectric-material-free areas. Such

Layer sequence can preferably be planarized using a CMP process ( "Chemical Mechanical Polishing"). It should be emphasized that in the event of a utility structure from an electrically insulating or dielectric material, an electrically conductive passivation layer is not necessary, at least between the useful and the cover layer.

Preferably, the decomposable material is thermally decomposable, that is, by means of heating to a predetermined temperature for a predetermined time in a given chemical environment (for example, under a protective gas atmosphere of argon, nitrogen or in a vacuum) of the layer - assembly removable. The required dec-temperature depends mainly on the choice of the material of the thermally decomposable layer. Further, the decomposable can temperature by using a mixture of different material components for the thermally decomposable structure are modified. Also, by setting the other process parameters at a thermal decomposition (for example, ambient pressure, etc.) can be influenced to the required Zersetztemperatur. The decomposable material may be decomposed as thermally alternatively in a different way. Has the decomposable material, for example, the property of electromagnetic radiation of a suitable wavelength range (for example, UV radiation) to absorb sufficiently strong and the absorption of such electromagnetic radiation through the covering layer is sufficiently low, the decomposition of the decomposable layer may by irradiating electromagnetic radiation on the inventive layer arrangement can be realized.

Suitable materials or classes of materials for the degradable material, for example, polyester, (predominantly aliphatic) polyethers such as polyethylene glycol, polypropylene glycol, polyethylene oxide or polypropylene oxide. Also suitable are polyacrylates, Polyτnethacrylate, polyacetals, polyketals, polycarbonates, polyurethanes, polyether ketones, cycloaliphatic polymers such as polynorbornene, predominantly aliphatic polyamides, novolacs, polyvinyl phenols, and epoxy compounds. Also suitable are copolymers or ter-polymers of the mentioned material classes.

Preferably, the decomposable material is photosensitive or photostructured, such as a resist.

In particular, a photoimageable resist may be one of the following combinations of a basic polymer and a photoactive component and photo acid.

As polymer can be used: polyacrylates, polymethacrylates, polyacetals, polyketals, co-polymers with maleic anhydride (such as styrene / maleic anhydride), aliphatic, aromatic or cycloaliphatic polymers with tert

Butyl [(COOC (CH 3) 3] such as tert-butyl ethacrylate or tert-butoxycarbonyloxy groups [(OCOO (CH 3) 3] such as tert

Butoxycarbonyloxystyrene (= t-BOC vinyl phenol).

As photoactive components are, for example

salts or Diazoketones, diazoquinones, Triphenylsulfoniu

Diphenyljodoniumsalze.

Suitable solvents for dielectric materials, resist or the decomposable material used temporarily, for example, methoxypropyl acetate, ethoxypropyl acetate, ethoxyethyl propionate, N-methylpyrrolidone, gamma-butyrolactone, cyclohexanone or cyclopentanone suitable.

In the inventive arrangement at least one layer-support structure is preferably formed in the arranged between the substrate and the topcoat layer. To improve the mechanical properties, it can be advantageous, such a support structure, preferably, use of metallic material where there is the chip layout to sufficiently large areas free of material. The support structure may for example be configured as a support column. Particularly, under the bond pads support columns for mechanically stabilizing are advantageous.

Furthermore, the layer arrangement may have a along the lateral boundary of the substrate extending substantially protective structure for protecting the useful against influences of the environment. Clearly, a completely impermeable protective ring is preferably at least 2 microns wide metal traces, and preferably multiple, also continuous long-Vias can at the chip edge (sealing ring) are carried out to an outgoing from the chip edge corrosion or

Oxidation of the realized as conductor tracks in the useful structure

Chip inside to avoid.

The useful structure may be at least partially covered by a

Passivation be surrounded ( "Liner"). Particularly in the case of using copper as the material for the useful structure a diffusion barrier to prevent the out-diffusion of the copper material or for improving the adhesion of the copper material is advantageous.

Furthermore, the inventive method for fabricating the layer assembly will be described. Embodiments of the layer arrangement also apply to the method for fabricating the layer assembly.

Preferably, the decomposable material is removed from the layered arrangement, for example, by thermally decomposing.

According to the method for producing a layer arrangement, the utility structure can be formed of copper and are at least partially coated with a passivation layer, which passivating layer by means of a (preferably selectively) electroless plating method of cobalt -tungsten-phosphorus (CoWP), cobalt -tungsten boron (CoWB), cobalt phosphor (CoP) or ruthenium (Ru) are formed. Alternatively, the passivation layer may by means of a (preferably selectively) "Chemical Vapor Deposition" - method (CVD method), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten-nitrogen (WN) or tungsten-carbon (WC) are formed. The layer of decomposable material and the useful structure can be formed by decomposable material is deposited and (for example, using a lithography - and an etching AV TATIONS) is patterned material of the useful structure is deposited and (the surface of the layer sequence thus obtained, for example, using a CMP process, "chemical mechanical polishing") is planarized. This method is particularly useful in

Using copper as the material for the useful structure is advantageous.

Alternatively, the layer of decomposable material and the useful structure can be formed by material of the useful structure is deposited and patterned (for example, using a lithography process and an etching process) is deposited and decomposable material. When using a metallic material for the useful structure, for example aluminum or copper, this method is referred to as forming the useful damascene process. The surface of the layer sequence thus obtained may then be planarized (eg, using a CMP process).

According to the inventive method, at least one additional stack of layers can be formed on the capping layer, the additional layer stack comprises an additional top layer on an additional layer of decomposable material and a useful structure.

Clearly two or more levels of Schich arrangement according to the invention can be formed sequentially. The layer arrangement contains in this case a

Substrate having thereon a first layer of useful structure and thermally decomposable material, formed thereon a first cladding layer, formed thereon a second layer of useful structure and decomposable material, formed thereon a second clad layer, a formed thereon third layer of useful structure and decomposable material, a third top layer, and so on.

In other words, a plurality of inventive layer assemblies can be stacked on one another, which in particular in the forming of a plurality of metallization planes in the silicon microelectronics advantageous (typically up to ten metallization). To remove the degradable material consists of the layer arrangement with as few work steps, a common decomposition method can be applied after forming all the layers or part of the layers (eg thermally). Is a particularly safe and complete removal of the decomposable material on the layer to ensure arrangement, this can double layer are subjected to a decomposition process, alternatively, after forming in each case a double layer of a layer of useful structure and decomposable material and a cover layer. In other words, each double layer is exposed to a separate decomposition process.

Preferably separate the useful structures can be coupled electrically and mechanically to each other by a cover layer by introduced into the top layer at least one contact hole and being filled with electrically conductive material. In addition, some typical values ​​and materials are listed. The thickness of the intermediate layer is preferably between lOOnm and lOOOnm. preferred

Layer thicknesses for the layer of decomposable material and the useful are between about lOOnm and about lOOOnm. A typical thickness for a photoresist for

Patterning an underlying layer is preferably between 200nm and lOOOnm. In addition, a

be anti-reflection layer is provided (e.g., BARC, "Bottom Anti Reflective Coating").

For lithography process during the formation of the layer arrangement according to the invention, for example, the wavelengths 248 nm, 193 nm, 157 nm or a wavelength in the extreme ultraviolet can be used (EUV lithography "extreme ultraviolet").

In summary, it should be noted that by means of a thermal-decomposable or vaporizable material, which can easily diffuse during the decomposing by the cover layer, a novel possibility is created outwardly mechanically sealed cavity structures, in particular as low-k dielectrics to form. In particular between conductor tracks of an integrated circuit "Air-Gaps" can be generated by the decomposable material is decomposed. This can achieve a significant reduction of the capacitive coupling of the interconnects and thus the RC signal delay.

Further, a simple and feasible using standard methods production method for the inventive layer arrangement is provided. Also, the invention in the context of a multi-layer metallization, an integrated, for example, for a plurality of metallization

Circuit usable. increase mechanical support structures as well as a guard ring, preferably at the chip edge, the mechanical stability of the layer arrangement.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it:

1A to 1R layer sequences at different times during the inventive method of manufacturing a layer arrangement according to the invention according to different

Embodiments of the invention.

In addition, a method for producing a layer arrangement is described according to a first embodiment of the invention with reference to Fig.lA to Fig.lH.

In order to obtain the layer sequence shown in Fig.lB 102 on a silicon wafer 100 (see FIG. Fig.lA) is formed a bottom layer 104 of polybenzoxazole. For this purpose, first, a polybenzoxazole precursor (poly-o-hydroxyamide) coated from a solution in N-methylpyrrolidone using spin-coating technology on the silicon wafer 100 and dried on a hot plate for about two minutes at about 120 ° C. Thereafter, the coated Siliziu - substrate annealed in an annealing furnace under a nitrogen atmosphere for about 60 minutes at about 420 ° C 100th Due to the annealing, the polybenzoxazole precursor is converted into polybenzoxazole material. The thickness of the dielectric bottom layer 104 is lμm.

In order to obtain the layer sequence shown in Fig. IC 106, an auxiliary layer 108 of photoresist on the

Layer sequence 102 applied. For this purpose a decomposable and photoactive film of a copolymer of tert-butyl methacrylate and methyl methacrylate (20 weight parts), a photo-acid of triphenylsulfonium trifluoromethanesulfonate and is methoxypropyl acetate as

Solvent (80 parts by weight) was applied using a spin coating technique to the ground layer 104 and dried for about 1 minute at about 100 ° C.

In order to obtain the layer sequence shown in Fig.lD 110, the resist auxiliary layer is heated 108 using a photomask (web-trench mask for the conductor tracks) exposed (exposure wavelength 248 nm) and 100 seconds on a hot plate at 100 ° C (so-called "post-exposure bake"), developed approximately 60 seconds with an aqueous-alkaline developer NMD-W of Tokya Ohka and dried for 1 minute at 100 ° C. This creates on the auxiliary layer 108, a decomposable structure 112 made of decomposable material. The Fig.lD according vertical height of the decomposable structure 112 is about lμm.

In order to obtain the layer sequence shown in Fig.lE 114, using the PECVD process ( "plasma enhanced chemical vapor deposition"), the layer sequence 110 with a thin layer combination of liner (tantalum material, 30 nm) and a copper seed layer ( coated about lOOnm). Alternatively, a PVD ( "Physical Vapor Deposition"), and for applying these layers, ie, a sputtering method, can be used. The copper seed layer is then electrically amplified such that all

Trenches regions between respective adjacent components of the structure 112 decomposed with copper material are filled. As shown in Fig.lE in accordance Fig.lE vertical height of the copper material 116 is greater than the vertical height of the decomposable structure 112th

In order to obtain the layer sequence shown in Fig.lF 118, the copper material 116 using the CMP method ( "chemical mechanical polishing") is dished so far that it forms a common plane surface with the decomposable pattern 112 on the surface. In other words, the copper material is ground above the decomposable structure 112th For passivating the

Copper surface is applied a deposited selectively using an electroless deposition method, cobalt tungsten phosphorus layer (not shown in the figure). The remaining copper material forms the copper conductor tracks 120th

In order to obtain the layer sequence shown in FIG. IG 122, to the layer sequence 120 is (analogously as described above) a further polybenzoxazole precursor applied and dried. Thus, a dielectric layer is formed of polybenzoxazole 124th

In order shown in Fig.lH layer 126 to obtain arrangement according to a first preferred embodiment of the invention, the layer sequence 122 is subjected to an annealing process. the underlying decomposable structure is decomposed from resist material 112 during the annealing of the benzoxazole -Dielektrikums at 420 ° C, so that cavities 128 remain. In this step, the dielectric cap layer 124 is protected from damage, since the decomposed material of the decomposable structure 112 diffuses through the cover layer 124th As the cavities 128 have a relative dielectric constant of approximately one, the copper forming strip conductors 120 to each other a reduced coupling capacitance.

In addition, a second preferred embodiment of the layer arrangement according to the invention will be described.

For this purpose, starting from the position shown in Fig.lH layer - 126 analogously to the method steps described with reference to Fig.lA to Fig.lH to the cover layer 124, another layer of decomposable material and juxtaposed areas of decomposable material is formed (not shown in the arrangement Figure). Above the last mentioned layer, a further dielectric layer is formed so that two conductor track planes are overlaid realized. Each conductor track plane is surrounded on both sides in the vertical direction by a respective dielectric layer. The method is not limited to two layers, but it may be formed and processed as many layers to each other.

In addition, a layered arrangement, referring to Fig. II 130 described according to a third embodiment of the invention.

The manufacturing method for forming the layer arrangement 130 is performed substantially the same way as described above with reference to Fig.lA to Fig.lH. The essential difference between the method of manufacturing the arrangement Schich

130 and the method of manufacturing the arrangement Schich

126 is that in the process described with reference to Fig.lD process step for patterning the auxiliary layer 108 to the decomposable structure 112, the

Patterning is performed such that the component shown in Fig.lD 112a of the decomposable structure 112 is additionally structured such that the component is divided into two spatially decoupled from each other subcomponents 112a, between which a further cavity is arranged. The further cavity is in a filled to the reference Fig.lE described method step, the analog processing step with copper material, so that when received to Fig.lF Fig.lH to analog processing, the layer arrangement 130 shown in Fig. II. This includes, in addition to a copper support column 132 which is provided in order to improve the mechanical stability of the layer arrangement 130th

A description is given with reference to Fig.lA to Fig.lH, Fig.lJ Fig. IN a method for producing a layer arrangement according to a fourth embodiment of the invention.

According to the fourth embodiment of the manufacturing method of the invention, the process steps shown above with reference to Fig.lA Fig.lH to be carried out first.

In order to obtain the layer sequence shown in Fig.lJ 134, a photoresist layer 136 is applied to the embodiment shown in Fig.lH layer sequence and structured. The application of the photoresist layer 136 is analogous to that above with reference to Fig. IC deposition of the auxiliary layer

described 108th Further, the photoresist layer is exposed to a contact hole mask 136th After a "post-exposure bake" and the development of a contact hole 138 which is located directly above one of the copper traces 120 is formed. As shown in Fig.lJ Further, the residual

Surface of the cover layer 124 covered with the photoresist layer 136th

In order to obtain the layer sequence shown in Fig.lK 140, the dielectric material of the cover layer 124 is etched in the contact hole 138 by means of an oxygen plasma for 100 seconds, whereby the surface of the copper conductor tracks is exposed 120th This creates a viaducts hole 142. To remove an oxide layer may be located on the surface of the copper conductor 120 another 20 seconds is etched by means of an argon plasma.

In order to obtain the layer sequence shown in Fig.lL 144, the remaining photoresist layer 136 is removed by a two minute treatment with N-methylpyrrolidone (stripped) dried and the layer sequence thus obtained for 60 seconds at 120 ° C.

To obtain the in Fig. IM shown layer sequence 146, the via hole 142 is filled with electroplated copper material to form the copper-contacting 148th

To obtain the layer arrangement IN shown in FIG. 150, as above with respect to the second

Embodiment described, formed a further double layer consisting of a layer with juxtaposed decomposable material and additional copper circuitry 152 and a further cover layer 156th Further, the decomposable material is thermally expelled from the thus processed additional bilayer. As shown in Fig. IN, creating additional cavities 154 are formed.

Furthermore, a method for manufacturing a layered arrangement according to a fifth embodiment of the invention will be described.

This embodiment is a modification of the method for fabricating the layer assembly 126 which is described with reference to the Fig.lA to Fig.lH. However, deviation from this is used instead of a polybenzoxazole - precursor is a low-k material, namely the material SiLK ™ (trademark of Dow Chemical Company) used as a material for the bottom layer 104th Instead of the use according to the first embodiment, the material for the auxiliary layer 108, a resist is used with the following components: 20 parts by weight of polyvinylphenol, whose phenolosche hydroxyl groups are blocked with a tert-butoxycarbonyloxy group (poly-t-BOC-vinylphenol); 1 part by weight of diphenyliodonium trifluoromethanesulfonate as a photo-acid; and 80 parts by weight of ethoxyethyl acetate as the solvent. Apart from the materials used, alternatively a layered arrangement is obtained, which corresponds substantially to that shown in Fig.lH layer assembly 126th

According to a method for producing a layer arrangement according to a sixth embodiment of the invention, a Schich arrangement similar to the arrangement layer 150 formed as described above with reference to the fourth

Embodiment described. However, according to the sixth embodiment, the components are used in accordance with the fifth embodiment, as a material for the photoresist and the dielectric.

Furthermore, referring to Fig.lA to Fig.lH, Fig.lJ described a method for producing a layer arrangement according to a seventh embodiment of the invention to Fig.lL, Figlo to Fig.lR.

First Fig.lJ the layer sequence 144 is, as described above with reference to Fig.lA to Fig.lH described to Fig.lL formed.

In order to obtain the layer sequence shown in Figure 10 158, another photoresist layer 160 is spin-coated from decomposable and photo-active material and dried.

In order to obtain the layer sequence shown in Fig.lP 162, the further photoresist layer is exposed to a conductor track photomask 160th The conductor track photomask is that that passage of the further photoresist layer is exposed 160, above which the via hole 142 was located previously selected such. The proportion present in the original via hole 142 of the further photoresist layer 160 is thus exposed and removed in the subsequent developing. This results in the typical dual-Dame scene structure shown in Fig.lP in which are exposed in the cap layer 124, the via hole 142 and a conductor track 120th Further, layer 160 is formed a further decomposable structure 164 from the structured further photoresist. In order to obtain the layer sequence shown in Fig. IQ 166, more copper circuitry 166 are described above with reference to Fig.lE, Fig.lF formed. Simultaneously the via hole 142 is filled with copper material. In other words, by means of a liner (e.g., tantalum) and a copper seed layer deposition, both the via hole

142 as well as free from further decomposable structure 164 surface areas of the layer sequence 162

Copper material covered. Excess copper and liner material is removed using a CMP process, thereby forming a planar surface of the layer sequence is achieved 166th

To obtain the layer arrangement shown in Fig.lR 170, the layer sequence shown in Fig. IQ is described on Fig. IG, Fig.lH 166 processed analogously as described above with reference. First, a further cover layer is applied to the surface of the layers resulted in 166 172nd Subsequently, the remaining photoresist material of the further decomposable structure 164 is removed by annealing, thereby further cavities are formed 174th

Furthermore, a method of manufacturing a layer is - described arrangement according to an eighth embodiment of the invention.

On a silicon substrate (wafer) is a polyimide precursor (polyamic acid) prepared from diaminodiphenyl ether and benzene tetracarboxylic acid, from a solution in N-methylpyrrolidone using a

Spin-coating technique, and dried on a hot plate for 2 minutes at 120 ° C. Subsequently, the coated substrate is annealed in an annealing furnace under a nitrogen atmosphere for about 60 minutes at about 420 ° C. Due to the annealing, the polyimide precursor is converted into polyimide. The ceiling of this layer as a dielectric layer serving polyimide film is about lμm.

Subsequently, a solution of a polyester (poly-1,4-butylene terephthalate) is applied by means of a spin coating technique to the dielectric and dried for about 3 minutes at about 150 ° C on a hotplate. The thickness of this layer is about lμm. The polyester layer, an approximately 200 nm thick silicon dioxide layer is deposited as a hard mask for patterning the decomposable polyester layer by means of CVD ( "Chemical Vapor Deposition"). The silicon dioxide layer is coated with a resist layer, which is composed of the following components: 20 parts by weight m-cresol novolak, 6 parts by weight of a triester of 2,3,4-trihydroxybenzophenone and naphthoquinone-diazide-4-sulfonic acid, and 80 parts by weight methoxypropyl.

After drying of the resist for 2 minutes at 100 ° C whose layer thickness is approximately 0.8μm.

The resist layer using a photo mask (web-trench mask) exposed (exposure wavelength 365 nm), developed with an aqueous alkaline developer AZ 303 from Celanese for approximately 60 seconds and dried at 100 ° C for 1 minute. The vertical height of the resist structures is approximately 0.8μm.

The resist pattern is by using a CHF 3 etching process -Plasma- for 30 seconds in the first silicon dioxide layer, then using 0 2 plasma etch for 60

Seconds transferred to the decomposable polyester layer. The

Silicon dioxide layer acts as an etch mask. During this transfer of the structures, the photoresist is - material is removed due to etching.

Subsequently, the silicon dioxide layer is removed by means of an approximately 60 seconds of treatment with an HF solution, rinsed the layer sequence with distilled water and dried for 60 seconds at 100 ° C.

The polyester structures produced according to this production method, polyimide correspond approximately to the layer sequence shown in Fig.lB 110. Based on this layer sequence can be proceed according to any of easily manufacturing method according to the invention to form a layer arrangement.

In this document, the following publications are cited

[1] BP Shieh, LC Bassmann, D.-K. Kim, KC Saraswat, MD Deal, JP Mc Vittie, RS List, S. Nag, L. Ting, Proc. IEEE IITC 1998, 125-127

[2] Demolliens, 0. et al. , Proceedings of IITC 2000, 276, 277

[3] carbon, P et al. (2000) "Air-Gaps in 0.3 micron Electrical Interconnections," IEEE Electron Device Letters, Vol.21, No.12, p.557-559

[4] DE 44 41 898 Cl

[5] US 5,461,003

[6] US 6,342,722 Bl

Reference Signs List 100 silicon wafer 102 layer sequence 104 ground layer 106 layer sequence 108 auxiliary layer 110 layer sequence 112 decomposable structure 112a component 114 layer sequence 116 of copper material 118 layer sequence 120 copper circuitry 122 layer sequence 124 covering layer 126 layer assembly 128 cavities 130 layer assembly 132 copper support column 134 layer sequence 136 photoresist layer 138. Contact hole 140 layer sequence 142 via hole 144 layer sequence 146 layer sequence 148 copper contact 150 layer assembly 152 additional copper circuitry 154 additional cavities 156 additional outer layer 158 layer sequence 160 further photoresist layer 162 layer sequence 164 further decomposable structure 166 layer sequence

168 further copper traces

170 layer assembly

172 additional topcoat

174 more cavities

Claims

claims:
1st layer arrangement
• having disposed on a substrate layer having a first portion made of a decomposable material and arranged next to the second partial region with a useful structure of a non-degradable material;
• with a covering layer on the layer of decomposable material and the useful;
• with an electrically conductive passivation layer at least between the useful and the cover layer;
• wherein the layer arrangement is set up such that the degradable material consists of the layer arrangement is removable.
2. Layer arrangement according to claim 1 with an intermediate layer between the substrate and the layer of decomposable material, and from the useful structure.
3. wherein the substrate comprises layer arrangement according to claim 1 or 2 silicon.
4. Layer arrangement according to claim 2 or 3, wherein said coating layer and / or the intermediate layer is made of dielectric material.
5. Layer arrangement according to one of claims 2 to 4, wherein said coating layer and / or the intermediate layer of one or a combination of the materials
• silicon oxide;
• Siliziurnnitrid; SiLK; porous SiLK; oxazole; porous oxazole; Black Diamond; Coral; Nanoglass; JSR LKD; polybenzoxazole; polybenzimidazole; polyimide; polyquinoline; polyquinoxaline; polyarylene; and polyarylene st
6. Layer arrangement according to one of claims 1 to 5, wherein said coating layer is arranged such that it is permeable to decomposed decomposable material.
7th Layer arrangement according to one of claims 1 to 6, wherein the useful structure is made of an electrically conductive material.
8th Layer arrangement according to claim 7, wherein the useful structure
• Silver;
• a silver alloy;
• of tungsten;
• tungsten silicide; • Aluminum;
• an aluminum alloy;
• copper; and or
• a copper alloy.
9. Layer arrangement according to one of claims 1 to 6, wherein the useful structure is made of a dielectric material.
10. Schich arrangement according to claim 9, wherein the useful structure
• silicon dioxide;
• silicon nitride; and or
• a ceramic material has.
11. Layer arrangement according to one of claims 1 to 10, wherein the decomposable material is thermally decomposable.
12. layer arrangement according to one of claims 1 to 11, wherein the decomposable material is one or a combination of
• polyester;
• polyether;
• polyethylene glycol;
• polypropylene glycol;
• polyethylene oxide;
• polypropylene;
• polyacrylate;
• polymethacrylate; polyacetal; Polyketal; polycarbonate; polyurethane; polyether ketone; cycloaliphatic polymer; polynorbornene; aliphatic polyamide; novolak;
polyvinylphenol; an epoxy compound; Co-polymer of these compounds; and comprising Ter-polymer of these compounds.
13. layer arrangement according to one of claims 1 to 12, wherein the decomposable material is photosensitive.
14. layer arrangement according to one of claims 1 to 13, wherein in the arranged between the substrate and the topcoat layer comprises at least a support structure is formed.
15. layer arrangement according to one of claims 1 to 14 with a line extending along the lateral boundary of the substrate protection structure for protecting the useful against influences of the environment.
16. layer arrangement according to one of claims 1 to 15 with a useful structure which at least partially surrounding passivation layer.
17. A method for producing a layer arrangement in which
• a layer is formed on a substrate having a first portion made of a decomposable material and arranged next to the second partial region with a useful structure of a non-degradable material;
• is a covering layer on the layer of decomposable material and the useful structure is formed; • is an electrically conductive passivation layer at least between the useful and the cover layer is formed;
• wherein the layer arrangement is configured such that the degradable material consists of the layer arrangement is removable.
18. The method of claim 17, wherein the decomposable material is removed from the layer arrangement.
19. The method of claim 18, wherein the decomposable material is removed from the layer arrangement by means of thermally decomposing.
20. The method according to any one of claims 17 to 19, wherein
• is the useful structure formed of copper;
• the useful structure is at least partially coated with a passivation layer, which passivation layer is formed by a o "Electroless deposition" process of cobalt-tungsten-phosphorus, cobalt-tungsten-boron, cobalt-phosphorus, or ruthenium; or o by means of a "chemical vapor deposition" -
Method of tantalum, tantalum nitride, titanium nitride, tungsten, tungsten-nitrogen or tungsten
Carbon is formed.
21. The method according to any one of claims 17 to 20, wherein the layer of decomposable material and the useful structure is formed by
• decomposable material is deposited and patterned;
• Material is deposited the useful;
• is the surface of the layer sequence thus obtained planarized.
22. The method according to any one of claims 17 to wherein the layer of decomposable material and the useful structure is formed by • the useful material is deposited and patterned 20;
• decomposable material is deposited;
• is the surface of the layer sequence thus obtained planarized.
23. The method according to any one of claims 17 to 22, wherein the at least one additional stack of layers is formed on the cover layer, the additional layer stack comprises an additional top layer on an additional layer of decomposable material and a useful structure.
24. The method of claim 23, are coupled to each other in which separate from each other by a cover layer useful structures by introduced into the top layer at least one contact hole and being filled with electrically conductive material.
EP03760551A 2002-06-20 2003-06-03 Layer assembly and method for producing a layer assembly Withdrawn EP1514303A2 (en)

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DE2002127615 DE10227615A1 (en) 2002-06-20 2002-06-20 Layer arrangement and method for producing a layer arrangement
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DE10227615A1 (en) 2004-01-15
CN1663040A (en) 2005-08-31
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TW200400561A (en) 2004-01-01
TWI222137B (en) 2004-10-11

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