EP1494507B1 - Digital interface with a potentiometer - Google Patents

Digital interface with a potentiometer Download PDF

Info

Publication number
EP1494507B1
EP1494507B1 EP04013161.7A EP04013161A EP1494507B1 EP 1494507 B1 EP1494507 B1 EP 1494507B1 EP 04013161 A EP04013161 A EP 04013161A EP 1494507 B1 EP1494507 B1 EP 1494507B1
Authority
EP
European Patent Office
Prior art keywords
amplitude
digital
interface
voltage
operating device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP04013161.7A
Other languages
German (de)
French (fr)
Other versions
EP1494507A1 (en
Inventor
Juen Reinhold
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tridonic GmbH and Co KG
Original Assignee
Tridonic GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tridonic GmbH and Co KG filed Critical Tridonic GmbH and Co KG
Publication of EP1494507A1 publication Critical patent/EP1494507A1/en
Application granted granted Critical
Publication of EP1494507B1 publication Critical patent/EP1494507B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/185—Controlling the light source by remote control via power line carrier transmission

Definitions

  • the invention relates generally to an interface for a lamp operating device, in particular for a ballast for a gas discharge lamp, to lamp operating devices with such interfaces and to methods for generating control commands, in particular dimming commands for a lamp operating device.
  • Similar interfaces are known from printed publications US 5,611,811 and EP 1 128 711 ,
  • a user is thus to be given the option of manually entering control commands via a digital interface, in particular dimming commands for an electronic ballast.
  • German patent application 197 08 784 An electronic ballast is known which (in the embodiment according to FIG. 7) has an interface device.
  • This interface device can be controlled via pushbutton signals or switch signals as well as via digital control signals.
  • a connected electronic ballast can then be switched on or off by a (short or long) button press.
  • a DSI (Digital Signal Interface) operation is possible in which certain digital commands, for example, setpoints for a brightness control, etc. transmit.
  • control commands eg dimming setpoints
  • a further object of the present invention is to provide a simple possibility of dimming such an operating device by means of a digital interface.
  • an interface for a lamp operating device, in particular for a ballast (ECG) for gas discharge lamps.
  • the interface has two input-side terminals of a digital control input and an evaluation logic, which can basically process both applied to the terminals digital signals as well as mains voltage signals.
  • a voltage divider or a potentiometer for continuously adjusting the amplitude of the voltage applied to the terminals of the digital control input mains voltage is provided.
  • the setting of a potentiometer in the manner of a dimmer is more intuitive for the user, since now a position (for example, a rotational position) and no longer a time duration reflects the desired dimming value.
  • the interface may comprise means for implementing the amplitude of the applied mains voltage in a pulse width information.
  • the evaluation logic can be designed to convert the (digital) pulse width information into control commands for a lamp operating device.
  • the evaluation logic can be designed to convert the pulse width information into dimming control values for a lamp operating device.
  • Zener diodes can subject the applied mains voltage at the digital interface to bipolar threshold formation.
  • a lamp operating device in particular a dimmable ballast for gas discharge lamps is provided which has an interface of the type mentioned above.
  • the invention also proposes a method for generating dimming commands for a lamp operating device, in particular for a ballast for gas discharge lamps.
  • the amplitude of a voltage applied to a digital interface mains voltage is detected and the amplitude level converted into a digital pulse width information that reflects how long the amplitude of the mains voltage has exceeded or fallen below a predetermined threshold.
  • This pulse width information can then be processed digitally as a dimming command for the lamp operating device.
  • the amplitude of the applied mains voltage can be continuously adjustable.
  • the implementation of the amplitude level in a digital pulse width information can be done in particular by means of a Zener diode circuit.
  • the interface device prepares these signals applied to the input-side terminals U IN1 , U IN2 in such a way that, irrespective of the nature of the applied signals, a digital signal is output at an output-side terminal OUT whose logic value corresponds to that at the input terminals U IN1 , U IN2 corresponding signal corresponds.
  • the digital logic signal output by the interface device may then be evaluated, for example, by a subsequent controller, which in turn may be connected to an electronic device, such as a Lamp operating device (eg electronic ballast electronic ballast) or LED operating device controls accordingly.
  • the input side (terminals U IN1 , U IN2 ) and the output side (OUT) of the inventive interface device are galvanically isolated from each other, which is schematically represented by the element GT.
  • element GT for galvanic isolation for example, optocouplers, transformers and level offset stages come into question.
  • One of the input-side terminals U IN2 can be connected directly to this galvanic isolation element GT.
  • an ohmic resistor R1 a positive temperature coefficient element (PTC element) PCT and two (optional) Zener diodes D1, D2 can be connected in series between the other input side terminal U IN1 and this element GT.
  • PTC element positive temperature coefficient element
  • the output signals of the element GT for galvanic isolation are fed to a AusretelogiK AL having a comparator KOMP.
  • the comparator KOMP compares the output signal of the element GT for galvanic isolation (input 3 of the comparator) with a voltage applied to the inverted input 2 reference or threshold signal of the comparator KOMP. Depending on the comparison, the comparator KOMP then forwards the logic signal OUT, for example, to the controller.
  • the ohmic resistor R1 must apply electrical energy to heat when a mains voltage signal is applied until the PTC element heats up and enters the high-impedance state, whereby the current falls through this path again.
  • the zener diodes D1, D2 serve to define the low level of the digital signal.
  • the interface is designed to process an analog signal derived from a mains voltage signal at the digital control input.
  • a voltage divider (potentiometer) ST upstream which is supplied with mains voltage U NETZ .
  • this voltage divider ST it is possible to set the amplitude of the voltage applied to the digital control input mains voltage U NETZ substantially continuously.
  • other means are conceivable to change the amplitude of the supplied mains voltage.
  • Fig. 2 shows a modification of Fig. 1 to the effect that the evaluation logic AL according to Fig. 2 Is part of the electronic ballast.
  • Fig. 2 provided that at the digital control input SE of the interface ES, that is to say more precisely at the two input-side terminals U IN1 , U IN2 a voltage divider ST is connected, which is supplied with the mains voltage U NETZ .
  • Fig. 3 provides a circuit in the interface ES (for example, the Zener diode circuit D1, D2, according to Fig. 1 ) that the (analog) amplitude information is converted at the output of the voltage divider ST and thus at the input of the digital control input SE of the interface IS in a (digital) pulse width modulation, which is supplied to the Ausretelogik AL and from this in turn in control signals for a connected operating device ECG is implemented.
  • the amplitude information set by the user by means of the potentiometer ST can be converted into pulse width information and then converted by the evaluation logic in dimming control values for a ballast.
  • the adjustment of the amplitude can be effected steplessly by means of the voltage divider / potentiometer ST.
  • Fig. 3 the case is described that the peak value of the voltage applied to the digital control input SE once has a value U MAX1 and at another time the smaller value (U MAX2 ⁇ U MAX1 ).
  • the peak value at the digital control input SE can be adjusted, for example, by a user by hand and a potentiometer.
  • the interface circuit ES for example, by means of in Fig. 1 Zener diode circuit D1, D2 shown a threshold value + - U TH performed.
  • the input signal of the evaluation logic AL sees accordingly schematically as in Fig. 3 , bottom illustration. With a high amplitude U MAX1 of the AC voltage applied to the digital control input SE results in a PWM signal with a relatively high duty cycle t 1 and corresponding to a large duty cycle.
  • the duty cycle is then converted by the evaluation logic AL by means of a table or function implemented in it in dimming position values, on / off commands, etc.
  • a dimmable ballast can be realized with an interface which can be dimmed both with digital control signals (eg DALI, DSI) and with a continuously adjustable mains voltage.
  • the mains voltage U NETZ is supplied via a voltage divider ST the digital control input SE of the interface SI.
  • the voltage at the digital control input SE also changes.
  • the interface circuit SE supplies this variable voltage or an equivalent signal via a galvanic coupling GK to the evaluation logic AL.
  • the evaluation logic AL then ensures that, for example, a lamp is dimmed in accordance with the signal amplitude applied to the digital control input SE.
  • the invention can be used, for example, in a simple manner with dimmable floor lamps, which are already equipped in many cases with a potentiometer / dimmer.

Description

Die Erfindung bezieht sich allgemein auf eine Schnittstelle für ein Lampen-Betriebsgerät, insbesondere für ein Vorschaltgerät für eine Gasentladungslampe, auf Lampen-Betriebsgeräte mit derartigen Schnittstellen sowie auf Verfahren zur Erzeugung von Steuerbefehlen, insbesondere Dimmbefehlen für ein Lampen-Betriebsgerät. Ähnliche Schnittstellen sind bekannt aus Druckschriften US 5 611 811 und EP 1 128 711 .The invention relates generally to an interface for a lamp operating device, in particular for a ballast for a gas discharge lamp, to lamp operating devices with such interfaces and to methods for generating control commands, in particular dimming commands for a lamp operating device. Similar interfaces are known from printed publications US 5,611,811 and EP 1 128 711 ,

Einem Benutzer soll somit die Möglichkeit gegeben werden, manuell über eine digitale Schnittstelle Steuerbefehlre, insbesondere Dimmbefehle für ein EVG, einzugeben.A user is thus to be given the option of manually entering control commands via a digital interface, in particular dimming commands for an electronic ballast.

Aus der EP 0 641 148 A1 ist es allgemein bekannt, mittels einer analogen Phasen-Anschnitttechnik ein Dimmen eines elektronischen Vorschaltgeräts zum Versorgung einer Last, wie beispielsweise einer Lampe, auszuführen.From the EP 0 641 148 A1 It is generally known to perform dimming of an electronic ballast for supplying a load, such as a lamp, by means of an analog phase gating technique.

Auch der deutschen Patentanmeldung 197 08 784 ist ein elektronisches Vorschaltgerät bekannt, das (in der Ausführungsform gemäss Figur 7) eine Schnittstellenvorrichtung aufweist. Diese Schnittstellenvorrichtung kann dabei über Tastersignale bzw. Schaltersignale wie auch über digitale Steuersignale angesteuert werden. Im Falle eines angeschlossenen Tasters kann dann ein angeschlossenes elektronisches Vorschaltgerät durch einen (kurzen bzw. langen) Tastendruck ein- bzw. ausgeschaltet werden. In gleicher Weise ist jedoch auch ein DSI (Digital Signal Interface)-Betrieb möglich, bei dem bestimmte digitale Befehle beispielsweise Sollwerte für eine Helligkeitsregelung etc. übermitteln.Also the German patent application 197 08 784 An electronic ballast is known which (in the embodiment according to FIG. 7) has an interface device. This interface device can be controlled via pushbutton signals or switch signals as well as via digital control signals. In the case of a connected button, a connected electronic ballast can then be switched on or off by a (short or long) button press. In the same way, however, a DSI (Digital Signal Interface) operation is possible in which certain digital commands, for example, setpoints for a brightness control, etc. transmit.

Bei der aus der DE 197 08 784 bekannten Schnittstellenvorrichtung ist es nachteilig, dass bei Anschluss eines mit Netzspannung versorgten Tasters oder Schalters an die Schnittstellenvorrichtung der Benutzer diejenige Betätigungsdauer des Tasters oder Schalters wählen muss, die dem vom Benutzer gewünschten Dimmwert entspricht. Mit anderen Worten, der Benutzer muss geistig einen Dimmwert in eine Betätigungsdauer für den Taster oder Schalter umrechnen.At the time of the DE 197 08 784 known interface device, it is disadvantageous that when connecting a supplied with mains voltage button or switch to the interface device, the user must select that actuation duration of the button or switch, which corresponds to the desired dimming value by the user. In other words, the user has to mentally convert a dimming value into an operating time for the button or switch.

Ausgehend von diesem Stand der Technik ist es Aufgabe der vorliegenden Erfindung, die manuelle Eingabe von Steuerbefehlen (bspw. Dimm-Sollwerte) für elektronische Vorschaltgeräte mit einer digitalen Schnittstelle intuitiver zu gestalten. Weiterhin ist es Aufgabe der vorliegenden Erfindung, eine einfache Möglichkeit bereit zu stellen, mittels einer digitalen Schnittstelle ein derartiges Betriebsgerät zu dimmen.Based on this prior art, it is an object of the present invention to make the manual input of control commands (eg dimming setpoints) for electronic ballasts with a digital interface more intuitive. A further object of the present invention is to provide a simple possibility of dimming such an operating device by means of a digital interface.

Diese Aufgabe wird erfindungsgemäß durch die Merkmale der unabhängigen Ansprüche gelöst. Die abhängigen Ansprüche bilden den zentralen Gedanken der Erfindung in besonderes vorteilhafter Weise weiter.This object is achieved by the features of the independent claims. The dependent claims further form the central idea of the invention in a particularly advantageous manner.

Erfindungsgemäß ist also eine Schnittstelle für ein Lampen-Betriebsgerät, insbesondere für ein Vorschaltgerät (EVG) für Gasentladungslampen vorgesehen. Die Schnittstelle weist dabei zwei eingangsseitige Anschlüsse eines digitalen Steuereingangs sowie eine Auswertelogik auf, die grundsätzlich sowohl an den Anschlüssen anliegenden Digitalsignale wie auch Netzspannungssignale verarbeiten kann. An dem digitalen Steuereingang ist dabei ein Spannungsteiler oder ein Potentiometer zur kontinuierlichen Einstellung der Amplitude der an den Anschlüssen des digitalen Steuereingangs anliegenden Netzspannung vorgesehen. Das Einstellen eines Potentiometers in der Art eines Dimmers ist für den Benutzer intuitiver, da nunmehr eine Stellung (bspw. eine Drehstellung) und nicht mehr eine zeitliche Dauer den gewünschten Dimmwert wiedergibt.Thus, according to the invention, an interface is provided for a lamp operating device, in particular for a ballast (ECG) for gas discharge lamps. The interface has two input-side terminals of a digital control input and an evaluation logic, which can basically process both applied to the terminals digital signals as well as mains voltage signals. At the digital control input while a voltage divider or a potentiometer for continuously adjusting the amplitude of the voltage applied to the terminals of the digital control input mains voltage is provided. The setting of a potentiometer in the manner of a dimmer is more intuitive for the user, since now a position (for example, a rotational position) and no longer a time duration reflects the desired dimming value.

Weiterhin kann die Schnittstelle Mittel zur Umsetzung der Amplitude der anliegenden Netzspannung in einer Pulsbreiten-Information aufweisen.Furthermore, the interface may comprise means for implementing the amplitude of the applied mains voltage in a pulse width information.

Die Auswertelogik kann dazu ausgelegt sein, die (digitale) Pulsbreiten-Information in Steuerbefehle für ein Lampen-Betriebsgerät umzusetzen. Insbesondere kann die Auswertelogik dazu ausgelegt sein, die Pulsbreiten-Information in Dimm-Stellwerte für ein Lampen-Betriebsgerät umzusetzen.The evaluation logic can be designed to convert the (digital) pulse width information into control commands for a lamp operating device. In particular, the evaluation logic can be designed to convert the pulse width information into dimming control values for a lamp operating device.

Zener-Dioden können dabei die anliegende Netzspannung an der digitalen Schnittstelle einer bipolaren Schwellenwertbildung unterziehen.Zener diodes can subject the applied mains voltage at the digital interface to bipolar threshold formation.

Gemäß einem weiteren Aspekt der vorliegenden Erfindung ist ein Lampen-Betriebsgerät, insbesondere ein dimmbares Vorschaltgerät für Gasentladungslampen vorgesehen, das eine Schnittstelle der oben angeführten Art aufweist.According to a further aspect of the present invention, a lamp operating device, in particular a dimmable ballast for gas discharge lamps is provided which has an interface of the type mentioned above.

Schließlich schlägt die Erfindung auch ein Verfahren zur Erzeugung von Dimmbefehlen für ein Lampen-Betriebsgerät, insbesondere für ein Vorschaltgerät für Gasentladungslampen vor. Dabei wird die Amplitude einer an einer digitalen Schnittstelle anliegenden Netzspannung erfasst und die Amplitudenhöhe in eine digitale Pulsbreiten-Information umgesetzt, die wiedergibt, wie lange die Amplitude der Netzspannung eines vorgegebenen Schwellenwert überschritten oder unterschritten hat. Diese Pulsbreiten-Information kann dann digital als Dimmbefehl für das Lampen-Betriebsgerät verarbeitet werden.Finally, the invention also proposes a method for generating dimming commands for a lamp operating device, in particular for a ballast for gas discharge lamps. In this case, the amplitude of a voltage applied to a digital interface mains voltage is detected and the amplitude level converted into a digital pulse width information that reflects how long the amplitude of the mains voltage has exceeded or fallen below a predetermined threshold. This pulse width information can then be processed digitally as a dimming command for the lamp operating device.

Die Amplitude der anliegenden Netzspannung kann dabei kontinuierlich einstellbar sein.The amplitude of the applied mains voltage can be continuously adjustable.

Die Umsetzung der Amplitudenhöhe in eine digitale Pulsbreiten-Information kann insbesondere mittels einer Zenerdioden-Schaltung erfolgen.The implementation of the amplitude level in a digital pulse width information can be done in particular by means of a Zener diode circuit.

Weitere Merkmale, Vorteile und Eigenschaften der vorliegenden Erfindung werden nunmehr Bezug nehmend auf die Figuren der begleitenden Zeichnungen sowie die folgende Beschreibung von Ausführungsbeispielen näher erläutert.

Fig. 1
zeigt eine Detailansicht eines ersten Ausführungsbeispiels der vorliegenden Erfindung,
Fig. 2
zeigt ein Ausführungsbeispiel der vorliegenden Erfindung, bei der die Auswertelogik (AL) in ein Vorschaltgerät (EVG) für Lampen integriert ist, und
Fig. 3
zeigt Zeitablaufsdiagramme bzgl. der am digitalen Steuereingang anliegenden Spannung (USE) und der daraus entstehenden Pulsbreitenmodulation (PWM).
wie in Figur 1 ersichilich, weist eine Schnittstellenvorrichtung gemässe der vorliegenden Erfindung dabei zwei eingangsseitige Anschlüsse UIN1, UIN2 eines digitalen Steuereingangs SE auf. An diese eingangsseitigen Anschlüsse UIN1, UIN2 können grundsätzlich Digitalsignale beispielsweise mit einer maximalen Amplitude zwischen 20 und 30 Volt oder aber Netzspannungsignale angelegt werden. Die Erfindung betrifft dabei den Fall, dass Signale ausgehend von einer Netzspannung an den digitalen Steuereingang SE angelegt werden.Further features, advantages and features of the present invention will now be explained in more detail with reference to the figures of the accompanying drawings and the following description of exemplary embodiments.
Fig. 1
shows a detailed view of a first embodiment of the present invention,
Fig. 2
shows an embodiment of the present invention, in which the evaluation logic (AL) is integrated in a ballast (EVG) for lamps, and
Fig. 3
shows timing diagrams with respect to the voltage applied to the digital control input voltage (U SE ) and the resulting pulse width modulation (PWM).
as in FIG. 1 Of course, an interface device according to the present invention has two input-side terminals U IN1 , U IN2 of a digital control input SE. In principle, digital signals, for example with a maximum amplitude between 20 and 30 volts or mains voltage signals, can be applied to these input-side terminals U IN1 , U IN2 . The invention relates to the case that signals are applied starting from a mains voltage to the digital control input SE.

Die Schnittstellenvorrichtung bereitet diese an den eingangsseitigen Anschlüssen UIN1, UIN2 anliegenden Signale derart auf, dass unabhängig von der Natur der anliegenden Signale an einem ausgangsseitigen Anschluss OUT ein Digitalsignal ausgegeben wird, dessen logischer Wert dem des an den eingangsseitigen Anschlüssen UIN1, UIN2 anliegenden Signals entspricht. Das von der Schnittstellenvorrichtung ausgegebene digitale Logiksignal kann dann beispielsweise von einem folgenden Controller ausgewertet werden, der wiederum ein angeschlossenes elektronisches Gerät, wie beispielsweise ein Lampenbetriebsgerät (z. B. elektronisches Vorschaltgerät EVG) oder LED-Betriebsgerät entsprechend ansteuert.The interface device prepares these signals applied to the input-side terminals U IN1 , U IN2 in such a way that, irrespective of the nature of the applied signals, a digital signal is output at an output-side terminal OUT whose logic value corresponds to that at the input terminals U IN1 , U IN2 corresponding signal corresponds. The digital logic signal output by the interface device may then be evaluated, for example, by a subsequent controller, which in turn may be connected to an electronic device, such as a Lamp operating device (eg electronic ballast electronic ballast) or LED operating device controls accordingly.

Die Eingangsseite (Anschlüsse UIN1, UIN2) und die Ausgangsseite (OUT) der erfindungsgemässen Schnittstellenvorrichtung sind voneinander galvanisch getrennt, was schematisch durch das Element GT dargestellt ist. Als Element GT zur galvanischen Trennung (Potentialtrennung) kommen dabei beispielsweise Optokoppler, Übertrager und Pegelversatzstufen infrage.The input side (terminals U IN1 , U IN2 ) and the output side (OUT) of the inventive interface device are galvanically isolated from each other, which is schematically represented by the element GT. As element GT for galvanic isolation (potential separation), for example, optocouplers, transformers and level offset stages come into question.

Einer der eingangsseitigen Anschlüsse UIN2 kann direkt mit diesem Element zur galvanischen Trennung GT verbunden sein. Zwischen dem anderen eingangsseitigen Anschluss UIN1 und diesem Element GT können dagegen ein Ohm'scher Widerstand R1, ein Element mit positiven Temperaturkoeffizienten (PTC-Element) PCT sowie zwei (optionale) Zenerdioden D1, D2 in Serie geschaltet sein.One of the input-side terminals U IN2 can be connected directly to this galvanic isolation element GT. By contrast, an ohmic resistor R1, a positive temperature coefficient element (PTC element) PCT and two (optional) Zener diodes D1, D2 can be connected in series between the other input side terminal U IN1 and this element GT.

Die Ausgangssignale des Elements GT zur galvanischen Trennung werden einer AuswertelogiK AL zugeführt, die einen Komparator KOMP aufweist. Der Komparator KOMP vergleicht das Ausgangssignal des Elements GT zur galvanischen Trennung (Eingang 3 des Komparators) mit einem an dem invertierten Eingang 2 anliegenden Referenz- oder Schwellenwertsignals des Komparators KOMP. Abhängig von dem Vergleich gibt der Komparator KOMP dann das Logiksignal OUT beispielsweise an den Controller weiter.The output signals of the element GT for galvanic isolation are fed to a AuswertelogiK AL having a comparator KOMP. The comparator KOMP compares the output signal of the element GT for galvanic isolation (input 3 of the comparator) with a voltage applied to the inverted input 2 reference or threshold signal of the comparator KOMP. Depending on the comparison, the comparator KOMP then forwards the logic signal OUT, for example, to the controller.

Bei dem Aufbau der in der Figur 1 dargestellten Schnittstellenvorrichtung wurde insbesondere darauf geachtet, dass verhältnismässig wenige und kostengünstige Bauteile verwendet werden. Wie im folgenden erläutert werden wird, weist eine derartige Schnittstellenvorrichtung dennoch die erforderliche Festigkeit gegenüber einer dauerhaft anliegenden Netzspannung auf sowie gegenüber Spannungsspitzen (Bursts) auf.In the structure of the in the FIG. 1 In particular, care has been taken to ensure that relatively few and inexpensive components are used. As will be explained below, however, such an interface device still has the required strength against a permanently applied mains voltage as well as against voltage spikes (bursts).

Der Ohm'sche Widerstand R1 muss bei Anliegen eines Netzspannungs-Signals so lange elektrische Energie in Wärme umsetzen, bis das PTC-Element sich erwärmt und in den hochohmigen Zustand übergeht, wodurch der Strom durch diesen Pfad wieder abfällt.The ohmic resistor R1 must apply electrical energy to heat when a mains voltage signal is applied until the PTC element heats up and enters the high-impedance state, whereby the current falls through this path again.

Die Zenerdioden D1, D2 dienen zur Definition des Low-Pegels des Digitalsignals.The zener diodes D1, D2 serve to define the low level of the digital signal.

Für die vorliegende Erfindung ist es grundsätzlich ausreichend, dass die Schnittstelle dazu ausgelegt ist, ein von einem Netzspannungssignal abgeleitetes Analogsignal an dem digitalen Steuereingang zu verarbeiten.For the present invention, it is basically sufficient that the interface is designed to process an analog signal derived from a mains voltage signal at the digital control input.

Wie in Fig. 1 ersichtlich ist an dem digitalen Steuereingang SE ein Spannungsteiler (Potentiometer) ST vorgeschaltet, der mit Netzspannung UNETZ versorgt ist. Mittels diese Spannungsteilers ST ist es möglich, die Amplitude der an dem digitalen Steuereingang anliegenden Netzspannung UNETZ im Wesentlichen kontinuierlich einzustellen. Im übrigen sind auch andere Mittel denkbar, um die Amplitude der zugeführten Netzspannung zu verändern.As in Fig. 1 it can be seen at the digital control input SE a voltage divider (potentiometer) ST upstream, which is supplied with mains voltage U NETZ . By means of this voltage divider ST, it is possible to set the amplitude of the voltage applied to the digital control input mains voltage U NETZ substantially continuously. Incidentally, other means are conceivable to change the amplitude of the supplied mains voltage.

Fig. 2 zeigt eine Abwandlung von Fig. 1 dahingehend, dass die Auswertelogik AL gemäß Fig. 2 Teil des Betriebsgeräts EVG ist. Indessen ist auch gemäß Fig. 2 vorgesehen, dass an dem digitalen Steuereingang SE der Schnittstelle ES, d.h. genauer gesagt an den beiden eingangsseitigen Anschlüssen UIN1, UIN2 ein Spannungsteiler ST angeschlossen ist, der mit der Netzspannung UNETZ versorgt ist. Fig. 2 shows a modification of Fig. 1 to the effect that the evaluation logic AL according to Fig. 2 Is part of the electronic ballast. However, it is also according to Fig. 2 provided that at the digital control input SE of the interface ES, that is to say more precisely at the two input-side terminals U IN1 , U IN2 a voltage divider ST is connected, which is supplied with the mains voltage U NETZ .

Wie nunmehr bezugnehmend auf Fig. 3 erläutert werden wird, sorgt eine Schaltung in der Schnittstelle ES (beispielsweise die Zenerdioden-Schaltung D1, D2, gemäß Fig. 1) dafür, dass die (analoge) Amplitudeninformation am Ausgang des Spannungsteilers ST und somit am Eingang des digitalen Steuereingangs SE der Schnittstelle IS in eine (digitale) Pulsbreitenmodulation umgesetzt wird, die der Auswertelogik AL zugeführt wird und von dieser wiederum in Steuersignale für ein angeschlossenen Betriebsgerät EVG umgesetzt wird. Insbesondere kann die Amplitudeninformation, die vom Benutzer mittels des Potentiometers ST eingestellt wird, in eine Pulsbreiten-Information und dann durch die Auswertelogik in Dimm-Stellwerte für ein Vorschaltgerät umgesetzt werden. Die Einstellung der Amplitude kann dabei mittels des Spannungsteiler /Potentiometers ST stufenlos erfolgen.Referring now to Fig. 3 will be explained, provides a circuit in the interface ES (for example, the Zener diode circuit D1, D2, according to Fig. 1 ) that the (analog) amplitude information is converted at the output of the voltage divider ST and thus at the input of the digital control input SE of the interface IS in a (digital) pulse width modulation, which is supplied to the Auswertelogik AL and from this in turn in control signals for a connected operating device ECG is implemented. In particular, the amplitude information set by the user by means of the potentiometer ST can be converted into pulse width information and then converted by the evaluation logic in dimming control values for a ballast. The adjustment of the amplitude can be effected steplessly by means of the voltage divider / potentiometer ST.

In Fig. 3 ist der Fall geschildert, dass der Scheitelwert der am digitalen Steuereingang SE anliegenden Spannung einmal einen Wert UMAX1 und zu einem anderen Zeitpunkt den kleineren Wert (UMAX2 < UMAX1) aufweist. Der Scheitelwert der an dem digitalen Steuereingang SE kann bspw. von einem Benutzer per Hand and einem Potentiometer eingestellt werden. In der Schnittstellenschaltung ES wird beispielsweise mittels der in Fig. 1 dargestellten Zenerdioden-Schaltung D1, D2 eine Schwellenwertbildung +- UTH durchgeführt. Das Eingangssignal der Auswertelogik AL sieht dementsprechend schematisch wie in Fig. 3, untere Abbildung, aus. Bei einer hohen Amplitude UMAX1 der am digitalen Steuereingang SE anliegenden Wechselspannung ergibt sich ein PWM-Signal mit verhältnismäßig hoher Einschaltdauer t1 und entsprechend einem grossen Tastverhältnis.In Fig. 3 the case is described that the peak value of the voltage applied to the digital control input SE once has a value U MAX1 and at another time the smaller value (U MAX2 <U MAX1 ). The peak value at the digital control input SE can be adjusted, for example, by a user by hand and a potentiometer. In the interface circuit ES, for example, by means of in Fig. 1 Zener diode circuit D1, D2 shown a threshold value + - U TH performed. The input signal of the evaluation logic AL sees accordingly schematically as in Fig. 3 , bottom illustration. With a high amplitude U MAX1 of the AC voltage applied to the digital control input SE results in a PWM signal with a relatively high duty cycle t 1 and corresponding to a large duty cycle.

Wenn dagegen mittels des Potentiometers/Spannungsteilers ST die Amplitude des an dem digitalen Steuereingang SE der Schnittstelle ES anliegenden Wechselspannung auf einen Wert UMAX2 < UMAX1 gedämpft wird, ergibt sich, wie in Fig. 3, untere Abbildung, dargestellt, am Eingang der Auswertelogik AL ein PWM-Signal mit einer verringerten Einschaltdauer t2 < t1 und entsprechend verringertem Tastverhältnis.If, by contrast, the amplitude of the alternating voltage present at the digital control input SE of the interface ES is attenuated to a value U MAX2 <U MAX1 by means of the potentiometer / voltage divider ST, the result is, as in FIG Fig. 3 , lower figure, shown at the input of the evaluation logic AL a PWM signal with a reduced duty cycle t2 <t1 and correspondingly reduced duty cycle.

Das Tastverhältnis wird dann von der Auswertelogik AL anhand einer in ihr implemetierten Tabelle oder Funktion in Dimm-Stellewerte, Ein-/Aus-Befehle etc. umgesetzt.The duty cycle is then converted by the evaluation logic AL by means of a table or function implemented in it in dimming position values, on / off commands, etc.

Mittels der Erfindung kann also ein dimmbares Vorschaltgerät mit einer Schnittstelle realisiert werden, welche sowohl mit digitalen Steuersignalen (z.B. DALI, DSI) wie auch mit einer kontinuierlich einstellbaren Netzspannung gedimmt werden kann. Die Netzspannung UNETZ wird dabei über einen Spannungsteiler ST den digitalen Steuereingang SE der Schnittstelle SI zugeführt.By means of the invention, therefore, a dimmable ballast can be realized with an interface which can be dimmed both with digital control signals (eg DALI, DSI) and with a continuously adjustable mains voltage. The mains voltage U NETZ is supplied via a voltage divider ST the digital control input SE of the interface SI.

Je nach Stellung des Potentiometers ST ändert sich auch die Spannung am digitalen Steuereingang SE. Die Schnittstellenschaltung SE leitet diese variable Spannung bzw. eine äquivalentes Signal über eine galvanische Kopplung GK der Auswertelogik AL zu. Die Auswertelogik AL sorgt dann dafür, dass beispielsweise eine Lampe entsprechend den am digitalen Steuereingang SE anliegenden Signalamplitude gedimmt wird.Depending on the position of the potentiometer ST, the voltage at the digital control input SE also changes. The interface circuit SE supplies this variable voltage or an equivalent signal via a galvanic coupling GK to the evaluation logic AL. The evaluation logic AL then ensures that, for example, a lamp is dimmed in accordance with the signal amplitude applied to the digital control input SE.

Die Erfindung kann beispielsweise in einfacher Weise bei dimmbaren Stehleuchten verwendet werden, welche in vielen Fällen bereits mit einem Potentiometer/Dimmer ausgestattet sind.The invention can be used, for example, in a simple manner with dimmable floor lamps, which are already equipped in many cases with a potentiometer / dimmer.

Claims (10)

  1. Interface for a lamp operating device, in particular for a ballast (EVG) for gas discharge lamps, having a digital control input (SE) and an evaluation logic (AL) for processing signals present at the terminals and for outputting control commands, characterized by an adjustable voltage divider (ST) voltage, connected to the digital control input (SE) and supplied with network for adjusting the amplitude of a network voltage applied to the digital control input, the amplitude information being converted into dimming setting values.
  2. Interface according to Claim 1, characterized by means (D1, D2) for converting the amplitude of the applied network voltage into an item of pulse width information.
  3. Interface according to Claim 2, characterized in that the evaluation logic (AL) is designed to convert the pulse width information into control commands for a lamp operating device.
  4. Interface according to Claim 2, characterized in that the evaluation logic (AL) is designed to convert the pulse width information into dimming setting values for a lamp operating device (EVG).
  5. Interface according to one of the preceding claims, characterized by Zener diodes (D1, D2) which subject the applied network voltage to a bipolar thresholding.
  6. Lamp operating device, in particular a dimmable ballast (EVG), for gas discharge lamps, having an interface (SI) according to one of the preceding claims.
  7. Method for generating control commands for a lamp operating device, in particular for a ballast for gas discharge lamps, with a digital interface (SI), having the following steps:
    - acquiring the amplitude of an AC voltage, applied to the digital interface (SI), for converting the amplitude information into dimming setting values,
    - converting (D1, D2) the amplitude level of the AC voltage into an item of digital pulse width information which represents how long the amplitude of the AC voltage overshoots a prescribed threshold value, and
    - digital converting (AL) of the pulse width information into a control command for the lamp operating device (EVG).
  8. Method according to Claim 7, characterized by the step of:
    converting (D1, D2) the pulse width information into dimming setting values of a lamp operating device.
  9. Method according to Claim 7 or 8, characterized in that the amplitude of the applied network voltage can be continuously adjusted (ST).
  10. Method according to one of Claims 7 to 9, characterized in that the conversion of the amplitude level into an item of digital pulse width information is performed by means of a Zener diode circuit (D1, D2).
EP04013161.7A 2003-07-01 2004-06-03 Digital interface with a potentiometer Not-in-force EP1494507B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10329683A DE10329683A1 (en) 2003-07-01 2003-07-01 Digital interface with potentiometer
DE10329683 2003-07-01

Publications (2)

Publication Number Publication Date
EP1494507A1 EP1494507A1 (en) 2005-01-05
EP1494507B1 true EP1494507B1 (en) 2013-08-28

Family

ID=33426810

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04013161.7A Not-in-force EP1494507B1 (en) 2003-07-01 2004-06-03 Digital interface with a potentiometer

Country Status (3)

Country Link
US (1) US7466084B2 (en)
EP (1) EP1494507B1 (en)
DE (1) DE10329683A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10329876B4 (en) * 2003-07-02 2016-06-02 Tridonic Gmbh & Co Kg Interface for a lamp operating device with low standby losses and method for driving a lamp operating device via such an interface
EP2182778B1 (en) 2008-10-29 2020-09-02 SITECO GmbH Method for controlling an external light and corresponding lamps
WO2011073498A1 (en) * 2009-12-18 2011-06-23 Nokia Corporation Method and apparatus for driving a led with pulses
AT13027U1 (en) * 2011-09-02 2013-04-15 Tridonic Gmbh & Co Kg CONTROLLABLE OPERATOR
AT16197U1 (en) * 2015-02-12 2019-03-15 Tridonic Gmbh & Co Kg Operating device for a lighting device, system and method for operating a control gear
DE102018206796A1 (en) * 2018-05-03 2019-11-07 Osram Gmbh ADAPTER CIRCUIT
DE102019125445A1 (en) * 2019-07-12 2021-01-14 Erco Gmbh Control gear

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965388A (en) * 1974-12-13 1976-06-22 Arthur D. Little, Inc. Digital light responsive switching circuit
JP3053658B2 (en) * 1991-03-04 2000-06-19 沖電気工業株式会社 Voltage / pulse width modulation circuit
DE4340604A1 (en) 1993-08-25 1995-03-02 Tridonic Bauelemente Ges Mbh Electronic ballast for supplying a load, for example a lamp
US5619081A (en) * 1994-01-18 1997-04-08 Leviton Manufacturing Co., Inc. Asymmetrical AC trigger simulation
US5539281A (en) * 1994-06-28 1996-07-23 Energy Savings, Inc. Externally dimmable electronic ballast
US5872429A (en) * 1995-03-31 1999-02-16 Philips Electronics North America Corporation Coded communication system and method for controlling an electric lamp
US5614811A (en) * 1995-09-26 1997-03-25 Dyalem Concepts, Inc. Power line control system
DE19757295B4 (en) 1997-03-04 2005-08-04 Tridonicatco Gmbh & Co. Kg Electronic ballast
US6094016A (en) * 1997-03-04 2000-07-25 Tridonic Bauelemente Gmbh Electronic ballast
JPH1167471A (en) * 1997-08-26 1999-03-09 Tec Corp Lighting system
US6218787B1 (en) * 1998-04-20 2001-04-17 Jrs Technology Inc. Remote dimming control system for a fluorescent ballast utilizing existing building wiring
US5945789A (en) * 1998-06-01 1999-08-31 Chou; Tsung-Ming Two-wire display lighting control structure
US6229271B1 (en) * 2000-02-24 2001-05-08 Osram Sylvania Inc. Low distortion line dimmer and dimming ballast
US6486616B1 (en) * 2000-02-25 2002-11-26 Osram Sylvania Inc. Dual control dimming ballast
JP3725015B2 (en) * 2000-09-22 2005-12-07 山洋電気株式会社 Uninterruptible power system
US6448713B1 (en) * 2000-12-07 2002-09-10 General Electric Company Sensing and control for dimmable electronic ballast
US6628093B2 (en) * 2001-04-06 2003-09-30 Carlile R. Stevens Power inverter for driving alternating current loads
CA2345456A1 (en) * 2001-04-27 2002-10-27 Lumion Corporation Method and apparatus for controlling lights

Also Published As

Publication number Publication date
US7466084B2 (en) 2008-12-16
EP1494507A1 (en) 2005-01-05
US20050023989A1 (en) 2005-02-03
DE10329683A1 (en) 2005-02-03

Similar Documents

Publication Publication Date Title
EP2334146B1 (en) Operating circuit for light-emitting diodes
DE102011100002B4 (en) Device for controlling a lighting device
EP1935213B1 (en) Method for operating an induction heating device
EP1772040B1 (en) Interface circuit for transmission of digital signals
EP1247431A1 (en) Device for controlling operating means for at least one electric illuminating means and a method for controlling operating means for at least one electric illuminating means
EP1494507B1 (en) Digital interface with a potentiometer
EP3350911B1 (en) Pfc module for intermittent flow
WO2012045478A1 (en) Pwm dimming of light sources
EP1473976B1 (en) Interface for digital and power line control signals and method for dimensioning such an interface
EP2512207A1 (en) Driver circuit and method for powering an LED and illuminant
EP1031258B1 (en) Interface for a lamp operating device
EP2408273A1 (en) Method and device for dimming an illuminant using a microcontroller
DE102012007450A1 (en) Converter for a light source, LED converter and method of operating an LLC resonant converter
EP2375868B1 (en) Electronic pre-switching device with interface device
EP3284319B1 (en) Converter for light sources
DE112015005931B4 (en) Lighting system and method for controlling the lighting system
EP2702838B1 (en) Electronic ballast for an illumination device
DE112011102274B4 (en) Control of operating parameters of control gear for LED
DE102019208960A1 (en) Procedure for operating a dimmer
EP3439159B1 (en) Reduction of light power fluctuations in a threshold control system of an actively clocked converter
AT16694U1 (en) Device for controlling a lighting device
EP1860925B1 (en) Electronic lamp cut-in unit with heater switch
EP3086626B1 (en) Operating circuit, lighting fixture and method for detecting a control signal
EP4102722A1 (en) Electronic switch with n-conductor terminal
WO2014187921A2 (en) Assembly and a method for activating leds

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

17P Request for examination filed

Effective date: 20050321

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20071113

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: TRIDONIC GMBH & CO KG

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 629937

Country of ref document: AT

Kind code of ref document: T

Effective date: 20130915

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502004014321

Country of ref document: DE

Effective date: 20131024

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20130828

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131230

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20130828

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131129

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502004014321

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20140530

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 20140624

Year of fee payment: 11

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502004014321

Country of ref document: DE

Effective date: 20140530

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20140603

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20150227

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140603

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140630

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140630

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20150630

Year of fee payment: 12

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 629937

Country of ref document: AT

Kind code of ref document: T

Effective date: 20150603

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150603

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20040603

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130828

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20140630

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20160603

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20160603

REG Reference to a national code

Ref country code: DE

Ref legal event code: R084

Ref document number: 502004014321

Country of ref document: DE

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20190830

Year of fee payment: 16

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 502004014321

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210101