EP1472615A2 - In-memory arithmetic - Google Patents

In-memory arithmetic

Info

Publication number
EP1472615A2
EP1472615A2 EP02720126A EP02720126A EP1472615A2 EP 1472615 A2 EP1472615 A2 EP 1472615A2 EP 02720126 A EP02720126 A EP 02720126A EP 02720126 A EP02720126 A EP 02720126A EP 1472615 A2 EP1472615 A2 EP 1472615A2
Authority
EP
European Patent Office
Prior art keywords
memory
alu
integer
computer memory
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02720126A
Other languages
German (de)
French (fr)
Inventor
Andrew Ramsay Knox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP1472615A2 publication Critical patent/EP1472615A2/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Definitions

  • the present invention relates to memory subsystems and in particular to memory subsystems which perform simple operations on data stored within the memory subsystems in response to instructions.
  • Prior art approaches to this problem include the use of SGRAM in graphics systems.
  • a bus controller decodes particular opcodes and sends instructions to SGRAM memory requesting it to perform certain operations on data stored in the SGRAM memory.
  • Another prior art approach to this problem is to use shared memory between the processor and a graphics adapter in which the graphics adapter performs operations on the memory.
  • the graphics adapter can have a processor which is optimised for typical graphics operations and so can perform such operations at a higher speed than the CPU.
  • the graphics adapter has to access the memory over the system bus and so access time to that bus is still required.
  • US Patent 4,569,016 discloses a mechanism for performing a ring shift of data under control of a mask.
  • the mechanism disclosed is contained within a CPU and the data must first be transferred from the memory subsystem to the CPU before the operation on the data may be carried out.
  • US Patent 6,061,783 discloses a packet processor for performing specific bit manipulation tasks.
  • the packet processor has a dedicated instruction memory which it reads in order to perform the bit manipulation tasks .
  • the memory is loaded by means of a slow interface from the main processor.
  • Main processor instructions are not stored in the instruction memory .
  • the present invention provides a method for performing simple arithmetic operations in a computer memory, the method comprising the steps of providing a computer system having a central processing unit;
  • ALU Arithmetic Logic Unit
  • Providing an Arithmetic Logic Unit associated with a computer memory means that the transfer of data from memory to CPU and return of that data back to the memory is avoided where the operation to be performed on the data is merely a simple arithmetic or logical operation. Such transfers take up a considerable amount of bus time and consequently slow the operation of a system. Having such simple arithmetic or logical operations performed within a memory improves performance of the system.
  • the instructions identified include bit left shifts, bit right shifts, increment, decrement, negation, integer addition, integer subtraction, integer negation, integer division and integer multiplication.
  • a process is initiated by the central processing unit which causes the ALU to execute the instruction asynchronously to the main processor.
  • the instructions which may be completed by said ALU are identified by virtue of belonging to a pre-defined subset of opcodes.
  • the method further comprises the steps of indicating to said CPU that said computer memory has an ALU associated with it; and the CPU instructing said memory to execute the identified instruction.
  • the present invention also provides a computer memory comprising a plurality of storage locations, each location being capable of storing data; an Arithmetic Logic Unit (ALU) , capable of performing simple arithmetic operations on data stored in one or more of the plurality of storage locations; and wherein the ALU executes instructions intended for a central processing unit, but which are identified as being able to be completed by the ALU associated with the computer memory.
  • ALU Arithmetic Logic Unit
  • FIG. 1 is a block diagram of a simple prior art Advanced Graphics Port (AGP) system where the graphics processor and system processor share memory, the shared memory containing textures for use by the graphics system; and
  • AGP Advanced Graphics Port
  • FIG. 2 is a block diagram of an in-memory ALU of the present invention.
  • Many simple arithmetic operations may be performed on single variable data stored in memory without requiring the processing power of the main system central processing unit. Examples of such operations include the shifting left of bits of data so as to divide by 2, 4, 8, 16 and the like and the shifting right of bits of data so as to multiply by 2, 4, 8, 16 and the like as well as inversion (negation) of each of the bits making up the data so as to multiply or divide by -1, and also incrementing and decrementing the data.
  • first and third embodiments of the present invention A requirement that is met by first and third embodiments of the present invention is that code portability be maintained and that the code will run on systems with or without the additional processing means in the memory subsystem.
  • a further requirement met by second and third embodiments of the present invention is that the additional overhead associated with portability should not exceed the performance gain achieved by implementing the invention. Both of these requirements may be handled in a first embodiment of the present invention in the same way as in the X86/X87 or 680X0 architectures where the use of a separate floating point unit was optional, the code running both on systems with and without a separate floating point processor.
  • dedicated instructions utilising the dedicated processor for memory processing are implemented.
  • the main CPU identifies the presence of the dedicated processor in the memory and instructs it to execute instructions which it is capable of executing.
  • ALU Arithmetic Logic Unit
  • negating a data value illustrates the difference in operation between today's method and using an in-memory technique is shown below. (The internal processing steps associated with address translation, bus timing and the like are omitted) .
  • FIG. 1 shows a prior art RAMBUS/SGRAM implementation 100 using the AGP architecture.
  • Processor 102 comprises a level 2 cache 104 which communicates with the CPU core 106 at a data rate of 2Gb per second.
  • Processor 102 communicates with core logic 110, which includes a memory controller at a data rate of 800Mb per second.
  • the core logic 110 communicates with a PCI bus 120 having PCI slots 122 into which PCI cards 124 may be inserted.
  • the core logic 110 also communicates with system memory 130 at a data rate of 800 Mb per second.
  • the core logic 110 further communicates with graphics controller 140 through an AGP port at a data rate of 528 Mb per second.
  • the graphics controller is connected to graphics memory 142 and provides output to a display 144.
  • Textures using for rendering a displayed image on display 144 are moved from system memory 130 through core logic 110 to the graphics controller 140.
  • the system memory 130 may, for example, contain a
  • Read-Modify-Write instruction which exclusive-ors (XOR) a bit mask onto the contents of graphics memory 142 (SGRAM memory 142 also has a very simple ALU) .
  • a bus controller in the core logic 110 after some overhead in being programmed by the processor 102, sends such commands through the graphics controller 140 to the SGRAM graphics memory 142 for execution.
  • System memory 130 comprises a storage array 132 such as can be found in conventional system memory together with an ALU 134 implementing the present invention.
  • the system memory 130 communicates with the core logic 110 by means of data 210 and address 212 buses and control 214 signals.
  • the system memory 130 also communicates logically with the processor 102 via an "In-memory capable" signal 202 which indicates that the system memory 130 supports in-memory arithmetic.
  • the logical communication is with the processor 102, but as the system memory 130 is only connected to the processor 102 through the core logic 110, the communication is physically through the core logic 110 to the processor 102.
  • the memory subsystem has a set of opcodes which are decoded for the memory subsystem in a similar fashion to that used for a floating point coprocessor.
  • the opcodes initiate processes to actually execute the instruction which run in parallel to the CPU processing opcodes.
  • the CPU polls the memory subsystem for completion at some suitable point in the code.
  • three control bits are provided to interface coprocessors.
  • An example of such a coprocessor is the Motorola MC68881 maths coprocessor, which has special hardware to accelerate floating point operations.
  • the Motorola 68020 coprocessor interface is fully explained in the User's Manual, ISBN-0-13-566860-3 or ISBN-0-13-566878-3.
  • An important feature of this interface is that operation of the coprocessor is undertaken in hardware; the operation is transparent to the programmer, thereby enabling the implementation of various functions without appearing as external hardware to the main processor. This means that, by the use of an exception handling mechanism, programs compiled to make use of, for example, floating point instructions will operate without recompilation regardless of the presence of the coprocessor.
  • a disadvantage of the first embodiment of the present invention is that the clock cycle overhead associated with exception generation/handling is high. This problem is overcome in the second embodiment of the present invention in which a new instruction is defined in the microprocessor command set (and hence the compiler) and in the third embodiment of the present invention in which a different signalling scheme between the CPU and memory are implemented.
  • the processor 102 opcodes are extended, in this case to include an MNEG (memory negate) opcode.
  • MNEG memory negate
  • the new operation involves the processor 102 accessing the data location (s) in the system memory 130 in the normal manner, but instead of reading the data on the processor data bus, the data bus presents the opcode corresponding to the MNEG instruction.
  • the data bus or the control signals further comprise appropriate signals used to indicate to the system memory 130 that this is an in-memory opcode upon which the system memory 130 operates.
  • the processor 102 knows, via the control line 202 indicating the presence of the arithmetic-capable memory that this opcode will be processed by the arithmetic-capable system memory 130. If the control line 202 indicates that the system memory is not arithmetic-capable memory the processor 102 microcode executes the instruction in the normal manner.
  • the processor 102 interprets the STANDARD opcode "NEG" and instead of going through the read-modify-write cycle (which is triggered by the opcode and executed in microcode in the processor 102) , the processor 102 instead passes the "NEG" opcode onto the data bus and sets the control lines associated with the use of the in-memory architecture to a state that the memory interprets as "act on the instruction opcode on your data bus" .
  • This embodiment is particularly advantageous because existing compiled executables will run unaltered. As described above for the second embodiment, if the system memory 130 is not arithmetic-capable, the processor 102 executes the instruction in the normal manner.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

A computer memory has a simple Arithmetic Logic Unit (ALU) associated therewith. The ALU is used to perform simple arithmetic operations such as bit left shifts, bit right shifts, increment, decrement, integer addition, integer subtraction, integer negation, integer division and integer multiplication. Instructions are recognised by which may be performed by the ALU associated with the memory, rather than by the central processing unit itself.

Description

IN-MEMQRY ARITHMETIC
Field of the Invention
The present invention relates to memory subsystems and in particular to memory subsystems which perform simple operations on data stored within the memory subsystems in response to instructions.
Background of the Invention
Conventionally, simple operations on data in memory have been performed by the central processing unit (CPU) reading the data from memory, performing the operation on the data and writing the data back to memory. Using a central processing unit in this way has the disadvantage that the data transfers to and from memory are slow and that such operations when being done by the CPU prevent the CPU from processing other more complex instructions. With the increasing size of main memories associated with CPUs, and with multiple processors sharing a common bus, time on the processor bus to access memory is becoming a more and more scarce resource.
It would be desirable to move some of the main CPU (or multiple CPUs) processing load for simple arithmetic operations away from the main CPU and to the memory subsystems .
Prior art approaches to this problem include the use of SGRAM in graphics systems. In these systems, a bus controller decodes particular opcodes and sends instructions to SGRAM memory requesting it to perform certain operations on data stored in the SGRAM memory.
Another prior art approach to this problem is to use shared memory between the processor and a graphics adapter in which the graphics adapter performs operations on the memory. The graphics adapter can have a processor which is optimised for typical graphics operations and so can perform such operations at a higher speed than the CPU. However, the graphics adapter has to access the memory over the system bus and so access time to that bus is still required.
US Patent 4,569,016 discloses a mechanism for performing a ring shift of data under control of a mask. The mechanism disclosed is contained within a CPU and the data must first be transferred from the memory subsystem to the CPU before the operation on the data may be carried out.
US Patent 6,061,783 discloses a packet processor for performing specific bit manipulation tasks. The packet processor has a dedicated instruction memory which it reads in order to perform the bit manipulation tasks . The memory is loaded by means of a slow interface from the main processor. Main processor instructions are not stored in the instruction memory .
Disclosure of the Invention
Accordingly, the present invention provides a method for performing simple arithmetic operations in a computer memory, the method comprising the steps of providing a computer system having a central processing unit;
providing a computer memory for storing data therein; providing an Arithmetic Logic Unit (ALU) associated with said computer memory; identifying instructions intended for the central processing unit which may be completed by the ALU associated with the computer memory; and executing the identified instructions within the ALU associated with the computer memory.
Providing an Arithmetic Logic Unit associated with a computer memory means that the transfer of data from memory to CPU and return of that data back to the memory is avoided where the operation to be performed on the data is merely a simple arithmetic or logical operation. Such transfers take up a considerable amount of bus time and consequently slow the operation of a system. Having such simple arithmetic or logical operations performed within a memory improves performance of the system.
Preferably, the instructions identified include bit left shifts, bit right shifts, increment, decrement, negation, integer addition, integer subtraction, integer negation, integer division and integer multiplication.
In a first embodiment of the invention, when one of said instructions capable of being completed by said ALU is identified, a process is initiated by the central processing unit which causes the ALU to execute the instruction asynchronously to the main processor. In a second embodiment of the invention, the instructions which may be completed by said ALU are identified by virtue of belonging to a pre-defined subset of opcodes.
In a third embodiment, the method further comprises the steps of indicating to said CPU that said computer memory has an ALU associated with it; and the CPU instructing said memory to execute the identified instruction.
The present invention also provides a computer memory comprising a plurality of storage locations, each location being capable of storing data; an Arithmetic Logic Unit (ALU) , capable of performing simple arithmetic operations on data stored in one or more of the plurality of storage locations; and wherein the ALU executes instructions intended for a central processing unit, but which are identified as being able to be completed by the ALU associated with the computer memory.
Brief Description of the Drawings
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a simple prior art Advanced Graphics Port (AGP) system where the graphics processor and system processor share memory, the shared memory containing textures for use by the graphics system; and
Figure 2 is a block diagram of an in-memory ALU of the present invention.
Detailed Description of the Invention
Many simple arithmetic operations may be performed on single variable data stored in memory without requiring the processing power of the main system central processing unit. Examples of such operations include the shifting left of bits of data so as to divide by 2, 4, 8, 16 and the like and the shifting right of bits of data so as to multiply by 2, 4, 8, 16 and the like as well as inversion (negation) of each of the bits making up the data so as to multiply or divide by -1, and also incrementing and decrementing the data.
The following are examples of single variable (monadic) data operations : Data Operation Result
5Eh (01011110b) Divide by 2 (shift left 1 bit) 00101111b (2Fh) 35h (00110101b) Divide by 4 (shift left 2 bits) 00001101b (ODh) 6Ah (01101010b) Divide by 8 (shift left 3 bits) 00001101b (ODh) F3h (11110011b) Divide by 16 (shift left 4 bits) 00001111b (OFh)
5Eh (01011110b) Multiply by 2 (shift right 1 bit) 10111100b (BCh)
35h (00110101b) Multiply by 4 (shift right 2 bits) 11010100b (D4h)
6Ah (01101010b) Multiply by 8 (shift right 3 bits) 01010000b (SOh)1
F3h (11110011b) Multiply by 16 (shift right 4 bits) OOllOOOOb (30h)2
1 3h carried forward to next digit
2 Fh carried forward to next digit
5Ah (01011010b) Multiply by -1 (inversion) 10100101b (A5h)
37h (00110111b) Increment 00111000b (38h) 48h (01001000b) Decrement 01000111b (47h)
Certain operations involving two variables may also be carried out in memory for simple data formats, for example, integer addition, subtraction, multiplication and division
The following are examples of double variable (dyadic) data operations :
Data Operation Result
3Ah (00111010b) Integer Addition 01010110b (56h) ICh (00011100b)
3Ah (00111010b) Integer Subtraction 00011110b (lEh) ICh (00011100b)
3Ah (00111010b) Integer Multiplication 01011000b (58h)3
ICh (00011100b)
3Ah (00111010b) Integer Division 00000010b (02h)
ICh (00011100b)
3 6h carried forward to next digit
Data formats such as floating point or Binary Coded decimal operations are not suitable for the present invention to be used. Nor are the common floating point routines such as trigonometrical, logarithmic, exponential and power functions (transcendental functions) .
It is known in compilers to attempt to optimise the executable code. An example is where an operation to divide an integer variable X by 32 is equivalent to shifting X by 5 bits to the right. Shifting X by 5 bits to the right is considerably quicker than an integer multiplication by 32. An extension to this optimisation is to optimise the executable code for the processing location, for example, main CPU, memory, graphics system and the like. The use of separate dedicated processors for specialised functions is well known, for example, using a graphics processor for OpenGL commands (rendering, shading, tiling and the like) . The present invention is the use of a dedicated processor for memory processing. A requirement that is met by first and third embodiments of the present invention is that code portability be maintained and that the code will run on systems with or without the additional processing means in the memory subsystem. A further requirement met by second and third embodiments of the present invention is that the additional overhead associated with portability should not exceed the performance gain achieved by implementing the invention. Both of these requirements may be handled in a first embodiment of the present invention in the same way as in the X86/X87 or 680X0 architectures where the use of a separate floating point unit was optional, the code running both on systems with and without a separate floating point processor. In a second embodiment of the present invention, dedicated instructions utilising the dedicated processor for memory processing are implemented. In a third embodiment, the main CPU identifies the presence of the dedicated processor in the memory and instructs it to execute instructions which it is capable of executing.
Memory chips are now made with extensive control hardware as well as the basic memory cells. The present invention proposes the addition of an Arithmetic Logic Unit (ALU) to such a memory chip. Such an addition requires very little die space since an ALU is a relatively simple device and may be implemented using a small number of transistors.
The difference in operation between today's method of, for example, incrementing a variable and using an in-memory technique is shown below. (The internal processing steps associated with address translation, bus timing and the like are omitted) . Today In-memory
Fetch variable from memory to a register Increment variable
Increment register
Put variable from register to memory
Another example of negating a data value illustrates the difference in operation between today's method and using an in-memory technique is shown below. (The internal processing steps associated with address translation, bus timing and the like are omitted) .
Today In-memory
Fetch variable from memory to a register Negate variable
Negate register
Put variable from register to memory
One of the problems experienced today is that the CPU clock speed can typically exceed the time required to fetch data from memory. Various techniques are used to overcome this - multi-level caches, speculative or out of order execution and so on. Thus, whilst performing the simple increment operation above, most of the time taken will be spent transferring the data between the memory & CPU. (It is realised that with some of the advanced architectures the read-ahead function may make the increment operation apparently execute in 0 or 1 clock cycle (s). However, this is a statistical result and is not ergodic . )
Figure 1 shows a prior art RAMBUS/SGRAM implementation 100 using the AGP architecture. Processor 102 comprises a level 2 cache 104 which communicates with the CPU core 106 at a data rate of 2Gb per second. Processor 102 communicates with core logic 110, which includes a memory controller at a data rate of 800Mb per second. The core logic 110 communicates with a PCI bus 120 having PCI slots 122 into which PCI cards 124 may be inserted. The core logic 110 also communicates with system memory 130 at a data rate of 800 Mb per second. The core logic 110 further communicates with graphics controller 140 through an AGP port at a data rate of 528 Mb per second. The graphics controller is connected to graphics memory 142 and provides output to a display 144.
Textures using for rendering a displayed image on display 144 are moved from system memory 130 through core logic 110 to the graphics controller 140. The system memory 130 may, for example, contain a
Read-Modify-Write instruction which exclusive-ors (XOR) a bit mask onto the contents of graphics memory 142 (SGRAM memory 142 also has a very simple ALU) . A bus controller in the core logic 110, after some overhead in being programmed by the processor 102, sends such commands through the graphics controller 140 to the SGRAM graphics memory 142 for execution.
Figure 2 shows an embodiment of the present invention. System memory 130 comprises a storage array 132 such as can be found in conventional system memory together with an ALU 134 implementing the present invention. The system memory 130 communicates with the core logic 110 by means of data 210 and address 212 buses and control 214 signals. The system memory 130 also communicates logically with the processor 102 via an "In-memory capable" signal 202 which indicates that the system memory 130 supports in-memory arithmetic. The logical communication is with the processor 102, but as the system memory 130 is only connected to the processor 102 through the core logic 110, the communication is physically through the core logic 110 to the processor 102.
Referring to figure 1, and using the example of a Motorola 68020 processor, consider the MC68020 instruction NEG (negate) . The operation performed is "(0 - Destination) -> Destination". This operation involves reading the data (which may be a byte (8 bits) , word (16 bits) , long word (32 bits) or (not implemented in the 68020 processor) ultra long word (64 bits)) from system memory 130 into a processor 102 register. The processor 102 register contents are then subtracted from zero and the result stored in the system memory 130 location from which the original data was read. This operation corresponds to the second example of comparisons between the prior art and the present invention described above .
In a first embodiment of the present invention, the memory subsystem has a set of opcodes which are decoded for the memory subsystem in a similar fashion to that used for a floating point coprocessor. The opcodes initiate processes to actually execute the instruction which run in parallel to the CPU processing opcodes. The CPU polls the memory subsystem for completion at some suitable point in the code. Using the example of a Motorola 68020 processor, three control bits are provided to interface coprocessors. An example of such a coprocessor is the Motorola MC68881 maths coprocessor, which has special hardware to accelerate floating point operations. The Motorola 68020 coprocessor interface is fully explained in the User's Manual, ISBN-0-13-566860-3 or ISBN-0-13-566878-3. An important feature of this interface is that operation of the coprocessor is undertaken in hardware; the operation is transparent to the programmer, thereby enabling the implementation of various functions without appearing as external hardware to the main processor. This means that, by the use of an exception handling mechanism, programs compiled to make use of, for example, floating point instructions will operate without recompilation regardless of the presence of the coprocessor.
A disadvantage of the first embodiment of the present invention is that the clock cycle overhead associated with exception generation/handling is high. This problem is overcome in the second embodiment of the present invention in which a new instruction is defined in the microprocessor command set (and hence the compiler) and in the third embodiment of the present invention in which a different signalling scheme between the CPU and memory are implemented.
In a second embodiment of the present invention, the processor 102 opcodes are extended, in this case to include an MNEG (memory negate) opcode. The new operation involves the processor 102 accessing the data location (s) in the system memory 130 in the normal manner, but instead of reading the data on the processor data bus, the data bus presents the opcode corresponding to the MNEG instruction. The data bus or the control signals further comprise appropriate signals used to indicate to the system memory 130 that this is an in-memory opcode upon which the system memory 130 operates. The processor 102 knows, via the control line 202 indicating the presence of the arithmetic-capable memory that this opcode will be processed by the arithmetic-capable system memory 130. If the control line 202 indicates that the system memory is not arithmetic-capable memory the processor 102 microcode executes the instruction in the normal manner.
In a third preferred embodiment, in response to a positive indication on the "in-memory arithmetic-capable" control line 202, the processor 102 interprets the STANDARD opcode "NEG" and instead of going through the read-modify-write cycle (which is triggered by the opcode and executed in microcode in the processor 102) , the processor 102 instead passes the "NEG" opcode onto the data bus and sets the control lines associated with the use of the in-memory architecture to a state that the memory interprets as "act on the instruction opcode on your data bus" . This embodiment is particularly advantageous because existing compiled executables will run unaltered. As described above for the second embodiment, if the system memory 130 is not arithmetic-capable, the processor 102 executes the instruction in the normal manner.

Claims

1. A method for performing simple arithmetic operations in a computer memory, the method comprising the steps of: providing a computer system having a central processing unit; providing a computer memory for storing data therein; providing an Arithmetic Logic Unit (ALU) associated with said computer memory; identifying instructions intended for the central processing unit which are capable of being completed by the ALU associated with the computer memory; and executing the identified instructions within the ALU associated with the computer memory.
2. A method as claimed in claim 1 wherein the instructions identified include bit left shifts, bit right shifts, increment, decrement, integer addition, integer subtraction, integer negation, integer division and integer multiplication.
3. A method as claimed in claim 1 wherein when one of said instructions capable of being completed by said ALU is identified, a process is initiated by the central processing unit which causes the ALU to execute the instruction asynchronously to the main processor.
4. A method as claimed in claim 1 wherein said instructions which may be completed by said ALU are identified by virtue of belonging to a pre-defined subset of opcodes.
5. A method as claimed in claim 1 further comprising the steps of: indicating to said CPU that said computer memory has an ALU associated with it; and the CPU instructing said memory to execute the identified instruction.
6. A computer memory comprising: a plurality of storage locations, each location being capable of storing data; an Arithmetic Logic Unit (ALU) , capable of performing simple arithmetic operations on data stored in one or more of the plurality of storage locations; and wherein the ALU executes instructions intended for a central processing unit, but which are identified as being able to be completed by the ALU associated with the computer memory.
7. A computer memory as claimed in claim 6 wherein the instructions identified include bit left shifts, bit right shifts, increment, decrement, integer addition, integer subtraction, integer negation, integer division and integer multiplication.
8. A computer memory as claimed in claim 6 further comprising means to identify to said central processing unit that said computer memory comprises an ALU.
EP02720126A 2001-10-26 2002-03-25 In-memory arithmetic Withdrawn EP1472615A2 (en)

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GB0125711A GB0125711D0 (en) 2001-10-26 2001-10-26 In-memory arithmetic
PCT/GB2002/001417 WO2003036461A2 (en) 2001-10-26 2002-03-25 In-memory arithmetic

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