Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
  • G06F3/0604—Improving or facilitating administration, e.g. storage management
  • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
  • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
  • G06F3/0661—Format or protocol conversion arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
  • G06F3/0671—In-line storage system
  • G06F3/0683—Plurality of storage devices
  • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Definitions

• the present invention relates to computer systems, in particular to multiprocessor systems, for example multiprocessor server systems.
• One application for the present invention relates to high density computer systems, for example, computer server systems for telecommunications applications.
• high density computer systems for example, computer server systems for telecommunications applications.
• Various approaches have been taken to providing such high- performance, high reliability systems.
• Typically such systems are designed around providing redundant resources so that if one component of the system develops a fault, the system remains operational using the redundant resources.
• Fault tolerance can also be achieved, for example, with multiprocessor systems that provide redundancy through dynamic, e.g., software-controlled, task distribution.
• High density systems are typically rack mountable, with one or more processor systems occupying a shelf in the rack. The trend in recent times is to make the computers with smaller form factors. This means that more computers can be located in a rack. This has the advantage of increasing the processing density within the racks, and also the advantage of reducing the distance between the computer systems.
• the present invention relates to the provision of data storage in a higher density computer system.
• An aspect of the present invention can provide a computer system comprising at least one information processing module including at least one module information connection for communicating information signals.
• At least one switch module can include at least one internal switch information connection for communicating information signals, at least one external switch information connection for connection to an external information network and at least one external storage connection for connection to external storage under an external storage channel format.
• a carrier can include an interconnection member for interconnecting the module information connection and the internal switch information connection.
• the switch module can include a protocol converter operable to convert between information packets comprising packet format storage data and signals in the external storage channel format.
• the information processing module can include a packet format storage protocol driver operable to communicate information packets containing storage data in packet format with the protocol converter.
• An embodiment of the invention can thus enable external storage to be provided in a modular system with a minimum of internal connections and without impacting bandwidth on external network connections.
• two removably mounted switch modules can be provided in the carrier.
• the information processing modules can also be removably receivable within the carrier.
• Each switch module can be operable selectively to connect each received information processing module to the external information network. Redundant information connections can be provided to increase reliability.
• the information connections can be, for example, Ethernet connections, or Infiniband connections.
• Information can be passed over the information connections using Internet Protocol packets.
• the packet format storage data can be in internet Small Computer Systems Interface (iSCSI).
• the external storage channel format can be Fiber Channel format.
• the protocol converter can be implemented using computer software operable on a processor in the switch module. The use of a structure of this type enables the connection of direct-attached storage (DAS) and or connection to a storage area network (SAN) via Fiber Channel.
• DAS direct-attached storage
• SAN storage area network
• the information processing modules can include respective service controllers.
• the switch module can also include a service processor, the service processor being connectable to the service controller of the information processing modules via respective management signal connections over the interconnection member.
• the carrier can be a rack mountable shelf and the information processing modules can be server blades.
• Another aspect of the invention can provide a server blade including at least one processor, memory and at least one blade information connection for communicating information signals.
• a storage interface can be operable to communicate storage data to and from external storage via the information connection.
• a further aspect of the invention can provide a switch module for a carrier that is operable to receive at least one information processing module.
• the switch module can include at least one internal switch information connection for communicating information signals with each information processing module, at least one external switch information connection for connection to an external information network and at least one external storage connection for connection to external storage under an external storage channel format.
• the switch module can include a protocol converter operable to convert between information packets comprising packet format storage data received from an information processing module and signals in the external storage channel format.
• Figure 1 is a schematic representation of an architecture of a multiprocessor system for supporting a web site
• Figure 2 is a schematic representation of a racking system incorporating an example of a carrier in the form of a rack-mountable shelf according to a first example
• Figure 3 is a front view of an example of a carrier in the form of a shelf of Figure 2;
• Figure 4 is a rear view of an example of the shelf of Figure 2;
• Figure 5 is a schematic perspective view, partly from the rear, of an example of an information processing cartridge for mounting in the shelf of Figure 2;
• Figure 6 is a schematic perspective view of an example of a combined switch and service processor module for mounting in the shelf of Figure 2;
• Figure 7 is a schematic perspective view of an example of a power supply module for mounting in the shelf of Figure 2;
• Figures 8 A, 8B and 8 C are a schematic plan view and schematic perspective views, respectively, of an example of the chassis and midplane of the shelf of Figure
• Figures 9A, 9B and 9C are schematic front, top and rear views, respectively, of an example of a midplane of the shelf of Figure 2;
• Figure 10 is a schematic cross section view through the shelf of Figure 2;
• FIG 11 is a functional block diagram of an example of an information processing subsystem for the information processing cartridge of Figure 5;
• Figure 12 is a functional block diagram of an example of an information processing subsystem for the combined switch and service processor module of Figure 6;
• Figure 13 is a functional block diagram of an example of a subsystem for the power supply unit of Figure 7;
• Figure 14 is a functional block diagram showing the connectivity between the components of the shelf of Figure 2;
• Figure 15 is a functional block diagram showing the external connectivity of the shelf of Figure 2;
• Figure 16 is a schematic representation of a shelf showing the external connections from the shelf of Figure 2;
• Figure 17 is a schematic representation of a rack mounted system comprising a plurality of such shelves;
• Figure 18 is a functional block diagram of a further example of an information processing subsystem for the information processing cartridge of Figure 5;
• FIG. 19 is a functional block diagram of an example of combined switch and service processor module subsystem according to the present invention.
• FIG. 20 is a functional block diagram of an information processing cartridge subsystem according to the present invention.
• Shown in Figure 1 is an example of an application of a high capacity multiserver system 1 for implementing a network-connected web site such as, for example, an airline reservation system on the World Wide Web.
• a network-connected web site such as, for example, an airline reservation system on the World Wide Web.
• an external network 3 e.g., the Internet
• gateways 7 which can be connected to an entry edge server group 9 implemented by a web farm as shown in Figure 1.
• the entry edge server group 9 forms an interface to the external network 3.
• the entry edge server group 9 can then be connected by switches 11 and a firewall 13 to a web edge server group 15 that can also be implemented as a web farm as shown in Figure 1.
• the web edge server group 15 can serve to cache web pages that are readily accessible to users 5 accessing the system 1 from the external network 3, for example for checking flight times, etc.
• the web edge server group can comprise a number of blade server (BS) shelves and a number of network addressable storage (NAS) shelves for storing critical data.
• BS blade server
• NAS network addressable storage
• the web edge server group 15 can be further connected by a further firewall 17 to a plurality of application servers 19, which can be responsible for, for example, processing flight reservations.
• the application servers 19 can then be connected via a further firewall 21 to computer systems 23, 25, for example, e- commerce services including financial services for receiving and processing payment for airline reservations.
• Multiprocessor server systems have many different applications and the present system is not limited to being applicable for use in only one or a limited number of such applications, rather multiprocessor server systems as described herein are operable for use in many different applications.
• a non-exhaustive list of such alternative applications includes: e-commerce web server systems; telecommunications network server systems; LAN application- and file- server systems and remote vehicle control systems.
• FIG. 2 there is shown a schematic perspective representation of a rack system 31 as viewed from the front including left and right front uprights 32 and 33 and left and right rear uprights 34 and 35.
• the uprights can be formed with apertures for receiving shelf fixings (e.g., screws, bolts, clips, etc., for mounting brackets, slides, rails, etc.).
• shelf fixings e.g., screws, bolts, clips, etc., for mounting brackets, slides, rails, etc.
• FIG. 2 Also shown in Figure 2 is an example of a blade server shelf 41 mounted in the rack system 31.
• the shelf 41 forms a carrier configured to carry a plurality of information processing cartridges 43 located side by side along the shelf.
• the shelf 41 is used herein in a conventional way to describe a structure that is mountable in rack system 31 and is configured to carry one or more components to form at least a part of a rack-mountable system.
• the shelf 41 is three-dimensional, having a height (H), width (W) and depth (D).
• one dimension hereinafter described as the height, H
• the depth, D, and the width, W is smaller than the other dimensions (hereinafter described as the depth, D, and the width, W) to facilitate mounting of the shelf in within the rack system 31.
• the width and depth are typically constrained by the dimensions of the racking system for which the shelf is designed, there is more freedom as regard the height, subject to taking account of any appropriate standards and packaging considerations.
• Each of the information processing cartridges contains at least one processor.
• Each information processing cartridge in the present example is operable as a server. In the described examples, the information processing cartridges are configured as robust enclosed modules.
• the information processing cartridges when aligned in the carrier shelf, look like rectangular slabs, or blades. Accordingly, an information processing cartridge can be described as a blade.
• the information processing cartridges 43 comprise information processing modules enclosed in an enclosure, or housing, so that the information processing modules have the form of cartridges. Also, as the information processing cartridges are to operate as computer servers in the example described in more detail presently, an information processing cartridge 43 can also be described as a server blade. Accordingly, in the context of this example, the terms module, cartridge and blade are used interchangeably.
• the illustrated example of a shelf 41 is configured to carry sixteen information processing cartridges 43, each of which is removably mountable in a respective aperture 45 in the front of shelf, whereby the information processing cartridges can be inserted into and removed from the front of the shelf 41 without removing the shelf 41 from the rack system 31.
• the shelf 41 comprises a three-dimensional, generally rectangular, enclosure, or housing, 47 that is suitable for mounting in generic racking systems including both 4-post and 2-post systems. It can be mounted on fixed rigid rack mounting ears and/or a simple slide/support system.
• the enclosure can be arranged with a height of up to about 130.5mm, a width of up to about 445 mm and a depth, including all hardware and fascias, but excluding cable management, of up to about 635mm, with the depth from the front-most point of a fascia to a rear I/O connector panel of a rear mounted Field Replaceable Unit (FRU) of about 610mm.
• FRU Field Replaceable Unit
• This example of a shelf 41 has a single enclosure, or housing, 47 that houses a number of modular units or subsystems, the majority of which are replaceable in the field and are therefore known as Field Replaceable Units (FRUs). These modular units include the information processing cartridges 43.
• FRUs Field Replaceable Units
• the shelf enclosure 47 can be fabricated from sheet material (e.g., from steel sheet) to form a chassis portion 49 that includes a base 51, two sides 53 and 55, a front 57 and a rear 59.
• the word "front” as used here is merely used as a label herein to refer to the face, or wall 57 of the enclosure that is located at the main access side of the rack system 31 in use when the shelf is mounted therein.
• the words “rear” and “side” are merely used as labels herein to refer to the faces, or walls 59, 53 and 55 that, in use, are located at those respective positions when the shelf is mounted in the rack system 31.
• the apertures 45 can be formed in the front face 57 for receiving the information processing cartridges 43 and, as will be explained later, apertures can also be formed in the rear face 59 for receiving further FRUs.
• the enclosure can further include a removable top cover 61 that can be secured to the chassis portion 49 by suitable fastening (e.g., screws).
• the apertures in the front and rear faces 57 and 59 allow at least some of the FRUs to be inserted into and/or removed from the shelf enclosure 47 via the front or the rear thereof, as appropriate, without removing the shelf from the racking. Access to components mounted in the shelf that are not accessible via one of the apertures in the front 47 and rear 59 faces can be achieved by removing the shelf enclosure 47 from the racking system 31 and then removing the top cover 61 of the shelf enclosure 47.
• FIG 3 is a front view of an example of a shelf 41 for a first example.
• a plastic front bezel 63 can be provided that fits on the front face 57 (shown in Figure 2) of the chassis 49 of the shelf enclosure 47.
• the front bezel 63 can be formed as a unitary removable part that spans the whole width and height of the front of the shelf enclosure 47.
• the front bezel can include a peripheral portion 64 that can provide
• One or more apertures 65 can be formed in the peripheral portion 64 of the bezel 63.
• the apertures 65 in the bezel can be arranged to align with one or more apertures (e.g. a slot (not shown in Figure 3) in the front face of the chassis. In use, air can pass
• a central area 67 of the front bezel 63 can be open allowing access to the apertures 45 in the front face
• LED indicators 69 can be mounted on a system indicator printed circuit board (not shown) behind a designated area of the bezel to
• a further system indicator board (also not shown) carrying LED indicators can be provided inside the shelf enclosure to be visible from the rear thereof.
• up to sixteen information processing cartridges 43 can be installed in respective apertures 45 in the front face 57 thereof. The number of information processing cartridges 43 actually installed in any installation is dependent upon the system configuration required. Various features relating to the information processing cartridges 43 that are shown in Figure 3 will be described later.
• Figure 4 illustrates the rear of the shelf unit of Figures 2 and 3. This shows two different types of FRU 71 and 81 (4 units in total) that have been inserted into respective apertures 72 and 82 in the rear of the shelf enclosure 47.
• the FRUs shown in Figure 4 include two Combined Switch and Service Processors (CSSPs) 71 and two Power Supply Units (PSUs) 81.
• CSSPs Combined Switch and Service Processors
• PSUs Power Supply Units
• Figure 5 provides a perspective view, partly from the rear, of an information processing cartridge 43.
• the term “rear” is applied in the context of the position, when installed, of the information processing cartridge, with respect to the shelf 41 (i.e. in this case the "rear” of the information processing cartridge 43 is innermost part of the information processing cartridge when it is inserted in the shelf 41).
• information processing cartridges are three-dimensional, having a height (h), width (w) and depth (d). If, as in the present example, the information processing cartridges are to be arranged in a one-dimensional array (a row) across the shelf, then efficient packing for the information processing cartridges is achieved where one dimension (here the width, w) is smaller than the other dimensions (here the depth, d, and the height, h).
• an enclosure 101 of the present example of an information processing cartridge 43 has six, generally rectangular, faces.
• the face that is visible from the front of the racking when an information processing cartridge 43 is mounted in the shelf 41 is known as the front face 102.
• the opposite face is known as the rear face 103.
• these two faces, as well as top and bottom faces 104 and 105 have the shape of elongate rectangles.
• the side faces 106 and 107 are also rectangular, but not elongate in the manner of the front, rear, top and bottom faces.
• the information processing cartridges have six generally rectangular faces
• the side faces of another example of an information processing cartridge could have the general shape of a triangle (whereby the information processing cartridge may then only have five faces), a pentagon (whereby the information processing cartridge may then have seven faces), and so on. Indeed, one or more or all of the edges could be curved.
• the present configuration provides advantages for example, in terms of manufacturing, engineering and packing density within a shelf 41.
• the information processing cartridge enclosure 101 is fabricated from pressed steel to form two chassis portions.
• the first portion 109 includes one side face 107, the part of each of the front and rear faces 102 and 103 and the top and bottom faces 104 and 105.
• the second portion 110 includes the other side face 108 and the remaining part of each of the front and rear faces 102 and 103 and the top and bottom faces 104 and 105.
• the two chassis portions 109 and 110 meet at a groove 108 and are secured to one another by fixings (e.g., one or more screws, not shown).
• the groove 108 runs along the top and bottom faces 104 and 105 of the enclosure 101 and are provided for interfacing with guide rails of the shelf chassis 49 (not shown in Figure 5, but see Figure 8C).
• a cover portion that is secured to the chassis portion forms the other side face 106.
• the chassis portions could be joined at a position other than the groove 108, with the groove 108 being formed entirely in one of the chassis portions.
• the enclosure 101 may be constructed from a number of sheets of steel, with each sheet forming one of the faces.
• the provision of the enclosure means 101 that the information processing cartridge 43 can safely be handled by an operator who is not a skilled technician.
• the information processing cartridge is a robust unit that protects its inner workings from the outside environment and vice versa.
• the use of a conductive enclosure, e.g., a metal enclosure means that the information processing cartridge includes its own electromagnetic shielding.
• the enclosure 101 is also provided with electromagnetic interference (EMI) fingers 114 to ensure good contact with the shelf chassis and the adjacent components.
• EMI electromagnetic interference
• the information processing cartridge 43 incorporates an injector/ejector handle 111 on the front face 102, with an associated latch mechanism 113 shown in Figure 5 for facilitating insertion and latching of the information processing cartridge 43 within an aperture in the shelf 41.
• the handle 111 of the injector/ejector lever extends substantially the whole height of the front face of the information processing cartridge 43, thereby increasing the mechanical advantage and facilitating injection and ejection of the information processing cartridge 43.
• the front face 102 of the information processing cartridge 43 has perforations 115, in the present example slits, to allow for airflow into the information processing cartridge 43. It will be noted in Figure 3 that the handle 111 is narrower I its middle than at its ends.
• the handle 111 can be bowed out from the front face of the information processing cartridge to further facilitate grasping thereof and to reduce any masking effect with regard to the perforations.
• the handle 111 could have an open frame-like structure to further facilitate airflow.
• the rear face 103 of the information processing cartridge 43 also has perforations 117 to allow for air to be exhausted from the rear of the information processing cartridge 43.
• a fan can be located within the enclosure 101 of an information processing cartridge 43.
• the fan is an impingement fan to direct cooling air onto a processor of the information processing cartridge, which fan also encourages air movement within the enclosure 101.
• LED indicators 119 can be provided on the front face 102 of an information processing cartridge to indicate whether power is on, whether service intervention is required and whether the information processing cartridge 43 can be removed.
• a connector 120 for example a 40 way single connector attach (SCA-2) connector, can be provided at the rear of the information processing cartridge 43 for electrical connection of the information processing cartridge 43 within the shelf 41.
• the connector 120 is advantageously able to withstand repeated removals and insertions of the enclosure 101 from and into a shelf 41.
• the connector arrangement can include a guide pin arrangement to prevent module misalignment during insertion of the information processing cartridge into the receiving location.
• Figure 6 provides a perspective view, partly from the front, of a Combined
• CSSP Shelf and Service Processor
• the face that is visible from the rear of the racking when a CSSP cartridge 71 is mounted in the shelf 41 is known as the rear face 122.
• the opposite face is known as the front face 123.
• these two faces, as well as side faces 126 and 127 have the shape of elongate rectangles.
• the top and bottom faces 124 and 125 are also rectangular, but not elongate in the manner of the front, rear, top and bottom faces.
• the CSSP cartridges have six generally rectangular faces, as for the information processing cartridges 43 it will be appreciated that other examples could have other configurations.
• the CSSP cartridge enclosure 121 is fabricated from steel sheet to form a chassis portion that includes the bottom face 125, the front and rear faces 122 and 123 and the side faces 126 and 127.
• a cover portion that is secured to the chassis portion forms the other top face 124.
• the cover portion is secured to the chassis portion by suitable fixings, for example one or more screws 128. It will be appreciated however, that in another example, other faces, or portions, of the enclosure could form the chassis and the cover portions.
• the provision of the enclosure 121 means that the CSSP cartridge 71 can safely be handled by an operator who is not a skilled technician. Also, through the use of the enclosure 121, the switch cartridge is a robust unit that protects its inner workings from the outside environment and vice versa.
• the CSSP cartridge 71 incorporates two D-shaped handles 132 to facilitate insertion and removal of the CSSP cartridge 71 with respect to an aperture 72 in the rear face of the shelf enclosure.
• a latch member 131 can be pivotably mounted on a plate that can be secured (e.g., using screws) to the rear face of the shelf enclosure. The latch member 131 is configured to engage one of the handles 132 and to secure the CSSP 71 in place.
• the CSSP 71 could be provided with an injector/ejector handle in a manner similar to the information processing cartridge.
• the front face 123 of the CSSP cartridge 71 has perforations 133 to allow for airflow into the CSSP cartridge 71.
• the rear face 122 of the CSSP cartridge 71 has perforations 135 to allow for air to be exhausted from the rear of the CSSP cartridge 71.
• At least one fan can be located, for example behind the perforated portion 135 of the rear face, in a CSSP cartridge 71 to channel cooling air through the CSSP cartridge 71 from the front to the rear.
• two fans are provided, one behind each set of perforations 135.
• LED indicators 137 can be provided on the rear face 122 of the CSSP enclosure 121 to indicate whether power is on, whether service intervention is required and whether the switch can be removed.
• Additional link status indicators can be provided integral to 2x4 stacked RJ-45 connectors 139, also shown in Figure 4.
• electrical connections 141 can be provided at the front face of the CSSP (i.e. on the face that in use is inside the shelf enclosure 47).
• Suitable connections for use in the present example include a connector for power connections, a connector for serial management data connections and a connector for information connections.
• information connections are implemented using an Ethernet information communication protocol, e.g. at 1 Gigabit (Gb).
• Gb Gigabit
• the connector arrangement can include a guide pin arrangement to prevent module misalignment during insertion of the CSSP cartridge module into the receiving location.
• guide pin holes 142 can be provided on the front face 123 into which guide pins may pass to aid module alignment.
• up to two CSSPs 71 can be mounted at any one time at the rear of the shelf unit in corresponding apertures 72 in the rear face of the shelf enclosure 47.
• the number of CSSPs 71 provided in any particular implementation depends upon system configuration and the need, or otherwise, for redundancy.
• FIG. 7 provides a perspective view, partly from the front, of a power supply unit (PSU) cartridge 81.
• PSU power supply unit
• PSU cartridge 81 is three-dimensional, having a height (h), width (w) and depth (d).
• the PSU cartridge 81 has two dimensions (hereinafter described as the width, w, and the depth, d) that are generally similar.
• An enclosure 145 of present example of a PSU cartridge 81 is of generally oblong shape, but has the "top" "front” edge cut away to form an additional "top” "front” sloping face. The enclosure 145 therefore has five, generally rectangular, faces and two faces of generally rectangular shape with one corner cut away.
• the face that is visible from the rear of the racking when the PSU cartridge 81 is mounted in the shelf 41 is known as the rear face 146.
• the opposite face is known as the front face 147.
• these two faces and the two side faces 150, 151 are of elongate generally rectangular shape with one corner cut away, given that the width and depth of the PSU cartridge are similar, whereas the top and bottom faces 148, 149, although still rectangular, are not, in this example, notably elongate.
• a top front face 148a is present at the top front of the enclosure.
• the front of the enclosure is sloped at the top edge.
• the information processing cartridges 43 it will be appreciated that other examples could have other configurations.
• the PSU cartridge enclosure 145 is fabricated from steel sheet to form a housing portion that includes the bottom face 149, the side faces 150 and 151 and the front and rear faces 146 and 147. Cover portions that are secured to the housing portion form the top face 148 and top front face 148a. The cover portions are secured to the chassis portion by suitable fixings, for example one or more screws
• the enclosure 145 means that the PSU cartridge 81 can safely be handled by an operator who is not a skilled technician. Also, through the use of the enclosure 145, the PSU cartridge 81 is a robust unit that protects its inner workings from the outside
• a conductive enclosure e.g., a metal enclosure
• the PSU cartridge includes its own electromagnetic shielding.
• the PSU enclosure 145 is provided with EMI fingers 153 to ensure good contact with the shelf chassis and the adjacent components.
• the PSU cartridge 81 incorporates two D-shaped handles 156 to facilitate insertion and removal of the PSU cartridge 81 with respect to an aperture 82 in the rear face of the shelf enclosure.
• a latch member 155 can be pivotably mounted on a plate that can be secured (e.g., using screws) to the rear face of the shelf enclosure. The latch member 155 is configured to engage one of the 5 handles 156 and to secure the PSU 81 in place.
• the PSU 81 could be provided with an injector/ejector handle in a manner similar to the information processing cartridge.
• the front face 147 of the PSU cartridge 81 has perforations 157 to allow for airflow into the PSU cartridge 81.
• the rear face 146 of the PSU cartridge 81 also has perforations 159 to allow for air to be exhausted from the rear of the PSU cartridge 81.
• a pair of fans can be located behind the perforated portions 159 of the rear face of a PSU cartridge 81 to channel cooling air through the PSU cartridge from the front to the rear.
• LED indicators 161 can be provided on the rear face 146 of the PSU enclosure 81 to indicate whether input power is good, whether output power is good, whether service intervention is required and whether the PSU can be removed.
• Electrical connectors 163 can be provided at the front face of the PSU (i.e. on the face that in use is inside the shelf enclosure 47) for connection to the shelf.
• the PSU 81 of the present example may suitably employ an SSI-MPS (Server Systems Interface - Midrange Power Supply) compliant right angle connector at the front face 147 of the PSU 81 to connect to the shelf 41.
• the power inlet 83 for each PSU 81 can incorporate a cable/connector retention mechanism (not shown) on the rear face 146 of the PSU to prevent accidental or malicious removal of the power input cord from the PSU 81.
• blanking panels/modules e.g., the blanking panels 44 shown in Figure 3
• EMC electromagnetic compliance
• ESD electrostatic discharge
• each of the FRUs such as the information processing cartridges 43, is advantageously contained in its own robust enclosure to facilitate EMC containment, ESD containment, handling, storage and transportation.
• Each FRU can be configured as a 'sealed' unit in the sense that it can be configured not to have field or customer serviceable parts internally.
• the FRUs can be configured readily to plug into the shelf enclosure and to be hot swappable.
• the FRUs can be keyed to prevent incorrect positioning and insertion into the shelf enclosure and are arranged positively to be retained in the shelf by a latching/locking mechanism.
• FRUs described above are not provided with removable media.
• internal data storage is provided by 2.5" IDE 9.5mm or 12.7mm profile hard disk drive (HDD) devices mounted internally in each information processing cartridge 43 and in the CSSP cartridge 71.
• the drives are not considered as FRUs and are not hot-swappable disk drives in the present example, although they could be in other examples.
• the information processing cartridges can be configured without internal hard disk drives.
• Figure 8A is a schematic plan view showing the internal configuration of an example of a shelf 41 with the cover 61 removed.
• Figure 8B is a schematic perspective view from above the rear of the chassis portion 47 of the shelf enclosure with the field replaceable units removed.
• Figure 8C is a schematic perspective view from below the front of the chassis portion 47 of the shelf enclosure with the field replaceable units and the base 51 removed.
• Figures 9A, 9B and 9C are, respectively, front, top and rear views of the midplane 171.
• the midplane is, in use, mounted vertically within the shelf 41 extending across the width W of the shelf 41 at a position approximately halfway between the front and the rear of the shelf 41.
• the vertically mounted midplane 171 extends, in this example, across the shelf 41 and allows for the electrical interconnection of the FRUs.
• the various apertures in the front and rear faces 57 and 59 of the shelf 41, in combination with the midplane 171, can be provided with guides (e.g., rails 181) and keying e.g., offset connector positioning for the insertion of the FRUs into the enclosure and midplane 171.
• the midplane 171 can be a double-sided, or multi-layer printed circuit board (PCB) assembly that can be mounted vertically in a rigid manner within the enclosure. It can carry connectors 175 on a front surface 172 for making electrical connection with corresponding connectors 120 on the information processing cartridges 43.
• PCB printed circuit board
• the midplane 171 can also carry connectors 177 and 179 on rear surface 173 for making electrical connection with corresponding connectors 141 and 163 on the CSSPs 71 and the PSUs 81, respectively.
• Conductive tracks (not shown) on and through the midplane 171 can be provided to interconnect the various connectors.
• the midplane can provide connectors for receiving corresponding connectors connected to first and second indicator boards 183 and 184 that each carry a respective set of LED indicators 69.
• the midplane 171 is not configured as a FRU and is not hot swappable. It is perforated to facilitate airflow through the shelf 41.
• the midplane 171 can include openings 185, which cooperate with openings in the enclosures of the FRUs 43, 71 and 81, to provide a path for cooling air to pass from the front to the rear of the shelf 41, the cooling air being forced through by fans in at least selected ones of the FRUs, for example in the CSSPs 71 and the PSUs 81, possibly also in the information processing cartridges 43.
• a plenum chamber floor member 94 can extend horizontally from the front of the midplane 171 to the front face 57 of the shelf enclosure, or chassis 47.
• the member 94 provides a floor for a plenum chamber 66, which is supplied with air via the apertures 65 in the front bezel and, in the illustrated example, the slot shaped aperture 68 in the front face 57 of the shelf enclosure 47.
• the top and sides of the plenum chamber are provided by the top cover 61 and side faces 53 and 54 of the shelf enclosure 47.
• a plurality of cartridge guide rails 98 can be provided at the underside of the plenum chamber floor member 94. These rails can be made from a material having a low coefficient of friction, such as polytetrafluoroethene (PTFE) or polythene. Each rail is advantageously positioned so as to interface with the groove 108 of each processing cartridge 43 to aid correct alignment and to facilitate insertion of the processing cartridge during insertion of the cartridge into the shelf 41.
• a further row of guide rails (not shown) can be provided in matching positions at the top surface of the base 51 of the shelf 41 such that alignment guide rails are present above and below the processing cartridges.
• a CSSP/PSU divider 96 can be provided to the rear of the midplane 171 and can extend horizontally to the rear face 59 of the shelf enclosure 47.
• the CSSPs 71 when inserted, are supported by the divider 96. To aid the correct insertion of the
• CSSPs 71, CSSP guide pins 178 are provided on the midplane 171 at positions adjacent connectors 177 on the midplane 171 for connection to the CSSPs 71.
• Respective positions 88 and 89 can be formed in the front face 57 and the rear face 59 at which first and second indicator boards 183 and 184 supporting the indicator LEDs 69 can be located. These positions 88, 89 therefore include an aperture through the respective face of the shelf enclosure 47 such that indicator LEDs 69 mounted onto a circuit board attached to the inside of the shelf enclosure 47 may be viewed from outside the shelf enclosure.
• the midplane 171 connects all the elements of a shelf together, including, in the present example, up to sixteen information processing cartridges 43, up to two CSSPs 71, two PSUs 81 and the two indicator boards 183 and 184.
• the midplane 171 due to its location within the shelf enclosure, the midplane 171 is not configured to be swappable. Accordingly, to maximize the system reliability, the midplane is configured to provide as a high level of reliability as possible. To this end, the midplane is advantageously configured without active devices and to include the minimum number of decoupling capacitors consistent with good design practice (ideally zero).
• the midplane supports a number of paths for various power and signal lines to interconnect the FRUs.
• each information processing cartridge 43 has a high speed information signal connection (e.g., a Gigabit (Gb) Ethernet SERialiser/DESerialiser (SERDES) connection) to each of the CSSPs 71, each connection consisting of two pairs of differential signals.
• a high speed information signal connection e.g., a Gigabit (Gb) Ethernet SERialiser/DESerialiser (SERDES) connection
• Gb Gigabit
• SERDES SERialiser/DESerialiser
• each information processing cartridge 43 has a serial console connection to the CSSP 71.
• Each connection consists of two TTL (Transistor-Transistor Logic) level signals that make a transmit and return (TX and RX) pair.
• TTL Transistor-Transistor Logic
• each PSU 81 has a management signal connection (e.g., a serial I2C (Inter-IC Bus) connection) to the CSSP 71 to control power and monitor environmental parameters.
• the I2C bus comprises of two signals SCL and SDA
• serial clock line and serial data line serial clock line and serial data line.
• I2C address programming pin is provided for the PSUs 81.
• Each information processing cartridge 43 and PSU 81 can signal to the CSSP
• a respective Inserted_L signal i.e., an active low signal.
• Each PSU 81 has five 12 Volt output rails. The routing from each PSU 81 is arranged so that a fault in any single FRU cannot completely interrupt the power to any other.
• the midplane 171 is provided with appropriate connector arrangements for receiving the connectors on the FRUs.
• the information processing cartridge 43 connects to the midplane 171 through a 40 pin Single Connector Attachment (SCA-2) connector as defined by the Small Computer Systems Interface (SCSI) standard. Accordingly, the midplane carries corresponding connectors 175.
• SCA-2 Single Connector Attachment
• SCSI Small Computer Systems Interface
• each CSSP 71 connects to the midplane 171 through a right-angle 40 pair connector.
• the corresponding connectors 177 on the midplane are straight male parts with a power connector.
• a guide pin arrangement is provided in addition to the connectors to prevent misaligned modules causing bent pins during insertion.
• a power module is used to provide connection between the power rails.
• the center pin is longer on the switch modules to provide a leading ground.
• the CSSP 71 also connects to the midplane 171 through a right-angled 125 way 5 row 2mm connector.
• the connector 177 on the midplane 171 includes a straight male part.
• a guide pin arrangement is provided in addition to the connectors to prevent misaligned modules causing bent pins during insertion.
• each PSU 81 connects to the midplane 171 through an SSI-MPS specification connector.
• the contacts are configured 5P/24S/6P with sequenced signal (S) and power (P) pins.
• the connector on the PSU is a 1450230-1 R/A male header, solder tails connector
• the mating connector 179 on the midplane can be a 1450540-2 vertical receptacle, press- fit connector.
• indicator boards 183 and 184 are provided at the front and rear of the system and are configured as FRUs.
• FRUs hold three system-level indicator LEDs 69 and include a FRU identity (FRU-ID) programmable read-only memory (PROM) each.
• FRU-ID FRU identity
• PROM programmable read-only memory
• Three LEDs 69 are present on the indicator board.
• These LEDs can be driven by the CSSP 71.
• identification information (FRU ID) for the midplane 171 is held on an I2C electrically erasable programmable read only memory (EEPROM) in the front indicator board 183.
• EEPROM electrically erasable programmable read only memory
• the CSSPs 71 provides a current limited supply to the indicator boards 183 and 184 via the midplane.
• the indicator boards 183 and 184 are also provided with an I2C address programming pin.
• FRU ID information can be stored instead, or in addition, on the rear indicator board 184.
• the midplane can be a totally passive unit.
• the FRU-ID PROMs communicate with the CSSPs 71 via an I2C bus. Each device on the bus has a separate I2C address.
• the lower three I2C address bits of the EEPROMs used are available as pins on the device, to allow programming with resistors.
• the least significant bit of this address (A0) is passed to the midplane via the corresponding connector. This allows the midplane 171 to program the address of the FRU-ID differently for the front and rear indicator boards 183 and 184, by pulling the address low for the front board and high for the rear indicator board 183.
• the FRU-ID for the midplane and for the other FRUs to be installed in the shelf can be stored on either front or rear EEPROM, but the CSSPs 71 are configured to use the EEPROM on the front indicator board 183 in the present embodiment.
• the EEPROM is at least 8kByte in size.
• the midplane 171 includes openings 185 to provide a ventilation path for cooling air passing through the shelf 41.
• the cooling air is forced through the shelf 41 by means of fans provided in each of the information processing cartridges 43, the CSSP modules 71 and the power supply modules 81.
• the openings 185 shown in Figures 8B, 9A, 9B and 9C form schematic representations of openings in the midplane 171.
• the openings could have any form (i.e., a series of large openings, or a number of small perforations), arranged on the midplane to align with corresponding openings or ventilation apertures in the various field replaceable units 43, 71 and 81.
• the path of the airflow from the front of the shelf to the back of the shelf can be configured to be as efficient as possible, depending on the detail configuration of the fan units and the ventilation openings or apertures in the information processing, switch, service processor and power supply unit modules 43, 71 and 81.
• Providing the fan units in the field replaceable units 43, 71 and 81 contributes to the aim of maintaining the chassis 49 and the midplane 171 of the shelf 41 free of active components, thereby minimising cost, and facilitating maintenance.
• by providing the fan units in each of the field replaceable units merely inserting and removing field replaceable units automatically adapts the flow of cooling air to the number and type of field replaceable units inserted in the shelf 41.
• each of the FRUs is designed to be a non-user serviceable unit.
• each FRU presents the user with a "sealed" unit which may be inserted into and removed from the shelf 41 as desired or required. If a
• FRU ceases to be operable, then the user has a choice only of returning the FRU to a supplier or service company for repair or of discarding the non-operable unit.
• FRUs are non-user serviceable, there is no requirement for a skilled technician to be employed in inserting or removing the FRUs into or from a shelf 41.
• each FRU is designed such that a non-skilled person should have difficulty in causing damage to the FRU during handling.
• the configuration and construction of the FRUs are non-user serviceable, there is no requirement for a skilled technician to be employed in inserting or removing the FRUs into or from a shelf 41.
• each FRU is designed such that a non-skilled person should have difficulty in causing damage to the FRU during handling.
• the configuration and construction of the FRUs are non-user serviceable, there is no requirement for a skilled technician to be employed in inserting or removing the FRUs into or from a shelf 41.
• the shelf enclosure contributes to facilitating easy insertion and removal of the FRUs.
• the midplane e.g., the guide rails to guide insertion of the FRUs, the locating pins, etc
• Shown in Figure 10 is an example the flow of cooling air through the shelf 41 and FRUs 43, 71, 81 mounted therein.
• the cooling air passing through the shelf 41 is drawn generally in a front to rear direction through the shelf 41 by cooling fans mounted within the CSSPs 71 and the PSUs 81.
• Two separate flow paths for cooling air are provided in this example.
• the first, indicated as flow path ⁇ by dotted lines 77 provides cooling air to the CSSPs 71.
• the second path, indicated as flow path ⁇ by dotted lines 78 provides cooling air to the information processing cartridges 43 and PSUs 81.
• the flow of cooling air along path ⁇ enters the shelf 41 through the elongate aperture 65 in the front face 57 of the shelf enclosure 47. This air then flows through the plenum chamber 66, and passes over the top edge of the midplane 171 to reach the perforations 133 of the front face of the CSSPs 71. The cooling air then passes through the CSSPs 71, providing cooling to the components thereof before passing out of the CSSPs 71 through the perforations 135 in the rear face of the CSSPs 71 thus being exhausted from the shelf 41.
• This flow of cooling air along flow path ⁇ is driven by fans 79 mounted within the CSSPs 71. In the present example, a pair of fans 79 is provided within each CSSP 71 and are mounted against the rear face thereof.
• Air flowing along path ⁇ is impeded from flowing around the processing cartridges 43 by plenum chamber floor member 94 and is impeded from flowing to the PSUs 81 by CSSP/PSU divider 96.
• This flow path ⁇ therefore ensures that air flowing to the CSSPs 71 is not warmed by passage though the processing cartridges 43 and therefore provides maximum efficiency cooling to the CSSPs 71.
• the flow of cooling air along path ⁇ enters the shelf 41 through the perforations 115 in the front face of the information processing cartridges 43.
• the air thus enters the information processing cartridges 43 and provides cooling to the components thereof.
• Cooling fans (not shown) within the information processing cartridges 43 direct the cooling air to the processor (CPU) of the information processing cartridge and directs the flow of air in the cartridge thereby increasing cooling efficiency.
• the air then exits the information processing cartridges 43 through the perforations 117 in the rear face thereof.
• the air then passes through the apertures 185 through the midplane 171 to reach the PSUs 81.
• This cooling air then passes though the perforations 157 on the front and upper front faces of the PSUs 81 to enter the PSUs and provide cooling to components thereof.
• the sloping rear of the upper face of the PSUs 81 increases the area over which air can be drawn into the PSUs, thereby reducing the back pressure on the air flowing through the shelf unit and aiding the cooling efficiency.
• the flow of cooling air along path ⁇ is driven by fans 85 mounted within the PSUs 81.
• a pair of fans 85 is provided within each PSU 81 and are mounted against the rear face thereof.
• Air reaching the PSUs 81 via path ⁇ will already have passed through the processing cartridges 43. Such air will therefore be already warmed above the ambient temperature outside of the shelf 41 by its passage through the processing cartridges 43.
• the cooling requirement of the PSUs 81 is typically less than that for the CSSPs 71, this does not cause any difficulty in the operation of the PSUs 81, which are adequately cooled by this flow of pre-warmed air.
• the pre- warmed air passing through the apertures 185 through the midplane 171 is impeded from flowing into path ⁇ and entering the CSSPs 71 by the SCCP/PSU divider 96.
• the information processing cartridge 43 includes a microprocessor 192 (a non- limiting example of a microprocessor that can be utilised in the present example is an UltraSPARCTM processor).
• the microprocessor is mounted on an information processing cartridge motherboard 191.
• a vectored interrupt controller (I-Chip) 194 and a configurable core voltage regulator module (NRM) 195 are provided.
• memory means for use by the processor 192 when executing instructions can be provided in the form of buffered dynamic random access memory (DRAM), for example configured as dual in line memory modules (DIMMs) 196 with a 72-bit data path with error correction codes (ECC), seated in two sockets on a riser card from the information processing cartridge motherboard 191.
• DRAM buffered dynamic random access memory
• DIMMs dual in line memory modules
• ECC error correction codes
• the memory capacity can be chosen to suit the processor addressable memory space. For example, in the present example, up to 4 Gigabytes (4GB) of addressable memory can be provided.
• Serial Presence Detect (SPD) auto-configuration is provided via a Service Management Bus (SMBus) over an I2C bus 197.
• SMBs Service Management Bus
• a PCI bus architecture can be employed with a so-called SouthBridge bus bridge 199 with SuperlO and two Gb Ethernet Media Access Control (MAC) devices. As described above, however, other bus protocols (e.g., Infiniband) can be used.
• a 32bit PCI bus 198 can be provided from the microprocessor 192.
• the SouthBridge 199 is a standard form of bus bridge, in the present example packaged in a 352 pin PBGA (Plastic Ball Grid Array) package, that provides the following functions: an SM Bus interface over the I2C bus 197 for access to the SPD (Serial Presence Detect) feature of the DIMMs that allows initialization of the memory controller; an Xbus interface for access via an Xbus 200 (which is a packet switched multiprocessor bus) to a PROM 201, a real time clock (RTC) 202 and an information processing cartridge service controller (hereinafter termed a Blade Service Controller (BSC)) 203; an IDE (Integrated Drive Electronics) interface that provides an ATA- 100 (AT Attachment) IDE connection 204 to an IDE disk drive 205; and a serial console interface on a service bus 206 to the BSC 203 that is used for operating system functions including a console function with this embodiment.
• PBGA Packet Transfer Bus
• two AC-coupled Ethernet interfaces 207 and 208 are provided in the present example, which are packaged in a 316 pin PBGA. These Ethernet interfaces can provide a PCI attached Ethernet MAC capable of operation up to Gigabit Ethernet performance.
• the physical layer can be implemented using SERialiser/DESerialisers (SERDESs) 209 and 210.
• SERDESs SERialiser/DESerialisers
• An example of a SERDES device is the TLK2201 transceiver manufactured by Texas Instruments, Inc.
• the SERDES devices use differential PECL TX+/- and RX+/- (Positive Emitter Coupled Logic Transmit and Receive) pairs to communicate to the switch portions of the CSSPs 71 over the midplane 171.
• the RX+/- pairs can be AC coupled at the information processing cartridge 43
• the TX+/- pairs can be AC coupled at each CSSP 71. This facilitates hot-swap of the information processing cartridges 43 and the
• BSC 203 and the Service Processor parts of the CSSPs 71 can be provided.
• Internal data storage can be provided in the present example by a hard disk 205 with a capacity of 30GB or more rated for 24/7 continuous operation.
• the hard disk 205 is accessed using the primary IDE interface of the SouthBridge 199.
• the hard disk 205 can hold an operating system, for example a Solaris operating system, and other software and data for performing information processing using the main, or host, processor (CPU) within the information processing cartridge 43.
• the BSC 203 can be implemented as a microcontroller (e.g., a Hitachi H8 microcontroller).
• the BSC 203 can provide various functions, including for example: dual access (for the information processing cartridges and the CSSPs 71) to PROM 201 and EEPROM 213 for boot information and a FRU-ID for the information processing cartridge; channelling communication between an information processing cartridge 43 and the service processor part of the CSSPs 71; control of power on reset (POR), system reset and externally initiated reset (XIR) to the microprocessor 192; control of the power, service-required and ready-to- remove LEDs 69; upgrading of field-upgradable firmware, via the serial interface; a watchdog function for the operating system; monitoring the speed of a CPU fan 214; and communications with an EEPROM 215 and the operating system via the Xbus 200.
• dual access for the information processing cartridges and the CSSPs 71
• PROM 201 and EEPROM 213 for boot information and a FRU-ID for the information processing cartridge
• FRU-ID for the information processing cartridge
• the BSC 203 can be powered by a 5N service bus (SB) rail as soon as a CSSP 71 and a PSU 81 are fully inserted into the midplane 171, it then turns on other DC/DC converters to provide power to the remainder of the information processing cartridge 43.
• a BSC reset signal can be derived from a simple conventional power on reset (POR) generator that monitors a 5V supply rail.
• a 1MByte Flash PROM 201 can be provided for storing boot variables for OpenBootTM PROM (OBP) and Power-On-Self-Test (POST). Further OBP variables can be stored in a second 16kByte (16kB) I2C PROM 215, accessible via the SouthBridge SM Bus port over the IC Bus 197.
• the PROM 215 can contain 8kByte for OBP variables and 8kByte of unused space.
• a 16kByte I2C EEPROM 213 that is accessible via the BSC 203 can contain BSC variables and FRU-ID variables.
• the EEPROM is nominally divided into 8kByte for FRU-ID and 8kByte for the BSC variables.
• Write protection for the FRU-ID is implemented by BSC firmware. Such write protection may be carried out by, for example, acknowledging instructions to write to the protected area, but not to carry out those write instructions.
• An environmental monitor sensor 215 can be provided to monitor the CPU and ambient temperatures. This sensor can be accessible via the onboard I2C bus from the BSC 203.
• the information processing cartridge 43 can be powered from two, diode commoned, 9V power supply rails 216 and 217.
• DC/DC converters 218 can be used to provide the voltage levels required by the information processing cartridge 43.
• the DC/DC converters 218 are supplied by dual 9V inputs 216, 217, individually fused 219, 220 and then diode commoned 221, 222.
• a 5V DC/DC converter can be turned on as soon as the FRU is fully inserted, with the BSC 203 and required portions of the SouthBridge 199 being powered (the 5VSB rail).
• a field effect transistor (FET) can be used to gate off the main 5V supply to the rest of the information processing cartridge 43.
• the DC/DC converter outputs and the main 5 V FET can be arranged not to turn on until the BSC 203 turns them on via a signal from the SouthBridge 199.
• the SouthBridge 199 can be used so that if the BSC 203 is reset (by a watchdog timeout or after a firmware download) the state of the DC/DC converters 218 is not affected.
• a PWR_GOOD signal can be asserted low to the BSC 203.
• a SouthBridge resume circuit can be operable to run from 3V3, and a simple Zener diode dropper circuit can be used to generate 3 V3 from the 5VSB supply.
• the inrush current can be limited, for example to ⁇ 1A, and the rate of rise can be configured not to exceed a predetermined value (e.g., 20A/s) to provide a so-called soft start to facilitate hot-insertion.
• a predetermined value e.g. 20A/s
• a soft start controller 223, which controls a ramping-up of voltage levels, can be enabled when the predetermined signal (Inserted_L signal) is asserted low, this signal is on a short pin in the connector and is connected to ground (GND - not shown) through the midplane 171.
• a processor impingement fan (processor fan) 214 is configured to run at full speed to cool the information processing cartridge 43 and the fan.
• the speed of the processor fan and sink can be monitored by the BSC 203, using a tachometer sense pin on the microcontroller. In the event of the fan speed falling below a predetermined speed, or percentage of its nominal speed (e.g., 80%), the BSC 203 can be arranged to issue an alert.
• the nominal speed of the fan can be recorded as part of the BSC EEPROM contents.
• the midplane connector 120 for the information processing cartridge 43 is used to establish the connection between the information processing cartridge 43 and the midplane.
• it supports up to 84 connections (pins) that will deliver SERDES outputs 224, 225, 12C signals 226, 227, and power 216, 217.
• Signal connections may be made through a right-angled connector.
• Power connections may be made through the information processing cartridge right-angled connector.
• the connector can be configured to facilitate hotswapping of the information processing cartridge, for example by having a low insertion force and/or guide pins to increase the ease of serviceability and prevent module misalignment during insertion.
• Interrupts to the processor 192 can be encoded using an encoded interrupt vector mechanism.
• An I-Chip Emulator (ICE) 228 functions as an interrupt concentrator, receiving all system interrupts and encoding them as an interrupt vector according to an interrupt vector code utilisable by the processor 192.
• the interrupt vector encoding may be based on a 6-bit interrupt vector code.
• CSSP combined switch and service processor
• each CSSP 71 provides the functionality of a Switch 73 and of a Shelf Service Provider, or Shelf Service Processor (SSP) 74.
• FIG 12 provides an overview of the functional components of the CSSP 71 including the functional components of the Switch 73 and the functional components of the SSP 74.
• the components relating to the Switch 73 are mounted on a Switch PCB 231
• the components relating to the SSP 75 are provided on a SSP PCB 232. It will be appreciated that such component arrangements are not compulsory for successful operation and that any other component arrangement over any number of component boards can be easily achieved using conventional component arrangement techniques.
• the midplane connector 141 on the CSSP 71 establishes the connection between the CSSP 71 and the midplane 171.
• it supports up to 84 connections (pins) that will deliver SERDES outputs 265-268, I2C signals 310, 320, 321 and 322, and power 278, 279.
• Signal connections may be made through a 40-pair right-angled connector.
• Power connections may be made through a right- angled connector.
• the connector can be configured to facilitate hotswapping of the board, for example with a low insertion force.
• the connector also uses guide pins to increase the ease of serviceability and prevent module misalignment during insertion.
• a switch microprocessor 240 is provided, in the present example the microprocessor used is a Power PC (MPC8245) packaged in a 352pin Tape Ball Grid Array (TBGA) package.
• This microprocessor 240 supports between 1MB and 2GB of address space in the present example. It further includes an Embedded Programmable Interrupt Controller (EPIC) that provides 5 hardware interrupts (IRQs) or 16 serial interrupts. There are 4 programmable timers with cascade mode function.
• DRAM memory for the processor can provided in the present example by a commodity DIMM 242.
• the processor 240 can be connected to a 32bit PCI bus 241, which operates at, for example, 33MHz/66MHz.
• a clock input to the processor 240 can be provided by a clock generator (CLK) 243.
• CLK 243 can include a configurable clock generator (not shown) implemented as a programmable clock synthesiser employing a crystal used to produce CPU clock signals.
• the clock frequency can be determined by jumper settings (not shown).
• a vectored interrupt controller (I-Chip) (not shown) and a configurable core voltage regulator module (VRM) (not shown) can be provided that operate substantially as described above with reference to the like components of Figure 11.
• two switch ASICs application specific integrated circuits 244, 245 are provided (in the present example, BCM5632 Gigabit switch ASICs).
• Each ASIC can provide twelve GMII Interfaces (1 Gigabit Ethernet) (for uplinks and downlinks) and one 10Gb XGMII interface for chip-to-chip communication (bridging) 246 between the ASICs 244 and 245.
• Sixteen GMII 1Gb 'downlinks', in the form of serialized Gb Ethernet data, are provided through four quad SERDES 248-251 to allow each information processing cartridge 43 to communicate with the switch 73.
• Eight GMII 1Gb 'uplinks' are provided for external communication through two quad PHYs 253 and 254 (in the present example BCM5404 ASICs) and RJ45 connectors on the rear panel 122.
• the ASICs 244 and 245 are configured via a PCI interface (32bit/33MHz) to the PCI bus 241.
• a Flash PROM 256 can store a real time operating system, and management and configuration data for the microprocessor.
• the Flash PROM 256 in the present example can be operable to hold 8MB - 16MB of data, depending on the software required.
• the flash PROM 256 can be operated via an on-chip XBus 258.
• a Real Time Clock (RTC) 259 can be provided for real-time functions with a back-up battery.
• a UART 260 Also connected to the XBus 258 can be a UART 260 which in turn connects to a serial bus 261 for providing an asynchronous console connection from the switch 73 to the SSP 74 which can be accessed by the SSP.
• An integrated MAC/PHY (Media Access Control/Physical) switch 271 can provides its own interface to the PCI bus 241. This MAC/PHY switch 271 can connects to a 10/100 Ethernet hub 272.
• the hub 272 can be operable to provide a management interface to the SSP 74 and a connection from an external management network to the switch 73 and SSP 74 of a given CSSP 71.
• the connection from the integrated MAC/PHY device 271 to the SSP 74 can be coupled capacitively.
• a loopback mode can be provided by the MAC/PHY device 271 for system diagnostics.
• the hub 272 can connect to an RJ45 connector 273 on the rear panel 122 of the CSSP enclosure 121.
• An 8kByte I2C EEPROM 262 can be used to store the FRU-ID and is accessible by the SSP portion 74 of each CSSP 71 via a serial bus 263 and the midplane 171.
• the upper 2kByte of the EEPROM 262 can be configured to be write protected.
• An I2C Redundant Control Register (RCR) 275 can be used to provide an alternate, redundant path for powering-down the CSSP 71 and Shelf Level Indicators 69 mounted on the front 57 and rear 59 panels of the shelf 41.
• the I2C RCR 275 can be accessible by both the SSP 73 of the CSSP 71 containing the RCR and the SSP 73 of a further CSP 71 connected via the midplane 171 via an I2C bus 276.
• a device suitable for use as the RCR 275 is a Phillips PCF8574 IC.
• SSP Shelf Service Provider
• SSP PCB 232 is facilitated by an interboard connector pair 298 and 299. It supports connections (pins) for I2C signals, 10/100 MAC/PHY output, and power.
• the switch PCB 231 carries the components associated with the switch, and it also carries the power, FRU-ID and environmental monitoring components along with the connectors for connections to the midplane 171 and external connectors.
• all SSP components requiring a connection to the midplane 171 or an external connection have signal paths routed through the connector pair 298, 299 and via the switch PCB 231 to the relevant midplane or external connectors.
• the SSP 74 includes a microprocessor 301 (e.g., a Power PC (MPC8245) processor) mounted on the SSP printed circuit board (PCB) 232.
• the processor 301 can be connected to a PCI bus 302, the present instance a 32 bit bus that operates, for example, at 33MHz/66MHz.
• a clock input to the processor 301 can be provided by a clock generator (CLK) 303.
• CLK 303 can comprise a configurable clock generator (not shown) implemented as a programmable clock synthesiser employing a crystal used to produce CPU clock signals. The clock frequency can be determined by jumper settings (not shown).
• a vectored interrupt controller (I-Chip) (not shown) and a configurable core voltage regulator module (NRM) (not shown) can be provided that operate substantially as described above with reference to the like components of Figure 11.
• the processor 301 can be provided with a DRAM memory 305.
• the memory capacity can be chosen to suit the processor addressable memory space. In the present example, 8 MB of DRAM memory is provided.
• An integrated MAC/PHY switch 306 can provide its own interface to the PCI bus 302.
• the MAC/PHY switch 271 can be connected to 10/100 Ethernet hub 272 via the interboard connectors 298, 299.
• a loopback mode can be provided by the MAC/PHY switch 306 for system diagnostics.
• Octal UARTs (Universal Asynchronous Receiver Transmitters) 308 and 309 can be connected between the PCI bus 302 and the interboard connector pair 298, 299.
• the signal path can be continued from the interboard connector pair 98, 299 to serial connections 310 on the midplane connector 141 on switch PCB 231.
• UARTS 308, 309 can facilitate serial (I2C) communications between the SSP 74 and each of the processing cartridges 43.
• a dual UART (DUART) 312 that in turn can connect via the interboard connectors 298, 299 to serial bus 261 for providing an asynchronous console connection from the SSP 74 to the switch 73.
• the DUART 312 can also have an I2C connection to an external connector on the rear face 122 of the CSSP enclosure 121.
• the external connector can provide a common operating system/boot console and command port 311.
• Flash PROM 315 Connected to the processor 301 via an XBus 314 can be a Flash PROM 315.
• the Flash PROM 315 can store a real time operating system, and management and configuration data for the microprocessor 301.
• the Flash PROM 315 can be operable in the present example to hold up to 2MB of data, depending on the software required.
• RTC real-time functions with a backup battery.
• the RTC 316 can also provide 8kByte of non-volatile random access memory (NNRAM), in the present instance implemented as an EEPROM. This can be used to contain information such as the FR-ID, a serial number and other FRU information.
• NRAM non-volatile random access memory
• a multiplexer 318 can be provided.
• the multiplexer 318 can have a single I2C connection to the processor 301 and connections, via the interboard connector pair 298, 299 and the midplane connector 141 to both PSUs 81, the midplane 171 and the other CSSP 71.
• the processor 301 can also comprise an embedded DUART to provide a redundant serial link to the SSP 74 of the other CSSP 71.
• an embedded DUART to provide a redundant serial link to the SSP 74 of the other CSSP 71.
• the advantage of using an embedded DUART is that the connection to the other CSSP is reliable and therefore likely to be functional.
• the embedded DUART link does not use the I2C Multiplexer for communications to the other CSSP, a common mode of failure for both the SSP - SSP I2C links can be avoided, it being assumed that the processor 301 is likely to be functional even if both embedded DUART channels are non-functional.
• the CSSP 71 can powered from two, diode commoned, 9V power supply rails 278 and 279.
• DC/DC converters 281 can be used to provide the voltage levels required by the CSSP 71.
• the DC/DC converters 281 can be supplied by dual 9V inputs 278, 279, individually fused 285, 286 and then diode commoned 287, 288.
• a soft start controller 283 can be provided to facilitate hot-insertion.
• a 5V DC/DC converter (I2C power regulator) 282 can be turned on as soon as the CSSP 71 is fully inserted.
• a 3.3V DC/DC converter can be turned when instructed, for example through SSP service software, by asserting low an appropriate signal (ONJ - not shown).
• the 3.3V converter can be arranged to turn on a converted for 2.5V, 1.2V, and a processor core voltage rail (Vcore) when the voltages are within an appropriate range.
• Vcore processor core voltage rail
• the inrush current can be limited, for example to ⁇ 1 A, and the rate of rise can be configured not to exceed a predetermined value (e.g.,
• a soft start controller 283 which controls a ramping-up of voltage levels, can be enabled when the predetermined signal (Inserted_L signal) is asserted low, this signal is on a short pin in the connector and is connected to ground (GND - not shown) through the midplane 171 until one of the supplies is removed.
• These circuits can be configured to withstand an overvoltage at their inputs whilst the input they are feeding is not powered, without any leakage to the unpowered circuit.
• a sense circuit can detect if the voltage has dropped below a threshold, for example 2.0V, as a result of a blown fuse, a power rail going down, etc.
• the DC/DC converters 281 can be protected against short circuit of their outputs so that no damage occurs.
• the I2C regulator 282 can be powered as soon as the CPPS 71 is fully inserted into the midplane 171. This can be facilitated through short pins connected to the soft start controller 283, which controls a ramping-up of voltage levels.
• the other DC/DC regulators can be turned on, for example by SSP software.
• a pair of fans 290, 291 can provide cooling to the CSSP 71.
• the fans 290, 291 can be configured to run at full speed to prevent overtemperature conditions by minimizing the temperature of the internal components and the fan.
• the speed of the fans 290, 291 can be monitored by the SSP 74 through an environmental monitor 295 on the switch board 231.
• the environmental monitor 295 can be alerted in the event of the fan speed falling below a predetermined value (e.g., 80% of its nominal speed).
• the fan can provide tachometer outputs to facilitate the measurement of fan speed.
• LED indicators 137 can be provided, for example with a green power LED, an amber LED for indicating that service is required and a blue LED for indicating that the switch is ready to be removed.
• LED indicators integrated on 2x4 stacked RJ45 connectors on the rear face of the CSSP 71 can be arranged, for example, to show green continually when the link is present and flash green when the link is active.
• the environmental monitor ENV MON 295 can be provided to maintain operational integrity of the CSSP 71.
• the ENV MON 295 can include limit values in limit registers and can. monitor, for example, temperature within the CSSP enclosure 72, the CSSP power rails, including the 12V, 3V3, Switch Processor Core Voltage, CSSP Processor Core Voltage and the two 9V power feed rails 278, 279 from the midplane 171.
• the outputs of the DC/DC converters 281 can be fed in to AID inputs of the ENV MON 295 for Watchdog comparisons to be made to the voltage limits set in the limit registers.
• the ENV MON 295 can also monitor the operating speeds of the fans 290 and 291.
• the ENV MON 295 can communicate with the SSP 74 of both CSSPs via an I2C bus 296.
• the midplane connector 141 can include sixteen 1Gb Ethernet connections 265-268 from four quad SERDES 248-251 and the I2C bus lines 596.
• the SSP 74 can access the I2C devices (FRU-ID EEPROM, 8-bit I/O expansion chip, and the system hardware monitor) through the midplane 171.
• I2C devices FRU-ID EEPROM, 8-bit I/O expansion chip, and the system hardware monitor
• rear panel Gb Ethernet connections can be provided from the two quad PHYs 253, 254 to 2x4 stacked RJ45 connectors 139 (to give 8 uplinks).
• Each port can be an independent 10/100/1000 BASE-T (auto negotiating) port.
• the PHY devices 253, 254 can operate in GMII mode to receive signals from the 8- Gigabit interfaces on the ASICs 244, 245.
• the Power Supply Units (PSUs) 81 can configured such that when two or more PSUs 81 are connected in parallel in the shelf 41, failure of any one of the paralleled units shall not affect system operation. Moreover, one of the PSUs can be installed or removed from a "live" system with or without input power applied. The outputs can have overcurrent protection.
• the PSU can have an I2C interface to provide power supply status via the midplane 171.
• the PSU can have an internal temperature sensor that reports via the I2C interface.
• the PSU fan speed can also be monitored and errors are reported via the I2C interface.
• Overvoltage and overcurrent sensors can also report via the I2C interface.
• a power supply e.g. mains power, or UPS type protected power
• transformer, regulator and rectifier circuitry 400 can operate to generate a DC output (in the present example, 12V DC) from the input (in the present example 230/240V 50Hz AC or 110V 60Hz AC).
• each PSU 81 can have a pair of cooling fans 402, 403 located at the rear of the PSU enclosure as described above with reference to Figure 7.
• the fans of each PSU 81 can be powered by both PSUs 81.
• the fans of both PSUs 81 can continue to run.
• this dual powering of cooling fans 402, 403 can be effected by providing a power supply line 404 from the transformer, regulator and rectifier circuitry 400 to power both fans 402, 403.
• first and second separate power lines 410, 412 from the other PSU 81 can provide duplicate power supply to the first and second fans 402, 403 respectively.
• the fan 402 can thus be powered by a diode commoned supply from line 404 and a diode commoned supply from line 410. Diode protection can be provided by diodes 405 and 411 respectively.
• the speed of the fan 402 can be controlled by a speed controller 408.
• the fan 403 can be powered by a diode commoned supply from line 404 and a diode commoned supply from line 412. Diode protection can be provided by diodes 406 and 414 respectively.
• the speed of the fan 403 can be controlled by a speed controller 409.
• the two speed controllers 408, 409 can in turn be controlled by a data input from each CSSP 71 received via an I2C bus connection (not shown in Figure 13).
• Power supply lines carrying DC power for the other FRUs of the shelf 41 are shown in Figure 13 as power line 416. All power connections to and from the PSU 81 can connect to the midplane 171 when the PSU is inserted in the shelf 41 via the midplane connector 163.
• the PSU 81 connects to the shelf through a 5P/24S/6P configuration SSI-MPS compliant right angle connector 163 at the front face 147 of the PSU 81.
• Connectors for the I2C interface can also be provided.
• the input power line 412 for the second fan 403 can be provided with a softstart module 413, to allow for hot insertion of the PSU 81 into the shelf 41.
• the softstart module 413 can be controlled, for example, by pulling a signal to ground
• Softstart protection for the first fan 402 can be provided by the main PSU softstart providing the power.
• the two input power lines 410 and 412 are separate lines having separate softstart provision, there is no common failure mode for the backup method of powering the fans 402, 403.
• a component power line or softstart module for example
• the power supply has four rear panel LED indicators
• a blue "Ready to Remove” LED can be driven by the I2C interface and indicate that the power supply may be removed from the system.
• An amber “Service Required” LED can be driven by the I2C interface and indicate that the power supply is in a fault condition: any output out of range, over-temperature or shutdown.
• a green "DC Output-OK” indicator can be driven by internal power supply circuits and show that the main 12 volt supply is functioning. The LEDs can remain lighted when individual outputs are in the current limited mode of operation.
• a green "AC Input- OK” indicator can be driven by internal power supply circuits and show that AC input power is within normal operating range.
• each of the processing cartridges (blades) 43 connects to the midplane 171 via a pair of information signal connections (e.g. Gb Ethernet links) 224, 225 and a pair of serial management signal connections 226, 227. Connections within the midplane 171 can ensure that each Ethernet link 224 is directed to a connection 265-268 from the midplane 171 to a first switch 73, and that each Ethernet link 225 is directed to a connection 265-268 from the midplane 171 to a second switch 73. Thus one Ethernet link can be established between each processing cartridge 43 and the switch 73 of each CSSP 71.
• Gb Ethernet links e.g. Gb Ethernet links
• each serial connection 226 is directed to a connection 310 from the midplane 171 to the first SSP 74 and that each serial connection 227 is directed to the second SSP 74.
• one serial link can be established between each processing cartridge 43 and the SSP 74 of each CSSP 71.
• information signal connections other than Gb Ethernet connections (e.g. Infiniband connections) could be employed in other examples.
• a plurality of serial connections can connect each SSP 74 to the other.
• Serial lines 320, 321 can connect each SSP 74 to the midplane 171 and connections within the midplane can connect the two sets of lines together.
• serial lines 322 can connect each SSP 74 to the midplane 171 and connections within the midplane 171 can connect to serial lines 324 from the midplane 171 to each PSU 81.
• each processing cartridge, or blade, 43 is connected to the switch 73 of each CSSP 71 by an information signal connection (e.g. a 1Gb Ethernet link) formed by a combination of links 224, 225 from the processing cartridge 43 to the midplane 171, connections within the midplane 171 and links 265-268 from the midplane 171 to each switch 73.
• an information signal connection e.g. a 1Gb Ethernet link
• a set of serial management signal connections comprising links 320, 321 and connections within the midplane 171 connect the SSP 74 of each CSSP 71 to the SSP 74 of the other CSSP 71.
• the 331 can be formed between the core data network 330 and the eight 1Gb Ethernet ports 139 provided on the rear panel 122 of the CSSP enclosure 121.
• a first external switch 335 can connect to a management (I2C) port 73 of the first CSSP 71 and a second external switch 336 can connect to a management (I2C) port 273 of the second CSSP 72.
• the management port 273 can provide a management network interface to both the switch 73 and SSP 74 of each CSSP 71.
• the external switches 335, 336 can each be connected to each of a pair of System Management Systems (SMSs) 338, 339.
• SMS System Management Systems
• a plurality of shelves 41 may be connected together via the core data network 330 under the control of a single management network utilising one set of SMSs 338, 339.
• a set of SMSs 338, 339 may comprise a single SMS (as well as a plurality thereof).
• use of at least two SMSs enables redundancy of components, therefore increasing overall system reliability.
• a serial interface control 343 operable under telnet protocol control is also connected to the shelf 41 in the present example. This can provide a common operating system/boot console connection to the SSP 74 of both CSSPs 71 via the RJ45 connector 311 on the rear panel 122 of each CSSP enclosure 121.
• up to 16 information processing cartridges, or blades 43 can be configured as sealed FRUs on a single shelf 41, the number of blades being chosen according to customer requirements.
• Each blade has its own processor and random access memory. If, for example, there is a maximum of 2Gbytes of memory per information processing cartridge, and one processor per blade, 16 processors (16P) with 5.33 processors per unit height (1U) and a total of 32GB of memory per shelf can be provided.
• the shelf 41 incorporates redundant combined switch and shelf service processor modules (CSSPs) 71 and redundant power supply units (PSUs) 81 separate from the blades 43.
• CSSPs switch and shelf service processor modules
• PSUs redundant power supply units
• the information processing cartridges can be kept compact and inexpensive. Also, as a result, they can be powered by DC power only, via the midplane 171.
• the FRUs e.g., the information processing cartridges, or blades, 43, the CSSPs 71 and the PSUs 81
• the enclosures of the FRUs can be arranged to enclose all of the functional components of the FRU with only electrical connectors being externally accessible and with indicator LEDs being externally visible as well.
• a rack mountable shelf that includes power supplies, a shelf service processor and switches in modular units, for carrying a number of processing cartridges, wherein the number of processing cartridges can be chosen according to customer requirements, provides a flexible and scalable computer configuration.
• the balancing of the load between the processors of the processing cartridges can be effected by software using conventional principles.
• a configuration as described provides an easily scalable processor architecture, whereby the processing power provided by a complete system based on the information processing cartridge/information processing cartridge carrier architecture can be scalable from moderate to very high capacity through the simple addition of further information processing cartridges.
• an example of the external connections from a shelf 41 can be in the form of two active information signal connections (e.g., Ethernet connections) 350 and 351, two active power connections 353 and an active/standby pair of management connections 354.
• each connection comprises a serial connection and a network (e.g. Ethernet or Infiniband) connection. It is possible to connect to either the active or the standby connection, as the incoming signal will be internally routed to whichever management controller (CSSP) is the current master. It will be appreciated, therefore, that the connections to a shelf can be kept to a minimum. It will further be appreciated from the configuration shown in Figure 16 that the system is scalable beyond a single shelf unit 41.
• Figure 17 illustrates how a plurality of shelves can be configured within one (or more) racks to provide even higher processing power.
• a constellation of shelves to provide a large grouping of servers is sometimes termed a "web farm" or "server farm” 360.
• the web farm comprises a plurality of shelves 41 that each carry a plurality of blades 43.
• NAS Network Attached Storage devices
• the NASs 373 are not required if there is no critical data to be stored, e.g. if the web farm is operating solely to provide web caching services.
• Management control of the web farm 360 can be provided through a pair of System Management Servers (SMSs) 362.
• SMSs System Management Servers
• Each SMS 362 can be connected to a management network via a link 366 and to a management console 365.
• the SMSs 362 can communicate with the individual shelves 41 via a pair of management switches 364.
• Each shelf 41 and NAS 373 can be connected to each management switch 364 via a connection 367.
• dual redundant management connections can be provided to each shelf 41 and NAS 373.
• Flow of data to and from the web farm 360 can be provided through a pair of data switches 369.
• Each data switch 369 can be connected to a consumer network via a link 370. It is to be understood that the consumer network can be a larger data network to which the web farm 360 is connected.
• This network can be an office or corporation intranet, a local area network (LAN), a wide area network (WAN), the
• connections 371 can be facilitated by connections 371. It is to be noted that as each shelf has its own switching capability, there is no need for each shelf 41 to be directly connected to the data switches 369. Connections can also be provided to connect the NAS units
• the topology used for interconnection of the data switches 369, shelves 41 and NASs 373 can be any topology providing at least one connection of any length between every possible pair of units.
• Complex topologies arranged to minimise the maximum connection length between any two given units in the web farm can be used.
• the web farm 360 comprising a plurality of shelves 41 with or without a plurality of NASs 373 can suitably be used as any or all of the entry edge server group 9, web edge server group 15 and application servers 19 described above with reference to Figure 1.
• Such storage can be provided within one or more NAS cartridges fitted into one or more of the shelves 41 in place of processing cartridges 43.
• a server shelf with local storage such as a RAID array (Redundant Array of
• Each module within a shelf or farm may run under the same operating system, or a plurality of different operating systems may be used.
• Examples of possible operating systems include Sun Microsystems' Solaris ® OS or another UNLXTM-Type OS such as LinuxTM, MINIXTM, or IrixTM, or UNLXTM or a Microsoft OS such as Windows NTTM, Windows 2000TM, Windows ME/98/95TM, Windows
• each processing cartridge within a shelf or farm be configured to run the same program software.
• individual processing cartridges may be configured to execute, for example, fileserver software, mailserver software, webhosting software, database software, firewall software, or verification software.
• two voltage sense circuits may be provided after the fuses and before the diodes, to prevent a latent fault caused by a failed fuse going undetected until one of the PSUs is removed or taken offline.
• Such circuits may configured to withstand an overvoltage at their inputs whilst the input they are feeding is not powered, without any leakage to the unpowered circuit.
• the processing module may be based on an UltraSPARC processor
• any other processor having sufficient processing capacity to undertake the tasks required of a particular processing cartridge may be used.
• Alternative processors include, but are not limited to, Intel x86 series and compatible processors, AMD x86 compatible processors, Alpha processors and PowerPC processors.
• Intel x86 series and compatible processors include, but are not limited to, Intel x86 series and compatible processors, AMD x86 compatible processors, Alpha processors and PowerPC processors.
• the particular example of an x86 compatible processor is described in more detail with reference to Figure 18.
• the parts corresponding to those of the UltraSPARC based system of Figure 11 have the same reference numerals and will not be described again here.
• each information processing cartridge comprises a single microprocessor, this is not a limiting case as each or any of the information processing cartridges may have more than one microprocessor arranged to share common storage resources to operate synchronously (in lockstep) or asynchronously. Also, it is not necessary that all information processing cartridges * inserted into a shelf at a given time are identical, rather a variety of different blade architectures may be used simultaneously.
• both Switch and Shelf Service Processor within a single FRU in the present example provides a facility within a single shelf 41 for dual redundancy in both functions in fewer different FRUs. As will be appreciated, there is no restriction that these two functions must be provided within a single FRU and division of the two functions into separate FRUs would present no difficulty to the skilled addressee.
• the backup power provision for the cooling fans of the PSUs is described above with reference to Figure 13. Although it is described that the backup power supply to each fan should be independent of the other, if the risk of common mode failure of backup power supply is judged to be low, or is of low importance, then the backup supply to each fan may be provided in common with the backup supply to all other fans.
• an information processing module forming a field replaceable server blade can include a processor and memory can be configured by means of software, firmware or hardware to provide a special purpose function.
• an information processing module can be configured to perform the function of one or more of a firewall, or a load balancer, encryption and/or decryption processing, an interface to a secure network, e.g. a virtual private network (VPN), a specialized switch with wide area network (WAN) connectability.
• a storage blade may be provided. The storage blade can be configured to be mountable in a server blade receiving location in a blade server carrier.
• the storage blade can comprise storage blade connectors configured for interconnecting with carrier connectors on the server blade carrier, whereby the storage blade is interchangeable with a server blade.
• a carrier, or shelf, for a server system can be arranged with a plurality of blade receiving locations for receiving blades, wherein the blades can be storage blades or information processing blades.
• the server system can be self configuring on receipt of the blades according to the type of blade received in each said location. To achieve the blade service controller in each blade can be operable to communicate with a shelf service provider to perform said configuring.
• NAS Network Attached Storage
• FIG. 19 illustrates an example of a combined switch and service processor in accordance with the invention to replace the combined switch and service processor of Figure 12.
• FC-AL interface 512 can be operable to convert between PCI format and a Fiber Channel Arbitrated Loop format (FC-AL).
• FC-AL Fiber Channel Arbitrated Loop format
• GBIC GigaBit Interface Converter
• the electrical signals at 514 can be provided to 9-way D type electrical connectors provided on the IO panel connector.
• a protocol converter 510 in the form of a software program provided in DRAM 242 and operable on the processor 240.
• storage data can be passed between the CSSP 71 and external storage devices using, for example, the Fiber Channel format over a FC-AL connection as described above.
• Another external storage protocol could be used in other examples.
• the communication of storage data can be carried out using, for example, iSCSI (Internet SCSI, or Internet Small Computer Systems Interface) format data over the Internet Protocol (IP), via the information connections (Ethernet or Infiniband) used for the exchange of information between the CS SP 71 and the server blades 43.
• iSCSI Internet SCSI, or Internet Small Computer Systems Interface
• an application on a server blade wishing to transmit information to a storage array sends small iSCSI protocol data in IP packets transmitted over the internal information connections and addressed to a specific IP address.
• the IP address maps in the CSSP 71 to the protocol converter 510.
• This storage data under the iSCSI format arrives in IP packets at the appropriate SERDES device 243, 249, 250, 251 from the server blade 43 concerned.
• the IP packet is then routed via the appropriate switch 244, 245 to the appropriate address for the protocol converter 510.
• the recognition of the arrival of an IP packet can be identified by software running on the CSSP processor 240 by means of an interrupt process, or by polling of the IP address location.
• the protocol converter 510 is operable to decode the storage information and to pass that storage information to the PCI/FC-AL interface 512 for transmission via the GBIC 516 to the optical connection 520 on the I/O panel connector.
• the protocol converter 510 is then operable to compose and transmit an appropriate IP packet containing the iSCSI format data via the appropriate switch and SERDES device to the server blade concerned via the midplane connector 141.
• the hardware configuration of the blade server can be as shown, for example, in Figures 11 and 18.
• an appropriate iSCSI driver 530 (shown schematically in the memory 196) is provided as part of the operating system for controlling the operation of the processor 192 of the server blade shown in Figure 20.
• the iSCSI driver 530 can perform the function of a storage interface in the blade server.
• the iSCSI format is used, it will be appreciated that other packet storage data formats could be used in other examples.
• an iSCSI driver 530 can similarly be provided for controlling the processor 378 of Figure 18.
• the iSCSI driver 530 is able to compose and send iSCSI format data formatted within IP packets over the information connections 224, 225 to the respective CSSPs 71 and is likewise able to decode received iSCSI IP packets.
• FC/IP Fiber Channel over the Internet Protocol
• FC/IP Fiber Channel over the Internet Protocol
• FC/IP Fiber Channel over the Internet Protocol
• FC/IP which is also known as Fiber Channel tunneling or storage tunneling, is a protocol that provides for Fiber Channel control codes and data to be translated into IP packets for transmission.
• Fiber Channel is a channel/network standard that can be implemented over fiber or copper and can operate as a generic transport mechanism.
• the protocol converter 510 is implemented by software that operates on the CSSP processor 240. However, in other examples, the protocol converter could be implemented by specific hardware (e.g., an Application Specific Integrated Circuit (ASIC) or by firmware (e.g., in a microcontroller).
• ASIC Application Specific Integrated Circuit
• an embodiment of the invention does not require any specific electrical connections to be provided in the midplane and the midplane connectors of the CSSP 71 and the server blades 43 to implement the external storage solution.
• iSCSI or the like and the provision of the external Fiber Channel connection from the CSSPs, enables efficient external storage to be provided without impacting the external network bandwidth available for non-storage IP traffic.
• the use of a structure as described, by way of example, with reference to Figures 19 and 20 enables the connection of direct-attached storage (DAS) and/or connection to a storage area network (SAN) over the external Fiber Channel connection.
• DAS direct-attached storage
• SAN storage area network

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