EP1295321A1 - Planarization process to achieve improved uniformity across semiconductor wafers - Google Patents
Planarization process to achieve improved uniformity across semiconductor wafersInfo
- Publication number
- EP1295321A1 EP1295321A1 EP01906705A EP01906705A EP1295321A1 EP 1295321 A1 EP1295321 A1 EP 1295321A1 EP 01906705 A EP01906705 A EP 01906705A EP 01906705 A EP01906705 A EP 01906705A EP 1295321 A1 EP1295321 A1 EP 1295321A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- dielectric layer
- semiconductor wafer
- polishing
- recited
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Definitions
- This disclosure relates to semiconductor fabrication and more particularly, to a
- Semiconductor devices are fabricated by processing layers of materials
- One such process includes planarizing a top
- Planarization techniques are not
- preprocessing steps may be employed.
- a mask process and an etching process are employed to remove material
- method for forming isolation regions includes a deposition of an oxide for a void free
- One problem with a mask and etch process is that the mask process is typically
- CMP chemical-mechanical polishing
- planarization is at the expense of global uniformity.
- eliminating a mask and etch step includes
- the semiconductor wafer is polished to remove a portion of the dielectric layer about
- the dielectric layer is polished across the
- a semiconductor wafer having first areas and second areas.
- first areas include trenches formed in a substrate of the semiconductor wafer.
- trenches are filled and up features form in the second areas.
- dielectric layer is adjusted after the trenches are filled to provide uniformity between a height of the dielectric layer in the first areas and a height of the dielectric layer in the
- An edge portion of the semiconductor wafer is polished to remove a
- the polishing is performed by a single non-stacked polishing
- the dielectric layer is polished across the entire semiconductor wafer
- step are eliminated from the polishing process.
- isolation regions By depositing and sputtering a second oxide layer on the first
- An edge portion of the semiconductor wafer is polished to remove a portion of the first and second oxide layers by exerting a bias force against edge portions of the wafer during polishing.
- the polishing is performed by a single non-stacked
- the dielectric layer is polished across the entire semiconductor wafer by employing the single non-stacked polishing pad and the
- the step of polishing an edge portion may include the step of
- the polishing pad may include a urethane polishing pad.
- forming a dielectric layer may include the steps of depositing and sputtering on the
- the dielectric layer to provide a void- free trench fill.
- the slurry may include a fumed
- the step of forming a dielectric layer may include the step of
- the step of forming a dielectric layer may include the step
- the method may include the step of adjusting the polish
- the step of depositing a dielectric layer may include
- HDP high-density plasma
- second oxide layer may include the step of depositing the first oxide layer by a high-
- the method may include the step of adjusting the polish rate of the first and second oxide layers.
- the bias power is preferably higher
- FIG. 1 is a flow diagram showing a method for planarizing a wafer without a
- FIG. 2 is a top view of a semiconductor wafer which may be planarized in
- FIG. 3 is a cross-sectional view of a substrate showing trenches formed therein
- FIG. 4 is a cross-sectional view of the substrate of FIG. 3 showing trenches
- FIG. 5 is a cross-sectional view of the substrate of FIG. 3 showing two
- FIG. 6 is a cross-sectional view of a conventional polish pad
- FIG. 7 is a cross-sectional view of a substrate having a dielectric layer formed
- FIG. 8 is a cross-sectional view of the substrate of FIG. 7 after etching in accordance with the prior art.
- FIG. 9 is a cross-sectional view of a polishing head apparatus showing edge
- the present invention provides methods for semiconductor fabrication and
- present invention includes new and useful method steps for polishing and deposition
- isolation regions which permit the formation of structures, such as, for example, isolation regions
- isolation in sub 0.25 micron deposited films or layers includes modulation of the
- oxide in the array regions is increased and polishing rate of oxide in the array regions
- This embodiment provides for modulation of global uniformity of the
- FIG. 1 a flow diagram for a method of depositing and planarizing a dielectric layer in accordance with the present invention is shown.
- block 10 a flow diagram for a method of depositing and planarizing a dielectric layer in accordance with the present invention is shown.
- semiconductor wafer 100 (FIG. 2) is provided. A semiconductor wafer 100, as shown.
- chips 102 for example, semiconductor memory devices, such as
- Wafer 100 includes areas 101
- Wafer 100 which do not include chips due to their proximity to the edge of wafer 100. Wafer 100
- wafer 100 is processed to
- Trenches 104 may be formed by employing a hard
- anisotropic dry etching e.g., reactive ion etching, substrate 106
- trenches 104 are formed for isolation
- regions such as shallow trench isolation regions employed for isolating devices
- isolation regions are formed by depositing a dielectric material
- Dielectric material 108 preferably includes an oxide and
- the high density oxide may be formed by employing a high density plasma deposition process. In one embodiment, shallow
- trench isolation regions are formed by filling trenches 104 with dielectric material
- substrate 106 may be covered by layers (not shown), such as a pad oxide layer or pad nitride layer or other dielectric for
- dielectric material 108 is a preferred embodiment, as shown in FIG. 4, as shown in FIG. 4, dielectric material 108
- dielectric layer 1 10 is modulated such that the
- dielectric material 108 e.g., oxide
- a deposition to sputter ratio is modulated to first provide a
- void free trench fill e.g., more sputtering
- the array areas e.g., less sputtering. This establishes more uniformity in polishing
- this modulation is performed during the deposition of dielectric
- dielectric material 108 In one preferred embodiment, the deposition of dielectric material 108
- deposition may include high-density plasma (HDP) deposition.
- HDP high-density plasma
- a multiple layer film 110' may be formed.
- Film 110' includes at least two layers
- HDP high density plasma
- the HDP process takes advantage of concurrent deposition and sputter,
- Up features 102 are formed in areas adjacent to arrays or in areas where large flat features occur. For example, the
- large up features include scribe lines or kerfs 103 between chips 102 (see FIG. 2).
- Dielectric layer 110' with layers 111 and 113 is advantageously provided to
- frequency bias is applied through the wafer's pedestal during deposition in a plasma
- the first layer (layer 111) at a higher bias for a
- bias layers include a lower volume of material than the high bias layers' volume.
- 11 1 and 113 may include different polishing rates as well.
- layer 113 may include different polishing rates as well.
- layer 113 may include different polishing rates as well.
- high-density plasma deposition/sputtering is employed to achieve high-density plasma deposition/sputtering.
- layer 111 is deposited with a bias of
- polishing is preferably performed
- fumed silica particles 60 to 120 RPMS for the platen, at 3 to 6 psi. and pressure, 60 to 120 RPMS for the carrier.
- CMP employs a hard urethane pad 51
- the top pad 51 is for
- the soft bottom pad 53 (felt)
- Up features 55 occur at transition locations in a
- dielectric layer 49 over the surface of a substrate 47.
- the current art employs a mask
- Patent No. 5,880,077 incorporated herein by reference.
- the mask and etch steps are eliminated while
- polishing rate uniformity includes the following.
- edge polishing is performed to compensate for non-uniform
- edge polishing is performed to
- Pad 202 may be provided with a wear-resistant surface or a wear-resistant
- Pad 202 is preferably affixed directly to a
- polishing table 204 and the modulation of uniformity can be accomplished by
- Edge polishing is performed since a single hard pad may leave an unpolished
- Edge polishing is preferably performed for a
- Contact with wafer 100 may be provided by shaping an interface 210, which may
- a carrier include a carrier, a carrier film, or other application of force to an edge portion of a
- Interface 210 includes a polishing membrane 203 for coupling wafer to
- An inner tube 214 may be included to perform the edge polish step of block 16
- Inner tube 214 includes an elastic material which applies a force to contact
- inner tube 214 is inflatable for applying a
- inner tube 214 is used for de- chucking (i.e., to lift) wafer 100 from the polish pad 202. By pressing onto wafer 100 through a plate 205 which is preferably perforated, inner tube 214 can also affect the polish pad 202.
- edge polishing by increasing the etch rate locally at the edge portions of wafer 100.
- Wafer 100 is edge polished to remove material at the edge portions of wafer 100. By utilizing an edge polish step in block 18, sufficient uniformity can be gained
- a polishing step such as a chemical mechanical polishing (CMP)
- the edge polish step of block 18 permits the use of a single pad, e.g.,
- IC 1000 pad in block 20 a single non-stacked hard pad 202 is used to
- Pad 202 is employed without continued
- Pad 202 may be provided with
- a wear-resistant surface or a wear-resistant material such as urethane, for example.
- pad is employed together with a fumed silica slurry to
- D7000 available commercially from Cabot, Inc.
- another preferred embodiment may include D7000 available commercially from Cabot, Inc.
- pad 202 includes a single (non-stacked) IC1000 pad, available from
- the steps of the present invention permit fabrication without a
- Some of the features of a preferred embodiment of the present invention include: 1) Use an edge polishing step prior at CMP such that global uniformity is
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US491645 | 2000-01-27 | ||
US09/491,645 US6359471B1 (en) | 1998-03-09 | 2000-01-27 | Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor |
US09/492,541 US6472291B1 (en) | 2000-01-27 | 2000-01-27 | Planarization process to achieve improved uniformity across semiconductor wafers |
PCT/US2001/002616 WO2001056070A1 (en) | 2000-01-27 | 2001-01-26 | Planarization process to achieve improved uniformity across semiconductor wafers |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1295321A1 true EP1295321A1 (en) | 2003-03-26 |
Family
ID=33479346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01906705A Withdrawn EP1295321A1 (en) | 2000-01-27 | 2001-01-26 | Planarization process to achieve improved uniformity across semiconductor wafers |
Country Status (1)
Country | Link |
---|---|
EP (1) | EP1295321A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997019467A1 (en) * | 1995-11-23 | 1997-05-29 | France Telecom | Side trench isolation method using a two-component protective layer of polysilicon on silicon nitride for insulator layer planarisation by chemical-mechanical polishing |
US5923993A (en) * | 1997-12-17 | 1999-07-13 | Advanced Micro Devices | Method for fabricating dishing free shallow isolation trenches |
US5952241A (en) * | 1997-09-03 | 1999-09-14 | Vlsi Technology, Inc. | Method and apparatus for improving alignment for metal masking in conjuction with oxide and tungsten CMP |
-
2001
- 2001-01-26 EP EP01906705A patent/EP1295321A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997019467A1 (en) * | 1995-11-23 | 1997-05-29 | France Telecom | Side trench isolation method using a two-component protective layer of polysilicon on silicon nitride for insulator layer planarisation by chemical-mechanical polishing |
US5952241A (en) * | 1997-09-03 | 1999-09-14 | Vlsi Technology, Inc. | Method and apparatus for improving alignment for metal masking in conjuction with oxide and tungsten CMP |
US5923993A (en) * | 1997-12-17 | 1999-07-13 | Advanced Micro Devices | Method for fabricating dishing free shallow isolation trenches |
Non-Patent Citations (1)
Title |
---|
See also references of WO0156070A1 * |
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Legal Events
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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Extension state: AL LT LV MK RO SI |
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DIN1 | Information on inventor provided before grant (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: MOTOROLA, INC. Owner name: INFINEON TECHNOLOGIES RICHMOND, LP Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: BAILEY, SCOTT, W. Inventor name: DAVIS, JONATHAN P. Inventor name: PAGE, JOSEPH E. |
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RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: BAILEY, SCOTT, W. Inventor name: DAVIS, JONATHAN P. Inventor name: PAGE, JOSEPH E. |
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RBV | Designated contracting states (corrected) |
Designated state(s): AT BE CH CY DE FR GB IE IT LI |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: MOTOROLA, INC. Owner name: INFINEON TECHNOLOGIES RICHMOND, LP Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
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