EP1281131A2 - Micro controller with re-programmable flash memory - Google Patents

Micro controller with re-programmable flash memory

Info

Publication number
EP1281131A2
EP1281131A2 EP00980243A EP00980243A EP1281131A2 EP 1281131 A2 EP1281131 A2 EP 1281131A2 EP 00980243 A EP00980243 A EP 00980243A EP 00980243 A EP00980243 A EP 00980243A EP 1281131 A2 EP1281131 A2 EP 1281131A2
Authority
EP
European Patent Office
Prior art keywords
program
logic controller
programmable logic
programmable
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00980243A
Other languages
German (de)
French (fr)
Inventor
Alan Mcnutt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Energy and Automation Inc
Original Assignee
Siemens Energy and Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Energy and Automation Inc filed Critical Siemens Energy and Automation Inc
Priority claimed from US09/697,419 external-priority patent/US7134118B1/en
Publication of EP1281131A2 publication Critical patent/EP1281131A2/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers

Definitions

  • the present invention relates to a flash memory and, more particularly, to a reprogrammable flash memory micro controller.
  • the flash memory may be configured as a programmable logic controller.
  • the controller CPU includes a microprocessor, possibly supplemented with a custom control instruction processor (boolean processor), for execution of the user program under the supervision of an operating system, random access data memory (RAM) for user and operating system data, battery backed RAM or non- volatile EEPROM for storing the user program, and a permanent ROM or EPROM for storage of the operating system software.
  • a custom control instruction processor boost converter
  • RAM random access data memory
  • the controller CPU includes a microprocessor, possibly supplemented with a custom control instruction processor (boolean processor), for execution of the user program under the supervision of an operating system, random access data memory (RAM) for user and operating system data, battery backed RAM or non- volatile EEPROM for storing the user program, and a permanent ROM or EPROM for storage of the operating system software.
  • RAM random access data memory
  • EEPROM electrically erasable programmable read-only memory
  • the user program is typically prepared on a general purpose computer and loaded into the PLC in symbolic form.
  • the loading is typically by means of a serial communications protocol, though a removable memory cartridge may sometimes be used to by-pass this step.
  • the symbolic code is converted to executable code by a compiler. Included in the system software that must be permanently stored in ROM, there is the actual operating system that coordinates execution, the communications software to support transfer of the user program and data, and the compiler which converts the symbolic user program to executable form.
  • the operating system has to coordinate the communications, compilation, and program execution functions. This requires some sophistication of the operating system to respond to communications events, queue/de queue deferred tasks, and manage mode transitions between program mode and run mode.
  • the compiler and communications software functions may be quite large, and significantly extend permanent storage requirements beyond that needed for controlling the execution of the user program.
  • micro controllers including the data RAM and operating system ROM on a single chip with the microprocessor.
  • the user program is contained in an external storage device: battery backed RAM, EPROM, or EEPROM, possibly added to the basic unit as a removable memory cartridge.
  • the functions of the programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
  • a micro controller incorporating a micro processor, RAM, and re programmable Flash EPROM in a single package implements the logical core of the program execution device.
  • the external pins of this package can be largely devoted to the 110 functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor.
  • External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
  • the communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device.
  • This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing.
  • the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel.
  • the kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
  • the block diagram below shows the extreme simplicity of the program execution device. This diagram shows, as non-essential auxiliary features, a watchdog timer function to disable outputs on controller failure and optical isolation of inputs and outputs.
  • the communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
  • the advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost.
  • the burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device.
  • the communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.
  • Fig. 1 shows the invention.
  • the functions of the programmable logic controller are located in physically separable units.
  • These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
  • a micro controller 10 incorporating a micro processor 12, RAM 14, and reprogrammable Flash EPROM 16 in a single package l ⁇ implements the logical core of the program execution device.
  • the external pins 20 of this package can be largely devoted to the I/O functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor.
  • External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
  • the communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device.
  • This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing.
  • the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel.
  • the kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
  • the diagram of Fig. 1 below shows the extreme simplicity, yet novel ingenuity, of the program execution device.
  • This diagram shows, as non-essential auxiliary features, a watchdog timer 22 function to disable outputs on controller failure and optical isolation 24 of inputs and outputs.
  • the communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
  • the advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost.
  • the burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device.
  • the communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)
  • Logic Circuits (AREA)

Abstract

Functions of a programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function. The micro controller incorporates a micro processor, RAM, and re programmable Flash EPROM in a single package implements the logical core of the program execution device.

Description

RE-PROGRAMMABLE FLASH MEMORY MICRO CONTROLLER AS PROGRAMMABLE LOGIC CONTROLLER
BACKGROUND
Field of the Invention.
The present invention relates to a flash memory and, more particularly, to a reprogrammable flash memory micro controller. The flash memory may be configured as a programmable logic controller.
Related Information.
Programmable logic controllers on the market today generally have a common architecture. Typically, the controller CPU includes a microprocessor, possibly supplemented with a custom control instruction processor (boolean processor), for execution of the user program under the supervision of an operating system, random access data memory (RAM) for user and operating system data, battery backed RAM or non- volatile EEPROM for storing the user program, and a permanent ROM or EPROM for storage of the operating system software.
The user program is typically prepared on a general purpose computer and loaded into the PLC in symbolic form. The loading is typically by means of a serial communications protocol, though a removable memory cartridge may sometimes be used to by-pass this step. Within the PLC, the symbolic code is converted to executable code by a compiler. Included in the system software that must be permanently stored in ROM, there is the actual operating system that coordinates execution, the communications software to support transfer of the user program and data, and the compiler which converts the symbolic user program to executable form. The operating system has to coordinate the communications, compilation, and program execution functions. This requires some sophistication of the operating system to respond to communications events, queue/de queue deferred tasks, and manage mode transitions between program mode and run mode. The compiler and communications software functions may be quite large, and significantly extend permanent storage requirements beyond that needed for controlling the execution of the user program.
Recently introduced models designed for low cost have used micro controllers including the data RAM and operating system ROM on a single chip with the microprocessor. The user program is contained in an external storage device: battery backed RAM, EPROM, or EEPROM, possibly added to the basic unit as a removable memory cartridge.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory that resolves the afore-mentioned problems. In this invention the functions of the programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
A micro controller incorporating a micro processor, RAM, and re programmable Flash EPROM in a single package implements the logical core of the program execution device. The external pins of this package can be largely devoted to the 110 functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor. External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
The communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device. This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing.
Instead of having a distinct operating system, the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel. The kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
The block diagram below shows the extreme simplicity of the program execution device. This diagram shows, as non-essential auxiliary features, a watchdog timer function to disable outputs on controller failure and optical isolation of inputs and outputs. The communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
The advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost. The burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device. The communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.
In existing programmable logic controllers, these included functions of communication and compilation typically consume tens of thousands of bytes of stored binary code. Removing these functions from the program execution device represents a significant saving in hardware for controllers that are designed for user programs of only a few hundreds of bytes.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 shows the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In this invention the functions of the programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
As shown in Fig. 1, a micro controller 10 incorporating a micro processor 12, RAM 14, and reprogrammable Flash EPROM 16 in a single package lδimplements the logical core of the program execution device. The external pins 20 of this package can be largely devoted to the I/O functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor. External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
The communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device. This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing. Instead of having a distinct operating system, the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel. The kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
The diagram of Fig. 1 below shows the extreme simplicity, yet novel ingenuity, of the program execution device. This diagram shows, as non-essential auxiliary features, a watchdog timer 22 function to disable outputs on controller failure and optical isolation 24 of inputs and outputs. The communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
The advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost. The burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device. The communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.
In existing programmable logic controllers, these included functions of communication and compilation typically consume tens of thousands of bytes of stored binary code. Removing these functions from the program execution device represents a significant saving in hardware for controllers that are designed for user programs of only a few hundreds of bytes.

Claims

Claims :
1. A programmable logic controller comprising: a single chip micro controller; internal RAM that is internal to said single micro controller; and internal re programmable read only memory that is internal to said single chip micro controller, the internal re programmable memory being used to store a user program for actualizing programmable logic controller functions.
2. A programmable logic controller program for directing a programmaable logic controller, comprising: a user program; and system sequencing and coordination instructions necessary to operate said programmable logic controller, wherein said user program and system sequencing and coordination instructions are compiled together into a single executable firmware module of said programmable logic controller, requiring no external operating system.
3. A programmable logic controller system, comprising: a program execution device having a re programmable memory and whose function is limited to program execution of a programmable logic controller; and a separable communication/programming device, which provides the programmability function, wherein said communication/programming device provides in a separable package all functions required for external communication and conversion of a user program for controlling said programmable logic controller from symbolic form to binary code, and loading of that code into said program execution device and wherein said binary code is programmed into said re programmable memory of said program execution device by direct manipulation of logic controls of said re programmable memory.
EP00980243A 1999-10-26 2000-10-26 Micro controller with re-programmable flash memory Ceased EP1281131A2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16145099P 1999-10-26 1999-10-26
US161450P 1999-10-26
US09/697,419 US7134118B1 (en) 2000-10-26 2000-10-26 Re-programmable flash memory micro controller as programmable logic controller
US697419 2000-10-26
PCT/US2000/029639 WO2001031474A2 (en) 1999-10-26 2000-10-26 Micro ocontroller with re-programmable flash memory

Publications (1)

Publication Number Publication Date
EP1281131A2 true EP1281131A2 (en) 2003-02-05

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EP00980243A Ceased EP1281131A2 (en) 1999-10-26 2000-10-26 Micro controller with re-programmable flash memory

Country Status (3)

Country Link
EP (1) EP1281131A2 (en)
CN (1) CN100388262C (en)
WO (1) WO2001031474A2 (en)

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CN112650189A (en) * 2019-10-12 2021-04-13 中电智能科技有限公司 Embedded PLC automatic test system and method

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EP0464433A3 (en) * 1990-06-29 1994-05-18 Nat Semiconductor Corp Microcontroller device having remotely programmable eprom & method of programming
US5379388A (en) * 1992-07-08 1995-01-03 Advanced Micro Devices, Inc. Digital signal processing apparatus with sequencer designating program routines
US5590373A (en) * 1994-07-25 1996-12-31 International Business Machines Corporation Field programming apparatus and method for updating programs in a personal communications device
US5606710A (en) * 1994-12-20 1997-02-25 National Semiconductor Corporation Multiple chip package processor having feed through paths on one die
US6023776A (en) * 1996-03-22 2000-02-08 Matsushita Electric Industrial Co., Ltd. Central processing unit having a register which store values to vary wait cycles
JPH10326205A (en) * 1997-03-27 1998-12-08 Mitsubishi Electric Corp System call issuing method
DE19732324A1 (en) * 1997-07-28 1999-02-04 Kloeckner Moeller Gmbh Circuit arrangement and method for memory space management and for processing user programs in small control systems

Non-Patent Citations (3)

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Title
See also references of WO0131474A3 *
VEDDER K.; WEIKMANN F.: "Smart cards-requirements, properties, and applications", 1 January 1998, STATE OF THE ART IN APPLIED CRYPTOGRAPHY. COURSE ON COMPUTER SECURITY AND INDUSTRIAL CRYPTOGRAPHY. REVISED LECTURES, SPRINGER-VERLAG BERLIN, GERMANY, PAGE(S) 307 - 331, ISBN: 9783540654742, XP002503200 *
VEDDER K.; WEIKMANN F.: "Smart cards-requirements, properties, and applications", STATE OF THE ART IN APPLIED CRYPTOGRAPHY. COURSE ON COMPUTER SECURITY AND INDUSTRIAL CRYPTOGRAPHY. REVISED LECTURES, 1998, BERLIN, GERMANY, pages 307 - 331, ISBN: 3-540-65474-7 *

Also Published As

Publication number Publication date
CN100388262C (en) 2008-05-14
CN1460216A (en) 2003-12-03
WO2001031474A3 (en) 2002-11-21
WO2001031474A2 (en) 2001-05-03

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