EP1261173A3 - System on a chip for packet processing - Google Patents

System on a chip for packet processing Download PDF

Info

Publication number
EP1261173A3
EP1261173A3 EP20020253533 EP02253533A EP1261173A3 EP 1261173 A3 EP1261173 A3 EP 1261173A3 EP 20020253533 EP20020253533 EP 20020253533 EP 02253533 A EP02253533 A EP 02253533A EP 1261173 A3 EP1261173 A3 EP 1261173A3
Authority
EP
Grant status
Application
Patent type
Prior art keywords
integrated
memory controller
used
interface circuit
packet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20020253533
Other languages
German (de)
French (fr)
Other versions
EP1261173A2 (en )
EP1261173B1 (en )
Inventor
Kwong-Tak A. Chui
Shailendra S. Desai
Daniel W. Dobberpuhl
Mark D. Hayter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/30Flow control or congestion control using information about buffer occupancy at either end or transit nodes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/60Router architecture
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/29Using a combination of thresholds
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/103Switching fabric construction using shared central buffer, shared memory, e.g. time switching
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/901Storage descriptor, e.g. read or write pointers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/9042Separate storage for different parts of the packet, e.g. header and payload
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/253Connections establishment or release between ports
    • H04L49/254Centralized controller, i.e. arbitration or scheduling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3018Input queuing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3027Output queuing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/35Application specific switches
    • H04L49/351LAN switches, e.g. ethernet switches

Abstract

A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
EP20020253533 2001-05-18 2002-05-20 System on a chip for packet processing Active EP1261173B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09861188 US7287649B2 (en) 2001-05-18 2001-05-18 System on a chip for packet processing
US861188 2001-05-18

Publications (3)

Publication Number Publication Date
EP1261173A2 true EP1261173A2 (en) 2002-11-27
EP1261173A3 true true EP1261173A3 (en) 2005-01-05
EP1261173B1 EP1261173B1 (en) 2007-01-03

Family

ID=25335122

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20020253533 Active EP1261173B1 (en) 2001-05-18 2002-05-20 System on a chip for packet processing

Country Status (3)

Country Link
US (2) US7287649B2 (en)
EP (1) EP1261173B1 (en)
DE (2) DE60217221D1 (en)

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Also Published As

Publication number Publication date Type
EP1261173A2 (en) 2002-11-27 application
US7320022B2 (en) 2008-01-15 grant
US7287649B2 (en) 2007-10-30 grant
US20020174255A1 (en) 2002-11-21 application
DE60217221D1 (en) 2007-02-15 grant
EP1261173B1 (en) 2007-01-03 grant
DE60217221T2 (en) 2007-10-04 grant
US20020174252A1 (en) 2002-11-21 application

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