EP1226503A2 - Bus system for simultaneous handling of various memory access procedures with a system-on-chip solution - Google PatentsBus system for simultaneous handling of various memory access procedures with a system-on-chip solution
- Publication number
- EP1226503A2 EP1226503A2 EP20000981154 EP00981154A EP1226503A2 EP 1226503 A2 EP1226503 A2 EP 1226503A2 EP 20000981154 EP20000981154 EP 20000981154 EP 00981154 A EP00981154 A EP 00981154A EP 1226503 A2 EP1226503 A2 EP 1226503A2
- European Patent Office
- Prior art keywords
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Bus system for the simultaneous processing of different memory accesses at ¬ system-on-chip solutions
The present invention relates to a data processing ¬ apparatus for transmitting, receiving, processing and storing data, as described in the preamble of annexed claim 1.
Modern electronic systems are becoming smaller due to the technological development. Due to this development complete systems are now on a chip (Chip) implemented as a so-called system-on-chip solution Lo. An example of this r is a computer system having one or more processors with one or more memory units, input and output units or transmitter and receiver units, external interfaces and a bus structure for transferring data between the individual components.
These system-on-chip solutions to such need. As input and output components and one or more processors, which performs the same resources, such as sharing one or more storage units and interfaces with simultaneous accesses to the storage units and interfaces to Engpassen during data transmission through the common bus structure.
In the prior art simultaneous requests (ie requests) are the users (processors, input and Ausgabeemhei- th) to shared resources (memory units, external interfaces), sequentially, that is processed sequentially.
These z. B. between the users and the bus structure interposed a so-called bus sequencer orders the (access requests) to buffer the user and in turn executes. This has the disadvantage that in some cases considerable delays in exports of accesses by several users created on the available resources, even if the user access to various resources.
The object of the present invention is thus a data verarbeitungsvorπchtung according to the preamble of claim 1 beigefug ¬ th provide that allows simultaneous access by multiple users to different memory devices.
This object is achieved by a data processing device with the features of the annexed claim 1.
According to the present invention controls de Zugriffssteue- tion users' access to the storage devices such that both can access memory devices at the same two users.
Deadlocks that prevent simultaneous access by two users on the existing storage devices, occur only when two users want to access the same storage device at the same time.
The parallel use of existing storage devices creates a significant increase in performance of the entire inventive shaped computing device to a data processing device with a conventional bus system.
The present invention is applicable let that more than two memory devices, and more than two users, such as processors and other hardware components that can directly access the storage device, such as transmitting or receiving device. On systems In this case, the erfmdungsgemaße access device allows equal ¬ simultaneous access of more than two users to the EXISTING ¬ which storage devices, as long as no two users want to access the same storage device at the same time.
Advantageous embodiments of the invention are in the dependent teranspruchen 2 to 11 indicated.
According to the present invention, the access of the appli ¬ is the controlled in the individual memory devices through the Zugriffsvorπchtung by, forwards the requests from the user indicating a corresponding access request to the respective memory device.
The access to the individual memory devices is controlled by access control, wherein access control is provided for each memory device. This has the advantage that its own access parameters can be set for each storage device such. As write protection, error detection, short-term barriers to access, inter ruptunterstutzung etc. The access controls are part of the access device.
Forwarding user requests to the appropriate storage devices and their access control area is from identification devices in which an identification device is provided for each user. The identification device determined based on the arrival of the m memory address contained ask for a memory access to the corresponding memory device and their access control. After the access control has been determined to be accessed the storage device, the request is forwarded to the appropriate access control tet; the m of the data contained storage device is thus read, and vice versa forwarded to the requesting user. Thus, according ä ß of the present invention, the selection of the memory device through the access device. The user itself does not distinguish the individual storage devices.
In order to permit a simultaneous and parallel access for users to a plurality of memory devices, it is necessary that the respective access controllers operate independently of each other, that is also that these devices m the access device are configured separately from each other. The same also applies to the identification devices.
According to the present invention, the Speichervorπch- obligations are designed so that m is stored, each with different application purposes them data. The data can be shared as needed, eg. B. m smaller data content of external internet must be quickly translated and larger amounts of data that are stored on external storage devices and is used by of the inventive data processing device and other users, such as external microprocessors, for example.
Particularly advantageous is this division of the tank supply directions when the erf dungsgemaße data processing apparatus is realized on a block solution as so-called system-on-chip Lo. It is for reasons of space on the device, a small, very fast storage device available, the z. As for the treatment of data is needed, the real-time needs to be processed. For larger amounts of data, another storage device is connected to the interface module has its own memory.
On the block is another interface (so-called master / slave interface) available on both other users (eg. As central processing units) of the inventive data processing device as well as other tank supply devices (eg. As a central memory, random access memory) are connected.
So a private Mikrocompu- let at this interface tersystem with a central unit and connect a Speichervor ¬ direction, on the example, a Betriebssy ¬ stem is loaded into the erfmdungsgemaße data processing device. But this interface also let USAGE ¬ to exchange data with other devices that z. B. forming a redundancy inventive shaped data processing device.
Characterized in that the access device erfmdungsgemaß m a precursor (Identif zierungsvorrichtung) and various supply is split grip control systems, a problem-free, non-blocking connection of a master / slave interface (z. B. PCI interface) is made possible. The Ansteuerungsemheit for external access is in this case as the internal memory devices assigned its own access control. The requirements rungsemheit external accesses its own identification device is assigned. the so-called "deadlock" situation is avoided by this separation of the access paths of master and slave interface, can occur by blocking this interface.
The present invention will be described by way of preferred exemplary embodiments with reference to the attached figures explained in more detail, m show which:
Figure 1 shows the structure of the inventive data processing apparatus as a system-on-chip solution,
2 shows the detailed construction of the inventive access device. Figure 1 shows the application of the inventive access system 4 ¬ a block 7 of the company Siemens AG, the protocol coprocessor ATM300.
The ATM300 building block 7 is m switching node of voice and Datenubertragungsnetzen used for disassembly and reassembly of data and provides a Protokollunterstutzung, ie the data is processed m depending on their parameters.
As can be seen in Figure 1, the processors la ... lc and the transmitting and receiving apparatus 2 to engage over the ¬ handle device 4 to the storage devices 3a, 3b, 3c. In conventional bus systems simultaneously feed are handles of two or more users la ... lc, processed 2 on several different storage devices in order.
According to the present invention, two or more departure pancake la ... lc, 2 3c simultaneously access a corresponding number of different storage devices 3a .... the requests are 3c during simultaneous access by two users la ... lc, 2 to a single storage device 3a ... sequentially, that is processed sequentially.
All connections between the blocks are bi-directional, that is, the data can be transferred m both directions. The arrows indicate the master / slave relationship between the individual components, such. For example, between the central processing units la ... lc (master) and the access device 4 (slave). The
done requirements m to access the case of users that appeal to the access device 4 to a storage device, etc.
The data of the users are divided depending on the application to different memory devices 3a ... 3c, wherein the storage devices 3a ... 3c differ in size and processing speed. Thus, be. B. data m real time must be processed on which it ¬ th memory device 3a is latched, which is located on the chip. 7
This storage device 3a has, as it is located directly on the block 7, very short access times, ie it is very fast. However, the storage capacity is relatively small. Therefore, larger amounts of data who needed a less high processing speed m of the second SpeI ¬ chervorrichtung 3b are stored. For the second Speichervor ¬ direction 3b, which is located outside of the block 7, is present on the block 7, a memory interface 10 degrees.
Furthermore, a so-called edge ma- / slave interface 8 (z. B. PCI interface, Peπpheral Component Interconnect) is supported by the component 7. This means that through this interface 8 both user access (e.g., as a microprocessor 9) on the block 7, as well as resources (eg. As more memory devices 3c) by block 7 can be addressed.
Since both the microprocessor 9 and the block 7 can access the storage unit 3c via an external access controller 11, it forms the interface between hardware and software. The access time is correspondingly slow due to the external access control.
Via the interface 8, the CPU 9 can access via the external access control 11 on the block. 7 For instance can. As when switching on the entire system, an operating system or other software from the storage device 3c m load the block. 7
Referring to Figure 2, the operating principle of the inventive access apparatus 4 is explained in more detail below. The access device 4 essentially consists of a preliminary stage, the identification devices 6a ... 6n (so-called arbiter ¬ Identifier) and access controllers 5a ... 5c (so-called target arbiter).
For each user, as central processing units la ... lc, transmitting and receiving means 2 and master / slave interface 8 it is em arbiter Identifier 6a ... 6n, each resource (SpeI ¬ chervorrichtungen, master / slave interface) em objective arbiter 5a ... 5c at your disposal.
The respective arbiter Identifier 6a ... 6n determined by means of the applied address, the output resources (memory devices) for the requested bus cycle. Since these precursor limited (arbiter Identifier) exclusively to the determination of the target arbiter (5a ... 5c), the necessary logic can be kept relatively low and mstanziert at reasonable expense gate for each user (established) are. As a result, an independent and parallel Auftragser- averaging for all users ensured, even if the bus system (erfmdungsgemaße access device 4) is already used for another purpose.
The access wish of the user through the respective arbiter identifier to the appropriate target Arbiter
5a ... 5c forwarded. Each objective arbiter manages a storage device 3a ... 3c and works independently of the other objective arbiters. In connection with the likewise independently operating arbiter identifiers is by DA em simultaneous access to different storage device allows.
The individual target arbiter 5a ... 5c can thereby individual ... meet 3c depended the tasks of the requirements of the respective storage device 3a such. B. write protection, error detection, interrupt handling. Furthermore 3a registers are available in the storage device that is accessible to the individual user through a direct connection.
flexible adaptation to appropriate conditions is made possible by the modular design of the bus system by a division of the bus system in arbiter identifiers and destination arbiter. To increase the performance of data processing apparatus according to the invention, the number of target arbiter can be increased with relatively little effort. The optimal number of target arbiter results from a trade-off between performance and required gate effort.
Priority Applications (3)
|Application Number||Priority Date||Filing Date||Title|
|PCT/DE2000/003765 WO2001033363A2 (en)||1999-11-02||2000-10-25||Bus system for simultaneous handling of various memory access procedures with a system-on-chip solution|
|Publication Number||Publication Date|
|EP1226503A2 true EP1226503A2 (en)||2002-07-31|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|EP20000981154 Withdrawn EP1226503A2 (en)||1999-11-02||2000-10-25||Bus system for simultaneous handling of various memory access procedures with a system-on-chip solution|
Country Status (2)
|EP (1)||EP1226503A2 (en)|
|WO (1)||WO2001033363A2 (en)|
Family Cites Families (3)
|Publication number||Priority date||Publication date||Assignee||Title|
|US5590304A (en) *||1994-06-13||1996-12-31||Covex Computer Corporation||Circuits, systems and methods for preventing queue overflow in data processing systems|
|US6006296A (en) *||1997-05-16||1999-12-21||Unisys Corporation||Scalable memory controller|
|US6038646A (en) *||1998-01-23||2000-03-14||Sun Microsystems, Inc.||Method and apparatus for enforcing ordered execution of reads and writes across a memory interface|
Non-Patent Citations (1)
|See references of WO0133363A2 *|
Also Published As
|Publication number||Publication date|
|US5859975A (en)||Parallel processing computer system having shared coherent memory and interconnections utilizing separate undirectional request and response lines for direct communication or using crossbar switching device|
|US4720784A (en)||Multicomputer network|
|US6072781A (en)||Multi-tasking adapter for parallel network applications|
|US6182183B1 (en)||Communications system and method with multilevel connection identification|
|US7523157B2 (en)||Managing a plurality of processors as devices|
|US5627976A (en)||Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture|
|US7617376B2 (en)||Method and apparatus for accessing a memory|
|US5490253A (en)||Multiprocessor system using odd/even data buses with a timeshared address bus|
|US6662252B1 (en)||Group and virtual locking mechanism for inter processor synchronization|
|US6691216B2 (en)||Shared program memory for use in multicore DSP devices|
|US6628662B1 (en)||Method and system for multilevel arbitration in a non-blocking crossbar switch|
|US5761445A (en)||Dual domain data processing network with cross-linking data queues and selective priority arbitration logic|
|EP0165600A2 (en)||Input/output bus for computer|
|US5032985A (en)||Multiprocessor system with memory fetch buffer invoked during cross-interrogation|
|US7165094B2 (en)||Communications system and method with non-blocking shared interface|
|US6421751B1 (en)||Detecting a no-tags-free condition in a computer system having multiple outstanding transactions|
|US6253271B1 (en)||Bridge for direct data storage device access|
|US5301283A (en)||Dynamic arbitration for system bus control in multiprocessor data processing system|
|US5396602A (en)||Arbitration logic for multiple bus computer system|
|US6182112B1 (en)||Method of and apparatus for bandwidth control of transfers via a bi-directional interface|
|US5006982A (en)||Method of increasing the bandwidth of a packet bus by reordering reply packets|
|US5689713A (en)||Method and apparatus for interrupt communication in a packet-switched computer system|
|US6295553B1 (en)||Method and apparatus for prioritizing delivery of data transfer requests|
|US5519883A (en)||Interbus interface module|
|US4821170A (en)||Input/output system for multiprocessors|
|AK||Designated contracting states:||
Kind code of ref document: A2
Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
|17P||Request for examination filed||
Effective date: 20020404
|RBV||Designated contracting states (correction):||
Designated state(s): DE FR GB
|18D||Deemed to be withdrawn||
Effective date: 20040921