EP1184900A2 - Batteriesteuerungsschaltkreis mit Leistungs-MOSFETs und Verfahren zu Seiner Herstellung - Google Patents

Batteriesteuerungsschaltkreis mit Leistungs-MOSFETs und Verfahren zu Seiner Herstellung Download PDF

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Publication number
EP1184900A2
EP1184900A2 EP01302533A EP01302533A EP1184900A2 EP 1184900 A2 EP1184900 A2 EP 1184900A2 EP 01302533 A EP01302533 A EP 01302533A EP 01302533 A EP01302533 A EP 01302533A EP 1184900 A2 EP1184900 A2 EP 1184900A2
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EP
European Patent Office
Prior art keywords
conductive
mosfet
protection circuit
circuit device
chip
Prior art date
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Granted
Application number
EP01302533A
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English (en)
French (fr)
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EP1184900A3 (de
EP1184900B1 (de
Inventor
Noriaki Sakamoto
Yoshiyuki Kobayashi
Hirokazu Fukuda
Hiroki Etou
Kouji Takahashi
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of EP1184900A2 publication Critical patent/EP1184900A2/de
Publication of EP1184900A3 publication Critical patent/EP1184900A3/de
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Publication of EP1184900B1 publication Critical patent/EP1184900B1/de
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/30105—Capacitance

Definitions

  • the present invention relates a protection circuit device using MOSFET and method of manufacturing the same, particularly enabling to build in a secondary battery and carrying out battery management.
  • a protection circuit device carrying out battery management of charge -discharge of the lithium ion battery must be smaller and sufficiently resist to short of load.
  • As such protection circuit device is built in vessel of lithium ion battery, miniaturization is required, and freely using COB (Chip on Board) technique using many chip parts meets require of miniaturization.
  • COB Chip on Board
  • switching element is connected to lithium ion battery in series, it is needed to make ON-state resistance of the switching element extremely small. This is indispensable factor to lengthen talking time or stand-by time in pocket telephone.
  • a protection circuit carrying out concrete battery management is shown in Fig. 19.
  • Two power MOSFETs Q1 and Q2 are connected to a lithium ion battery LiB in series to detect voltage of the lithium ion battery LiB with a control IC.
  • the detection carries out on-off control of the two power MOSFETs Q1 and Q2, and the lithium ion battery LiB is protected from over-charge, over-discharge, or load short.
  • the power MOSFETs Q1 and Q2 connect drain electrodes D in common, source electrodes S are arranged respectively at both ends thereof, and gate electrode G of each MOSFETs is connected to the control IC.
  • a power source is connected to ends of the circuit, and charge current is applied to the lithium ion battery LiB to arrow direction so as to charge.
  • charge current is applied to the lithium ion battery LiB to arrow direction so as to charge.
  • both ends of the circuit are connected to a load and operation of a pocketable terminal till designated voltage.
  • voltage is detected by the control IC, gate voltage of the power MOSFET Q1 becomes L from H, and the power MOSFET Q1 becomes off and cuts the circuit so as to protect the lithium ion battery LiB.
  • sell density was 7.4 million per a square inch and ON-state resistance was 17 m ⁇ in planer structure that a channel is formed on a semiconductor substrate surface
  • sell density is extremely improved in 25 million per a square inch and ON-state resistance is decreased in 27 m ⁇ .
  • sell density is 72 million per a square inch and ON-state resistance is decreased in 12 m ⁇ .
  • Fig. 20 is a plan view describing a protection circuit device mounting such a power MOSFET improved in sell density. Although circuit parts shown in Fig. 19 are mounted actually, the parts are not shown all in the figure.
  • a conductive path 2 comprising copper foil is formed on both face of an insulating board 1, and has multilayer interconnection where the conductive paths 2 of upper face and lower face of the board are connected through through-hole (not shown) at desired position.
  • Power MOSFETs 3 and 4 are resin-molded in an external form of SOP8 for surface mounting, two terminals 5 and 5 connected to drain electrodes go out at one side, and at the opposite side, a gate terminal 7 connected to a gate electrode and a source terminal 8 connected to a source electrode go out.
  • Symbol 9 is a control IC
  • symbol 10 are chip capacitors corresponding to C1 to C3 of Fig. 19
  • symbol 11 are chip resisters corresponding to R1 and R2 of Fig. 19.
  • Symbols 12 and 13 are external terminals corresponding to LP2 and LP3 of Fig. 19. The external terminals are fixed on pads 14 formed at part of the conductive path 2 by solder.
  • the protection circuit device is formed in a suitable shape to put in the case of the lithium ion battery, miniaturization is the largest problem for fundamental needs.
  • Fig. 21 shows a section structure of the power MOSFETs 3 and 4.
  • a frame is a pressed frame comprising NK-202 (copper 97.6%, tin 2%) as material, and a bare chip 23 of the power MOSFET is fixed with a preform material 22 comprising solder or silver paste on a header 21 of the frame.
  • a drain electrode is formed by gold lining electrode (not shown) on lower face of the bare chip 23 of the power MOSFET, and on upper face, a gate electrode and a drain electrode are formed by deposition of Aluminum.
  • a drain terminal of the frame is connected to the drain electrode directly, and the gate electrode and the source electrode are electrically connected to a gate terminal 7 and a source terminal 8 by ball bonding using gold bonding wire 24. Therefore ON-state resistance of power MOSFET is influenced ON-state resistance existing in frame material, preform material, material for the bonding wire, and electrode material of the source electrode on the upper face of the chip for decreasing ON-state resistance.
  • Fig. 22 and Fig. 23 are plan view describing the prior art decreasing ON-state resistance devising bonding wire.
  • Fig. 22 is a view where current capacity is improved by increasing the bonding wire 24 connecting the source electrode and the source electrode 8 to four wires.
  • Fig. 22 is a view where current capacity is improved by increasing the bonding wire 24 connecting the source electrode and the source electrode 8 to four wires, two short wires and long two wires, and where resistance of the source electrode is decreased by broadening bonding portion to the source electrode.
  • Sample A and Sample B are the conventional mold structure of SOP8, Sample A corresponds to the structure of Fig. 22, and Sample B corresponds to the structure of Fig. 23.
  • These figures show, in the case that bonding wires is changed to combination of two short wires and two long wires from four short wires, decrease of ON-state resistance of 1.33 m ⁇ , from 13.43 m ⁇ to 12.10 m ⁇ , however changing solder to Ag paste can not decrease ON-state resistance.
  • the invention is carried out from the aspect of above problems.
  • the object of the present invention is to provide a protection circuit device using power MOSFET for realizing low ON-state resistance and reducing size of the device.
  • the protection circuit device using a MOSFET connects two MOSFET in series and switches said both MOSFETs.
  • a conductive path having a desired pattern is provided on an insulating board, each gate electrode and each source electrode of a MOSFET chip integrating said both MOSFET in one chip are fixed on the desired conductive path, and conductive material is put on a common drain electrode provided at a back face of said MOSFET chip.
  • each gate electrode and each source electrode of a MOSFET chip integrating said both MOSFET in one chip are fixed on a conductive path having a low resistance, provided outside the chip.
  • the MOSFET chip is fixed on the conductive path by flip chip method and conductive path of common drain electrode is removed so as to realize low ON-state resistance and miaturization.
  • a protection circuit device using MOSFET connects two MOSFET and switches said both MOSFETs with a control IC.
  • a conductive path of a desired pattern buried in an insulating resin is provided, each gate electrode and each source electrode of a MOSFET chip integrating said both MOSFET in one chip are fixed on the desired conductive path, and conductive material is put on a common drain electrode provided at a back face of said MOSFET chip.
  • a method for manufacturing a protection circuit device using MOSFET has process providing a conductive foil and forming a conductive path by forming a thinner trench than thickness of said conductive foil on at least said conductive foil except area becoming the conductive path, process fixing each gate electrode and each source electrode of a MOSFET integrating two MOSFETs on said desired conductive path in one chip, process bonding conductive material on a common electrode of the MOSFET, process covering said MOSFET and molding with insulating resin so as to fill into said trench , and process removing said conductive foil of part of thickness where said trench is not provided. Therefore, efficient method for manufacturing a protection circuit device using a MOSFET is realized.
  • Fig. 1 shows a plan view of a protection circuit device using the invention. Although circuit parts are mounted as the circuit shown in Fig. 19 is realized in the protection circuit device, the parts are not shown all in the figure.
  • a conductive path 32 comprising copper foil is formed on both face of an insulating board 31, and has multilayer interconnection where the conductive paths 32 of upper face and lower face of the board are connected through through-hole (not shown) at desired position.
  • Characteristic of the invention is to mount a MOSFET chip 33 integrating power MOSFETs Q1 and Q2 of switching element in one chip with just bare chip by flip chip method.
  • FIG. 33 A structure of concrete structure of the MOSFET chip 33 is shown in Fig. 33.
  • Fig. 2A is a plan view
  • Fig. 2B is a section view cut by X-X line.
  • the MOSFET chip 33 has an N + /N semiconductor substrate 334 being drain region, a P channel region 335, a trench 336 provided passing through the channel region 335, a gate electrode 338 buried in the trench 336 through a gate oxide film 337 and comprising poly silicon, an N+ source region 339 provided adjacent to the trench 336, and P+ body region 340 forming a board diode provided adjacent to the source region 339.
  • a substrate source electrode 342 contacting the source region 339 and the body region 340 and formed by aluminum-sputtering , and a substrate gate electrode 343 connected to the gate electrode 338.
  • a barrier metal layer 344 of Pd/Ti or Au/TiW is provided, and on the layer a source electrode 331 and a gate electrode 332 of gold bump formed by gold plating of 25 ⁇ m height.
  • a drain electrode 333 is provided by deposition of Au/Cr and so on.
  • the source electrode 331 and the gate electrode 332 of the power MOSFETs Q1 and Q2 are arranged symmetrically with respect to center line Y-Y of the chip as clear from Fig. 2A, the source electrodes 331 are provided at most part of the semiconductor substrate 334, the gate electrodes 332 are provided symmetrically with respect to line largely separated at corner portions of the semiconductor substrate 334. This is for easy fixing to the conductive path corresponding by flip chip method.
  • the source electrode 331 and the gate electrode 332 may be formed with a solder electrode bonding brazing material such as solder to a conductive ball, and a source electrode 221 and a gate electrode 222 may be usual flat electrodes enabling to solder without projecting electrodes because the conductive paths 32 are electrically separated.
  • a mounting structure is shown. That is, a conductive path 32 formed by desired copper foil or conductive paste so that the circuit shown in Fig. 19 is realized on an insulating board 31 formed by glass epoxy board or ceramic board is provided. On the conductive path 32, MOSFET chip 33 is fixed, and at least MOSFET chip 33 is covered by said insulating resin 34.
  • two source electrodes 331 and two gate electrode 332 of the MOSFET chip 33 are contacted to a plural of conductive paths 32A, 32B, 32C, and 32D, and fixed by solder or the conductive paste 35.
  • solder or the conductive paste 35 fixes a conductive metal plate 36 such as copper .
  • the conductive metal plate 36 is provided in order to decrease ON-state resistance of power MOSFET Q1 and Q2 of the MOSFET chip 33 connected in series, and has an object too to improve radiation characteristic. Therefore forming by only solder or conductive paste 35 instead of the conductive metal plate 36 can achieve the object to decrease ON-state resistance.
  • thermosetting resin such as epoxy resin and thermoplastic resin such as polyimide resin and polyphenylenesulfide are used. All kinds of resin are used if they are resins hardening using a die and covering by dipping and painting.
  • the MOSFET chip 33 is fixed to the conductive path 32 by flip chip method in the mounting structure, it is not need to take the drain electrode 333 of the MOSFET chip 33 out so that the structure without using bonding wire is thin and expensive.
  • a mounting structure of the second mode for carrying out of the protecting circuit device using MOSFET of the invention is described referring Fig. 4.
  • Fig. 4 shows a mounting structure. That is, a conductive path 41 is buried in an insulating resin 40, on said conductive path 41 a MOSFET chip 33 is fixed, and the conductive path 41 is supported by said insulating resin 40.
  • the mounting structure comprises the MOSFET chip 33, a plural of conductive paths 41A, 41B, 41C, and 41D, a conductive metal plate 36, and the an insulating resin 40 burying the conductive paths 41A, 41B, 41C, and 41D. Between the conductive paths 41, a trench 42 filled with the insulating resin 40 is provided. Said conductive paths 41 are supported by the insulating resin 40.
  • thermosetting resin such as epoxy resin and thermoplastic resin such as polyimide resin and polyphenylenesulfide are used. All kinds of resin are used if they are resins hardening using a die and covering by dipping and painting.
  • a conductive foil of Cu as a main material a conductive foil of Al as a main material, or a conductive foil comprising alloy of Fe-Ni and so on is used.
  • conductive material is possible, especially conductive material enable to etch and evaporate by laser are desirable.
  • the MOSFET chip 33 where the power MOSFET Q1 and Q2 are integrated in one chip is a semiconductor bare chip having a source electrode 331 and a gate electrode 332 at front face thereof, and at entire back face, having a drain electrode 333.
  • a concrete structure of the MOSFET chip 33 is described in Fig. 2, therefore description is omitted here
  • a conductive metal plate 36 is fixed by brazing material such as solder and a conductive paste 35 such as Ag paste.
  • the conductive metal plate 36 is provided in order to decrease on-state resistance of power MOSFET Q1 and Q2 of the MOSFET chip 33 connected in series, and has an object too to improve radiation characteristic. Therefore forming by only solder or conductive paste 35 instead of the conductive metal plate 36 can achieve the object to decrease ON-state resistance. Connection of the conductive metal plate 36 to the other conductive path 41 is not need.
  • the structure consists of the conductive path 41, MOSFET chip 33, the conductive metal plate 36, and the insulating resin 40, consists of necessary minimum elements so that the structure is thin and expensive.
  • each of the conductive paths 41 is insulated by insulating resin 40 as the insulating resin 40 covers the MOSFET chip 33 and fills into said trench 42 between said conductive paths 41 so as to have function supporting in one body.
  • front face of the insulating resin 40 filled into the trench 42 and front face of the conductive path 41 are substantially in coincidence. Because of that, at mounting the mounting structure on a printed board, the structure is automatically self-aligned as the structure can rise by surface tension of brazing material such as solder and move horizontally.
  • a conductive film 37 is formed on front face of a conductive path 41, and excepting that, the structure is substantially same as the structure of Fig. 4. Therefore the conductive film 37 is described.
  • First characteristic is a point that the conductive film 37 is provided to prevent bending of a conductive path or a circuit device.
  • the mounting structure itself bends and the conductive path curves and peel off by difference of coefficient of thermal expansion between insulating resin and conductive path material (called first material hereafter).
  • first material conductive path material
  • thermal conductivity of the conductive path 41 is superior than thermal conductivity of the insulating resin
  • the conductive path 41 expands previously by temperature rise.
  • covering a second material smaller coefficient of thermal expansion than the first material can prevent bending and peeling off of the conductive path and bending of the mounting structure.
  • Au, Ni, or Pt is good for the second material.
  • Coefficient of expansion of Cu is 16.7X10 -6
  • Au is 14X10 -6
  • Ni is 12.8X10 -6
  • Pt is 8.9X10 -6 .
  • Second characteristic is a point that the structure has anchor effect by the second material. Eaves are formed by the second material, further as the eaves 38 fixing to the conductive path 41 are buried in the insulating resin 40, anchor effect appears so as to prevent the conductive path 41 removing.
  • a sheet-shaped conductive foil 50 is provided.
  • Material of the conductive foil 50 is selected considering fix ability of brazing material, bonding ability, and plating ability.
  • a conductive foil of Cu as a main material, a conductive foil of Al as a main material, or a conductive foil comprising alloy such as Fe-Ni and so on is used.
  • thickness of the conductive foil is 10 ⁇ m to 300 ⁇ m desirably, here copper foil of 70 ⁇ m (2 oz.) is adopted. However the thickness of more than 300 ⁇ m or less than 10 ⁇ m is fundamentally available. As described later, the thickness is good when the thinner trench 42 than thickness of the conductive foil 50 is formed.
  • the sheet-shaped conductive foil 50 rolled in roll shape with designated width or the conductive foil cut in designated size may be transferred to each later-mentioned process.
  • a photo resist (etching-resist mask) PR is formed on a Cu foil 50, and is patterned so that the conductive foil 50 excepting at least area becoming the conductive path 41 exposes (Refer Fig. 6 about the above.)
  • the conductive foil is etched through said photo resist PR (Refer Fig. 7 about the above.)
  • Depth of the trench 42 formed by etching is 50 ⁇ m for example, and the side thereof is coarse face so that adhesiveness to the insulating resin 40 is improved.
  • the side wall of the trench 42 is shown in straight schematically, the structure differs depending on method of removing .
  • wet etching and dry etching are used.
  • ferric chloride or cupric chloride is mainly used, and said conductive foil is dipped into the enchant or showered by the enchant.
  • the conductive foil is generally etched non-anisotropically, the trench 42 of inner part than an opening spreads, and the side face of the trench 42 becomes curved structure being side-etched.
  • both etchings of anisotropy and non-anisotropy are possible .
  • it is said impossible to remove Cu by reactive ion etching by using sputtering method, Cu can be removed easily.
  • both etchings of anisotropy and non-anisotropy can be carried out.
  • a conductive film having etching-tolerant against etching liquid may be selectively covered instead of the photo resist.
  • the conductive film acts as an etching protection film and therefore the trench can be formed without using resist.
  • Material for the conductive film is Ag, Au, Pt, or Pd.
  • the etching-tolerant conductive film can be bonded easily and therefore can be used as die pad and bonding pad alone.
  • a MOSFET chip 33 is mounted on the conductive path 41 made of the conductive foil 50 separated by the trench 42.
  • MOSFET chip 33 is a semiconductor bare chip having a source electrode 331 and a gate electrode 332 at front face thereof, and at entire back face, having a drain electrode 333. Pattern recognition is carried out by chip mounting apparatus facing the source electrode 331 and the gate electrode 332 to lower side, and the MOSFET 33 is fixed by flip chip method with brazing material such as solder or the conductive paste 35 contacting the each electrode to the conductive paths 41A and 41B, and 41C and 41D.
  • a conductive metal board 36 comprising copper is fixed on a drain electrode 333 provide at the back face of the MOSFET chip 33 by brazing material such as solder or the conductive paste 25.
  • the conductive metal plate 36 does not short with other electrode.
  • connection of the conductive metal plate36 and the conductive path 41 is not necessary, it is possible to mount easily with rough positioning using different-shaped parts mounter.
  • thermosetting resin such as epoxy resin is realizes by transfer mould
  • thermoplastic resin such as polyimide resin and polyphenylenesulfide is realized by injection mould.
  • thickness of the insulating resin 40 covered by surface of the conductive foil 50 is adjusted so as to cover about 100 ⁇ m from top portion of the circuit element. It is possible to make thickness thick or thin considering strength.
  • Characteristic of the process is that the conductive foil 50 becoming the conductive path 41 functions as a supporting board till covering the insulating resin 40.
  • the conductive path is formed using the supporting board in the past, the conductive foil 50 functioning as the supporting board is material necessary as electrode material in the invention. Therefore the invention has merit to operate making composition material as few as possible, and can realize reduction of cost.
  • the conductive foil 50 is not separated individually as the conductive path 41. Therefore the conductive foil is handled in one body as the sheet-shaped conductive foil 50, and the structure has characteristic that operation of transfer to die and mounting on die is very easy.
  • the conductive film may be formed previously at the back face of the conductive foil of Fig. 5. In this case, a part corresponding to the conductive path may be covered selectively. Method of covering is plating for example.
  • material resisting to etching is desirable.
  • the conductive path 41 can be separated only by etching without polishing.
  • MOSFET 33 is described selectively as a circuit part, actually many circuit parts necessary for the protection circuit device of the invention are mounted on the conductive foil 50 shown in Fig. 10 including matrix shape MOSFET 33.
  • Fig. 10 shows a plan view of a board of the conductive foil 50 after forming the trench 42.
  • the board has size of 45mm ⁇ 60mm, the conductive path 41 is formed at the hatching part, and the separated part 42 is formed at the white part. Therefore part becoming the mounting structure is arranged in matrix shape, 3 row 8 line, and index marks 511 and index holes using in process are provided at periphery thereof.
  • dicing lines are controlled at center of the index marks comprising two lines provided both ends of the board.
  • Fig. 11 is an enlarged plan view of a board of one conductive foil 50 of Fig. 10.
  • a MOSFET chip 33 is fixed on conductive paths 41A, 41B, 41C, and 41D shown at left side of the figure by flip chip method.
  • a control IC 9 is fixed to the conductive path 41 at center portion thereof, and at the conductive path 41 of periphery of the IC, chip capacitors corresponding to C1 to C3 of Fig. 19 and chip resistors corresponding to R1 and R2 of the Fig. 19 are fixed using a chip mounter.
  • External terminals shown at four corners with LP1,LP2, LP3, and LP4 correspond to terminals LP1,LP2, LP3, and LP4 shown in Fig. 19.
  • protection circuit device of the invention formed on the board of the conductive foil 50 shown in Fig. 10 become an individual protection circuit device using MOSFET by cutting at a part of the insulating resin 40 of the trench 42 on dicing line shown with one dot chain line to directions of X axis and Y axis using dicing machine .
  • the back face of the conductive path 41 is connected to the conductive path of the printed board by brazing material such as solder in order to use.
  • the conductive path 41 is buried in the insulating resin 40 so as to realize the mounting structure of the protection circuit device using flat MOSFET where the back face of the insulating resin 40 and the back face of the conductive path 41.
  • Characteristic of the method for manufacturing is that operation of separating the conductive path 41 can be carried out using the insulating resin 40 as a supporting board.
  • the insulating resin 40 is a necessary material for material burying the conductive path 41, and the supporting board is not need like the conventional method for manufacturing. Therefore the method has characteristic to manufacture with minimum material and to realize reduction of cost.
  • Thickness of insulating resin from surface of the conductive path is adjusted at fixing of the insulating resin of front process.
  • the MOSFET chip 33 is fixed on the conductive path 41 by flip chip method in the invention, bonding wire is excluded. Therefore depending on thickness of the MOSFET chip 33 mounted, the mounting structure has characteristic that thickness thereof is extremely made thin.
  • the mounting structure is buried in the insulating resin 40 of about 400 ⁇ m thick with the conductive path 41 of 40 ⁇ m thick and the MOSFET chip 33 of about 200 ⁇ m thick. (Refer Fig. 4 about the above.)
  • a method for manufacturing a mounting structure of a protection circuit device using MOSFET having eaves is described referring Fig.12 and Fig. 13 to Fig. 17. Except covering a second material 60 becoming eaves, the structure is substantially same as the first mode for carrying out so that concrete description is omitted.
  • a conductive foil 50 covered on the a conductive foil 50 comprising a first material with the second material 60 which is small in etching rate is provide.
  • Ni is covered on Cu foil, Cu and Ni are etched at one time by ferric chloride or cupric chloride, and difference of etching rate forms Ni in shape of eaves 38 so that it is suitable.
  • Thick solid line is the conductive film 60 comprising Ni, thickness thereof is desirable to be 1 to 10 ⁇ m. The thicker the thickness of the film of Ni, the more easily the eaves is formed.
  • the second material may cover material selectively etching with the first material.
  • eaves 38 is formed.
  • Al, Ag, and Au are considered.
  • the processes are the following: forming photo resist PR on Ni 60, patterning the photo resist so that Ni except area becoming the conductive path 41 exposes, and etching through said photo resist.
  • the separating (dicing) step can be performed by forming notches having a predetermined depth in the insulating resin by using a dicing saw, and then separating respectively by using the notches as scribe line.
  • the invention consists of minimum elements: the MOSFET chip integrating power MOSFETs Q1 and Q2 in one chip, the conductive path, the conductive metal plate, and the insulating resin.
  • the construction is a mounting structure of protection circuit device using MOSFET useful for resource. Therefore the mounting structure of the protection circuit device using MOSFET not having extra components till completion and reducing cost extremely.
  • MOSFET chip can be mounted directly with flip-chip with high accuracy.
  • bonding wire is not need, and by making thickness of film of the insulating resin and thickness of the conductive foil optimum value, height of the structure is made very thin less than 0.5 mm, and at the same time small, light mounting structure is realized.
  • the back face of the conductive path exposes from the insulating resin, the back face of the conductive path instantly connects to outside without using the back face electrode and the through-hole needed in the conventional structure.
  • the second material is formed at front side of the conductive path, bend of the mounting board, particularly bend of long and thin conductive path or peeling off is depressed by difference of coefficient of thermal expansion.
  • the eaves covered by the conductive path is formed. Therefore the eaves(visors) can cause anchor effect, and prevent bend of the conductive path and slipping out of the insulating resin.
  • the conductive foil itself becoming material of the conductive path functions as the supporting board, the conductive foil supports the whole till forming the trench or mounting of MOSFET and covering the insulating resin.
  • the insulating resin functions as the supporting board. Therefore the protection circuit device is manufactured by necessary minimum of the MOSFET chip, the conductive foil, the insulating resin.
  • the both are able to shift without touching side face of the conductive path on the mounting board at mounting. Especially in the case that the both are mounted with shifted position, it is possible to re-arrange shifting to horizontal direction. If brazing material is melted after mounting, the device mounted with shift aims to return itself to upper portion by surface tension of melted brazing material so that rearrangement by the device itself is possible.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Fuses (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP01302533A 2000-09-04 2001-03-20 Batteriesteuerungsschaltkreis mit Leistungs-MOSFETs und Verfahren zu seiner Herstellung Expired - Lifetime EP1184900B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000266709A JP3650008B2 (ja) 2000-09-04 2000-09-04 Ｍｏｓｆｅｔを用いた保護回路装置およびその製造方法
JP2000266709 2000-09-04

Publications (3)

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EP1184900A2 true EP1184900A2 (de) 2002-03-06
EP1184900A3 EP1184900A3 (de) 2004-01-21
EP1184900B1 EP1184900B1 (de) 2006-07-12

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US (2) US7211868B2 (de)
EP (1) EP1184900B1 (de)
JP (1) JP3650008B2 (de)
KR (1) KR100366173B1 (de)
CN (1) CN1199531C (de)
DE (1) DE60121396T2 (de)
TW (1) TW486923B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460689A2 (de) * 2003-03-17 2004-09-22 Analog Power Intellectual Properties Limited Elektronische Anordnungen

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3650008B2 (ja) * 2000-09-04 2005-05-18 三洋電機株式会社 Ｍｏｓｆｅｔを用いた保護回路装置およびその製造方法
US8884361B2 (en) 2002-07-19 2014-11-11 Renesas Electronics Corporation Semiconductor device
US7034344B2 (en) * 2003-07-08 2006-04-25 International Rectifier Corporation Integrated semiconductor power device for multiple battery systems
US8390131B2 (en) * 2004-06-03 2013-03-05 International Rectifier Corporation Semiconductor device with reduced contact resistance
TWI365516B (en) * 2005-04-22 2012-06-01 Int Rectifier Corp Chip-scale package
JP2007129068A (ja) * 2005-11-04 2007-05-24 Toshiba Corp 半導体装置とその製造方法、及びその製造に用いる基板
US8426960B2 (en) * 2007-12-21 2013-04-23 Alpha & Omega Semiconductor, Inc. Wafer level chip scale packaging
JP4804497B2 (ja) * 2008-03-24 2011-11-02 ルネサスエレクトロニクス株式会社 半導体装置
US8547068B2 (en) 2008-09-18 2013-10-01 Samsung Sdi Co., Ltd. Protection circuit module and secondary battery including the protection circuit module
US8723300B2 (en) * 2012-08-13 2014-05-13 Fairchild Semiconductor Corporation Multi-chip module power clip
JP2013070101A (ja) * 2013-01-10 2013-04-18 Renesas Electronics Corp 半導体装置
US20150132614A1 (en) * 2013-11-12 2015-05-14 Infineon Technologies Ag Sensor arrangement, energy system and method
US9614256B2 (en) * 2014-03-31 2017-04-04 Infineon Technologies Ag Lithium ion battery, integrated circuit and method of manufacturing a lithium ion battery
CN106158804B (zh) 2015-04-02 2018-11-16 台达电子工业股份有限公司 一种半导体封装结构及其半导体功率器件
WO2016203764A1 (ja) * 2015-06-17 2016-12-22 パナソニックＩｐマネジメント株式会社 半導体装置及びモジュール部品
JP2017130527A (ja) * 2016-01-19 2017-07-27 力祥半導體股▲フン▼有限公司ＵＢＩＱ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐ． 半導体装置
JP7135636B2 (ja) * 2018-09-14 2022-09-13 富士電機株式会社 半導体装置
US11742267B2 (en) 2020-10-12 2023-08-29 Toyota Motor Engineering And Manufacturing North America, Inc. Power electronics assembly having flipped chip transistors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889962A (en) * 1988-08-19 1989-12-26 Northern Telecom Limited Circuit board with coaxial circuit and method therefor
US5179032A (en) * 1990-02-01 1993-01-12 Quigg Fred L Mosfet structure having reduced capacitance and method of forming same
EP0717497A2 (de) * 1994-12-14 1996-06-19 Hitachi, Ltd. Zusammengesetzter Leistungs-MOSFET
DE19607974A1 (de) * 1995-03-03 1996-09-05 Mitsubishi Electric Corp Körper für eine Verdrahtungsanordnung, Verfahren zu dessen Herstellung und Leiterplatte, bei der der Körper für eine Verdrahtungsanordnung verwendet wird
US6046071A (en) * 1993-06-01 2000-04-04 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107866A (ja) * 1983-11-17 1985-06-13 Toshiba Corp 半導体装置
GB2207315B (en) 1987-06-08 1991-08-07 Philips Electronic Associated High voltage semiconductor with integrated low voltage circuitry
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
EP0591862B1 (de) * 1992-10-02 1999-05-26 Matsushita Electric Industrial Co., Ltd. Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung
JP3443238B2 (ja) 1996-06-20 2003-09-02 三洋電機株式会社 保護回路を備えるパック電池
JPH1032223A (ja) * 1996-07-15 1998-02-03 Mitsubishi Electric Corp 半導体装置
JPH10117443A (ja) 1996-08-20 1998-05-06 Shin Kobe Electric Mach Co Ltd 二次電池の過充電及び過放電防止装置
US5939753A (en) * 1997-04-02 1999-08-17 Motorola, Inc. Monolithic RF mixed signal IC with power amplification
JP3413569B2 (ja) * 1998-09-16 2003-06-03 株式会社日立製作所 絶縁ゲート型半導体装置およびその製造方法
US6269011B1 (en) * 1999-02-14 2001-07-31 Yazaki Corporation Power supply system having semiconductor active fuse
US6548328B1 (en) 2000-01-31 2003-04-15 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US6396138B1 (en) * 2000-02-15 2002-05-28 International Rectifier Corporation Chip array with two-sided cooling
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6436734B1 (en) 2000-08-22 2002-08-20 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
JP3650008B2 (ja) 2000-09-04 2005-05-18 三洋電機株式会社 Ｍｏｓｆｅｔを用いた保護回路装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889962A (en) * 1988-08-19 1989-12-26 Northern Telecom Limited Circuit board with coaxial circuit and method therefor
US5179032A (en) * 1990-02-01 1993-01-12 Quigg Fred L Mosfet structure having reduced capacitance and method of forming same
US6046071A (en) * 1993-06-01 2000-04-04 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
EP0717497A2 (de) * 1994-12-14 1996-06-19 Hitachi, Ltd. Zusammengesetzter Leistungs-MOSFET
DE19607974A1 (de) * 1995-03-03 1996-09-05 Mitsubishi Electric Corp Körper für eine Verdrahtungsanordnung, Verfahren zu dessen Herstellung und Leiterplatte, bei der der Körper für eine Verdrahtungsanordnung verwendet wird

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460689A2 (de) * 2003-03-17 2004-09-22 Analog Power Intellectual Properties Limited Elektronische Anordnungen
EP1460689A3 (de) * 2003-03-17 2005-07-20 Analog Power Intellectual Properties Limited Elektronische Anordnungen
US6963140B2 (en) 2003-03-17 2005-11-08 Analog Power Intellectual Properties Transistor having multiple gate pads

Also Published As

Publication number Publication date
DE60121396D1 (de) 2006-08-24
CN1199531C (zh) 2005-04-27
JP3650008B2 (ja) 2005-05-18
CN1342037A (zh) 2002-03-27
DE60121396T2 (de) 2007-07-05
JP2002076340A (ja) 2002-03-15
KR100366173B1 (ko) 2002-12-31
US7211868B2 (en) 2007-05-01
US20050029588A1 (en) 2005-02-10
EP1184900A3 (de) 2004-01-21
US20020053744A1 (en) 2002-05-09
TW486923B (en) 2002-05-11
KR20020018930A (ko) 2002-03-09
EP1184900B1 (de) 2006-07-12

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