EP1143405B1 - Driving method and apparatus for a multiplexed display with normal working mode and standby mode - Google Patents

Description

The present invention generally relates to a method and a device for controlling a multiplexed display device. By "multiplexed display device" or more simply "multiplexed display", will be understood within the context of the present description, a multi-line display device, that is to say a display device having a number of display lines greater than unity, controlled by multiplexing. By "multiplexing" it will be understood here that the control signals of the display are multiplexed in time. We will also talk about "dynamic" display.

The present invention applies to any type of multiplexed display, regardless of its size. In particular, the present invention is advantageously applied to multiplexed liquid crystal displays (LCDs).

Referring to the figure 1 , there is illustrated a conventional dynamic display device 10. The illustrated display typically includes a first display section 10A and a second display section 10B. This display 10 is of a conventional type found for example in a cell phone. The first display section 10A is thus a display section comprising predefined symbols, for example symbols intended to indicate the reception level of the cellular telephone, the battery life, the arrival of a call, the time, or other information that is typically permanently displayed on the display when the device is turned on. The second display section 10B is typically a matrix type display section for displaying alpha-numeric and / or graphical data such as a caller's number, a short message, etc. The first and second display sections are typically physically interconnected to form a single composite display having a symbol section and a matrix section for displaying alpha-numeric messages.

The display shown at figure 1 thus typically presents a set of segments or pixels arranged in rows and columns. In order to activate these segments and pixels, a plurality of row and column electrodes (not shown) are respectively coupled to the rows and columns of the display. In the case of an LCD display, these line and column electrodes are for example arranged on opposite plates between which is arranged the liquid crystal layer. Voltages applied to the row and column electrodes combine to generate an electric field in an area between the electrodes. This area between electrodes is referred to as "pixel" or "segment" depending on the geometry of the area. Thus, in the case of the first display section 10A including the symbols, it will be preferable to speak of "segments" whereas in the case of the second display section 10B, preference will be given to "pixels". Nevertheless, in both cases, the voltages applied to the row and column electrodes combine to selectively enable or disable pixels or segments of the display. As a simplification, the term "pixel" will be used in the rest of this description to indicate indifferently a pixel or a segment of the display.

It will be understood that the terms "line" and "column" are used to indicate that the pixels are arranged in a matrix form and are controlled by pairs of electrodes, each pixel being located at an intersection of a pair of line electrodes and column. In some displays, these pairs of electrodes may, however, be denominated differently, for example by the terms "anterior electrode" and "posterior electrode", or "frontplane electrode" and "backplane electrode" in English terminology. In the context of the present description, the terms "line electrode" and "column electrode" refer to any type of electrode arrangement, including arrangements where the electrodes are not arranged in a linear fashion. It will also be understood that the terms "line" and "column" do not necessarily imply that a line extends horizontally and that a column extends vertically. The terms "line" and "column" can therefore perfectly be interchanged.

Dynamic displays that have just been briefly presented, such as LCD displays, are frequently used in many battery-powered products, such as calculators, electronic pocket diaries, cell phones, electronic timepieces, etc. . A significant advantage of such display devices is their relative low power allowing the products incorporating them to operate sustainably using their battery or operate with smaller batteries.

The current trend is to produce powerful devices, of small dimensions and whose power consumption is as small as possible. One way to save power in a device incorporating a dynamic display such as an LCD display would be to completely turn off the power of the display pixels that are in sleep mode or that are not otherwise used. However, it is realized in practice that it is not possible to completely cut the power of the pixels. In practice, in fact, the pixels, in particular the pixels of an LCD display, must typically be controlled by an alternative control signal of zero DC, even when these are in the "off" state. If the control signal had a non-zero DC component, it could result in particular a residual polarization of the display that would make the latter not operational.

Control signals conventionally applied to the row and column electrodes are in the form of a succession of alternating frames so that the resulting average voltage on a pixel taken over a period encompassing two successive frames is zero. More specifically, from one frame to another, the signal is reversed or inverted with respect to the signal generated during the previous frame. In the remainder of the description, a series of two successive frames will be defined as a cycle, this cycle being thus divided into a first half-cycle corresponding to a first frame and a second half-cycle corresponding to a reverse frame with respect to the first one.

According to this conventional control technique, the non-active pixels are typically kept in the "off" state by the application of voltages such that the resulting voltage on the non-active pixel has an amplitude too small to put it in the "state". we". Each pixel of the display, whether in the "on" or "off" state, thus typically sees abrupt and frequent switching of voltage levels at its terminals, each of these switching consuming energy.

The document US Patent 5,805,121 thus suggests a method for controlling an aforementioned dynamic display by which the number of switches on the pixels, in particular on the pixels set to the "off" state, is substantially reduced. Although a significant reduction in consumption is achieved through the teaching of this document, there is still a need to find more optimal solutions and to reduce even more significantly the consumption of such multiplexed displays.

It may be noted in particular that a disadvantage of the control technique proposed in the document US Patent 5,805,121 , taking the example presented in figure 5 of this document lies in the fact that during three-quarters of a control cycle, the control signals applied to the row electrodes are all maintained at non-energizing voltage levels. This fraction of the cycle during which the signals are held at these levels of non-activation is all the more important as the number of display lines set to the non-active state is important (in the example of the figure 5 , this number is three non-active display lines out of four). It can thus be seen that the time devoted to the control of still active display lines is not optimized with respect to the total duration of a control cycle.

A general object of the present invention is therefore to propose a method of control of a multiplexed display which overcomes the disadvantages of control techniques of the prior art and which responds, in particular, both to a desire to reduce consumption and to a desire to optimize the control of a such multiplexed display.

This object is achieved, according to the present invention, by the control method whose characteristics are set forth in claim 1.

Another object of the present invention is to provide a control device for a multiplexed display for implementing the aforementioned method.

This object is achieved, according to the present invention, thanks to the control device whose characteristics are set forth in claim x.

Advantageous variants of the method and the control device according to the present invention are the subject of the dependent claims.

An advantage of the technique proposed by the invention lies in the fact that the control of the display not only ensures a significant reduction in consumption but also an optimal control of the display. These two effects are ensured by an adequate control of the multiplexing rate of the display as will be seen in more detail later in this description.

• la figure 1, déjà présentée, montre un exemple conventionnel d'un dispositif d'affichage multiplexé;
• la figure 2 montre un exemple d'un dispositif d'affichage multiplexé comportant vingt-quatre lignes et cinq colonnes, utilisé dans le cadre d'un mode de mise en oeuvre particulier pour illustrer le principe de fonctionnement de la présente invention;
• les figures 3A et 3B illustrent, dans un premier mode de fonctionnement dit normal où les vingt-quatre lignes de l'affichage sont actives, des exemples de signaux pouvant être appliqués respectivement sur les lignes et sur les colonnes de l'affichage de la figure 2 pour sélectivement activer ou désactiver des pixels de cet affichage;
• la figure 3C illustre, dans le premier mode de fonctionnement, les signaux présents aux bornes de trois pixels de l'affichage de la figure 2, ces signaux résultant de la combinaison des signaux, illustrés aux figures 3A et 3B, appliqués sur les lignes et colonnes correspondantes de l'affichage;
• les figures 4A et 4B illustrent, dans un deuxième mode de fonctionnement dit de veille où seules les huit premières lignes de l'affichage sont actives, des exemples de signaux pouvant être appliqués respectivement sur les lignes et sur les colonnes de l'affichage de la figure 2 pour sélectivement activer ou désactiver des pixels de cet affichage;
• la figure 4C illustre, dans le deuxième mode de fonctionnement, les signaux présents aux bornes de trois pixels de l'affichage de la figure 2, ces signaux résultant de la combinaison des signaux, illustrés aux figures 4A et 4B, appliqués sur les lignes et colonnes correspondantes de l'affichage;
• les figures 5A et 5B illustrent, dans le deuxième mode de fonctionnement dit de veille où seules les huit premières lignes de l'affichage sont actives, d'autres exemples de signaux pouvant être appliqués respectivement sur les lignes et sur les colonnes de l'affichage de la figure 2 pour sélectivement activer ou désactiver des pixels de cet affichage;
• la figure 5C illustre, dans le deuxième mode de fonctionnement, les signaux présents aux bornes de trois pixels de l'affichage de la figure 2, ces signaux résultant de la combinaison des signaux, illustrés aux figures 5A et 5B, appliqués sur les lignes et colonnes correspondantes de l'affichage;
• la figure 6 montre schématiquement un exemple de réalisation d'un dispositif de commande d'un affichage multiplexé permettant de mettre en oeuvre le procédé de commande selon la présente invention.

Other features and advantages of the present invention will appear more clearly on reading the detailed description which follows, made with reference to the accompanying drawings given by way of non-limiting examples and in which:

• the figure 1 , already presented, shows a conventional example of a multiplexed display device;
• the figure 2 shows an example of a multiplexed display device having twenty-four lines and five columns, used in the context of a particular embodiment to illustrate the operating principle of the present invention;
• the Figures 3A and 3B illustrate, in a first normal operating mode where the twenty-four lines of the display are active, examples of signals that can be applied respectively to the rows and columns of the display of the display. figure 2 to selectively enable or disable pixels of this display;
• the figure 3C illustrates, in the first mode of operation, the signals present at the terminals of three pixels of the display of the figure 2 , these signals resulting from the combination of the signals, illustrated in Figures 3A and 3B , applied to the corresponding rows and columns of the display;
• the Figures 4A and 4B illustrate, in a second mode of operation says when only the first eight lines of the display are active, examples of signals that can be applied respectively to the lines and columns of the display of the display. figure 2 to selectively enable or disable pixels of this display;
• the figure 4C illustrates, in the second mode of operation, the signals present at the terminals of three pixels of the display of the figure 2 , these signals resulting from the combination of the signals, illustrated in Figures 4A and 4B , applied to the corresponding rows and columns of the display;
• the Figures 5A and 5B illustrate, in the second mode of so-called standby operation where only the first eight lines of the display are active, other examples of signals that can be applied respectively to the rows and columns of the display of the figure 2 to selectively enable or disable pixels of this display;
• the Figure 5C illustrates, in the second mode of operation, the signals present at the terminals of three pixels of the display of the figure 2 , these signals resulting from the combination of the signals, illustrated in Figures 5A and 5B , applied to the corresponding rows and columns of the display;
• the figure 6 schematically shows an exemplary embodiment of a control device of a multiplexed display for implementing the control method according to the present invention.

We will first describe by means of the figure 2 and FIGS. 3A to 3C and 4A to 4C , the control method according to the present invention. The figure 2 shows for explanatory purposes a nonlimiting example of a multiplexed display, designated generally by the reference numeral 10, comprising a plurality of pixels arranged in twenty-four lines, designated 101 to 124 and in five columns, designated 201 to 205. Like this is schematized on the figure 2 , some pixels, shown in black in the figure, are in the state "ON", that is to say in a state said active. Other pixels, shown in white in the figure, are in the "OFF" state, that is to say in an inactive state. In the remainder of the present description, particular attention will be given to the pixels designated by the references 11, 12 and 13 selected from the set of pixels of the display to illustrate the control method according to the present invention. The pixel 11 is thus at the intersection of the line 101 and the column 204, the pixel 12 at the intersection of the line 108 and the column 202 and the pixel 13 at the intersection of the line 124 and column 204. It will be noted that the pixel 12 is active while the pixels 11 and 13 are inactive.

We did not show in the display 10 of the figure 2 of lines of symbols. It will be understood, however, that the first line 101 of the display may for example correspond to a line of symbols according to the illustration of FIG. figure 1 for example. It will be recalled here again that the term "pixel" encompasses both a pixel of a matrix type display and a segment of a display consisting of specific symbols.

The pixels are coupled to line electrodes and to column electrodes (not shown), each of which is provided with a line signal, respectively a column signal, the combination of which defines the activation state of the pixel at the center of the column. intersection of the corresponding line and column.

The lines 101 to 124 of the display are sequentially activated by means of line signals applied to the corresponding line electrodes (not shown) of the display 10 of the display. figure 2 . These line signals will be designated in the rest of the description by the references BP1 to BP24, the signal BP1 corresponding to the line signal applied to the electrode of line 101, the signal BP2 to the line signal applied to the electrode of line 102 and so on until the signal BP24 applied to the electrode of line 124.

The figure 3A illustrates, in a first mode of operation of the so-called normal display, the appearance of the line signals applied to the row electrodes of the display. For the sake of simplification, in the figure 3A only the line signals BP1, BP2, BP8 to BP10 and BP24 respectively applied to the electrodes of lines 101, 102, 108 to 110 and 124 have been shown. Those skilled in the art will be perfectly able to deduce the looks for the remaining line signals from the information given here.

Each of the line signals BP1 to BP24 can take up to four distinct voltage levels VLCD, V1, V4 and VSS. The VLCD and VSS voltages constitute activation levels and the voltages V1 and V4 of the non-activation levels. It will be understood that a pixel can be activated by an appropriate column signal only if the corresponding line signal is simultaneously brought to the activation voltage level VLCD, respectively VSS. In the example shown in FIGS. 3A to 3C , the non-activation voltages V1 and V4 are respectively defined at 83% and 17% of the activation voltage VLCD, VSS being chosen as a reference at 0 Volt.

During a first half-cycle, designated A in the figure 3A the line signals BP1 to BP24 thus vary between the activation voltage VSS and the non-activation voltage V1. During the next half-cycle, designated B in the figure 3A , the line signals BP1 to BP24 vary between the activation voltage VLCD and the non-activation voltage V4.

More specifically, the line signal BP1 is briefly brought to the activation voltage VSS for a determined duration T at the beginning of the first half-cycle A in order to activate the line 101 of the display, then remains constant at the voltage of no activation V1 during the remainder of the half-cycle A. During the following half-cycle B, the line signal BP1 is reversed relative to the preceding half-cycle, that is to say that the signal BP1 briefly passes to the voltage d VLCD activation for a determined duration T at the beginning of the next half-cycle B, then remains constant at the non-activation voltage V4 during the remainder of the half-cycle B.

In order to activate the line 102 of the display, the line signal BP2 is briefly brought to the activation voltage VSS, respectively to the activation voltage VLCD, during the first half-cycle A, respectively during the second half-cycle B, just after the passage of the BP1 line signal to these same activation levels. The remaining line signals BP3 to BP24 are arranged in an analogous manner, the line signal BP24 thus being brought to the activation levels VSS, VLCD at the end of each half-cycle A, B.

It will therefore be understood that each line signal BP1 to BP24 is sequentially fed once during half a cycle A, B, for a determined duration T, to the activation voltage VSS, VLCD, so that the lines of the display are sequentially activated once during a half-cycle period.

The duration T during which the line signal is brought to the activation voltage is determined by the duration of each half-cycle, that is to say by the frame frequency of the display, as well as by the number of lines of the display, here at the number of twenty-four. In the example illustrated, it will therefore be understood that each line signal is brought to the activation voltage VSS, VLCD during 1 / 24th of the half-cycle period. The rest of the time the line signal is brought to the voltage of no activation V1, resp. V4.

In summary, it will therefore be understood that the lines are sequentially activated during each half-cycle, the activation and non-activation levels being alternated from one half cycle to another. At a given moment, only one line of the display is thus activated, the other lines being all controlled by the non-activation voltage V1, V4.

Appropriate column signals are applied to the electrodes (not shown) of columns 201 to 205 of the display 10 to selectively enable or disable the pixels of the display. These line signals will be designated in the rest of the description by the references FP1 to FP5, the signal FP1 corresponding to the column signal applied to the electrode of the column 201, the signal FP2 to the column signal applied to the electrode of the column. the column 202 and so on up to the FP5 signal applied to the electrode of the column 205.

The figure 3B illustrates, also in the first mode of operation of the display, the shape of the column signals FP1 to FP5 applied to the electrodes of FIG. column (not shown) of the display 10 of the figure 2 . Also for the sake of simplification, in the figure 3B only the column signals FP2 and FP4 respectively applied to the electrodes of the columns 202 and 204, that is to say the electrodes comprising in particular the pixels 11, 12 and 13 taken by way of example, have been represented. The skilled person will be perfectly able to deduce the pace of the remaining column signals from the figure 2 and some figure 3B .

We will also see, from figure 3B , that the FP1 to FP5 column signals can also take up to four distinct voltage levels VLCD, V2, V3 and VSS. The voltages V2 and V3 also constitute non-activation levels. It will be understood that a pixel can be activated by an appropriate line signal only if the corresponding column signal is simultaneously brought to the activation voltage level VLCD or VSS, according to the half cycle considered. In the example shown in FIGS. 3A to 3C , the non-activation voltages V2 and V3 are respectively defined at 66% and 34% of the activation voltage VLCD.

During the first half-cycle A, the column signals FP1 to FP5 thus vary between the activation voltage VLCD and the non-activation voltage V2. During the following half-cycle B, the column signals FP1 to FP5 vary between the activation voltage VSS and the non-activation voltage V3.

More specifically, the line signal FP2 illustrated in FIG. figure 3B at the time intervals determined during the first half-cycle A, the activation voltage VLCD is activated in order to activate the corresponding pixels in the display column 202, namely the pixels of the lines 102 and 106 to 108. The rest of the time, during this first half-cycle A, the column signal is brought to the non-activation level V2. During the following half-cycle B, the column signal FP2 is reversed with respect to the preceding half cycle, that is to say that the signal FP2 is brought to the activation voltage VSS at the determined time intervals corresponding to the activation of the pixels of the lines 102 and 106 to 108, this signal FP2 being brought the rest of the time to the non-activation level V3.

Similarly, the FP4 column signal shown in FIG. figure 3B at the time intervals determined during the first half-cycle A, the activation voltage VLCD is turned on in order to activate the corresponding pixels in the column 204 of the display, namely the pixels of the lines 102 and 104, this FP4 signal remaining at the level of non-activation V2 the rest of the time. During the following half-cycle B, the signal FP4 is reversed and is thus brought to the activation level VSS at the time intervals corresponding to the activation of the pixels of the lines 102 and 104, this signal FP4 being brought the rest of the time to level of non-activation V3.

It will therefore be understood that each column signal FP1 to FP5 is brought selectively, during a half-cycle A, B, at the activation voltage VLCD, VSS, in order to activate the corresponding pixels in each of the columns 201 to 205 of the display. It will thus be understood that the signals enabling the activation and deactivation of the pixels in a column are multiplexed in time on each column signal FP1 to FP5.

The elementary duration during which the column signal is brought to the activation voltage VLCD, resp. VSS, to enable the activation of a determined pixel in the column, corresponds to the duration T previously defined in relation to the line signals BP1 to BP24, that is to say 1 / 24th of the period of a half -cycle in this example. In other words, each half-cycle A, B is decomposed in this operating mode into twenty-four sub-periods corresponding to the twenty-four pixels that can be activated in each column of the display.

It will also be understood that the interval during which each of the line signals BP1 to BP24 is brought to the activation level VSS, resp. VLCD appears sequentially in the line signals BP1 to BP24 at each of these twenty-four sub-periods.

In the remainder of the description, "multiplexing rate" will be understood to mean a parameter determined by the number of so-called active lines of the display and defining, strictly speaking, the number of active lines multiplexed on the column signals FP1 to FP5. Thus, in the so-called normal operating mode, illustrated by the FIGS. 3A to 3C , the twenty-four lines 101 to 124 of the display are active. In such a case, we will speak of a multiplexing rate of 1:24. It will be noted that the duration T previously defined with respect to the line signals BP1 to BP24, is also the elementary duration during which the column signals are brought to the activation voltage to enable the activation of a determined pixel in the column. , is directly related to this parameter. It will thus be deduced directly from a multiplexing ratio of 1:24 that twenty-four active display lines are controlled and that consequently each half-cycle of the line signals BP1 to BP24 and column FP1 and FP5 is decomposed into twenty-four sub-periods.

The multiplexing rate thus determines the appearance of the line signals BP1 to BP24 as well as the intervals during which the column signals FP1 to FP5 must be brought to the activation level VLCD, resp. VSS, to selectively enable pixels.

In the remainder of the description, it will be seen that, according to the present invention, in at least a second mode of so-called standby operation in which a set of lines among the lines of the display is deactivated, the multiplexing rate is reduced by proportion of the number of inactive lines. According to the mode of implementation In particular, only eight lines of the display will remain active in this standby mode of operation. According to this illustrative embodiment of the present invention, the multiplexing rate will therefore be reduced to 1: 8, meaning that each half-cycle A, B is then decomposed into eight sub-periods. The Figures 4A to 4C will subsequently highlight this point.

It will of course be understood that the invention is not limited to the modes of implementation described hereinafter in the description, namely modes of implementation where only eight lines are active in standby mode of operation. Those skilled in the art will be perfectly able to adapt the method as well as the device according to the present invention so that a different number of lines are active in standby operation mode.

The figure 3C illustrates the signals at the terminals of the pixels 11, 12, 13 resulting from the combination of the corresponding line and column signals. The three signals represented thus correspond respectively to the signal present at the terminals of the pixel 11 resulting from the difference FP4-BP1 of the column signal FP4 and the line signal BP1, to the signal present at the terminals of the pixel 12 resulting from the difference FP2-BP8 of FIG. column signal FP2 and the line signal BP8 and the signal present at the terminals of the pixel 13 resulting from the difference FP4-BP24 of the column signal FP4 and the line signal BP24.

From the examination of the figure 3C the following findings can be made. As already mentioned in the preamble, the levels of the VSS, VLCD and non-activation voltages V1 to V4 are chosen so that the resulting signals at the terminals of the pixels have, over a period of two successive half-cycles. , that is to say over a period including the half-cycles A and B of the figure 3C , a mean value substantially zero.

More specifically, the levels of non-activation V1 to V4 are chosen, in the example illustrated in FIGS. FIGS. 3A to 3C as fractions of the activation voltage VLCD (VSS being set as 0 Volt reference) and so that the resulting signal across each pixel is +/- V4 during twenty-three of the twenty-four sub-periods of each half-cycle, and +/- VLCD or +/- V2 during one of the twenty-four sub-periods depending on whether the pixel is respectively active or inactive. To satisfy this condition, it will be noted that the non-activation voltages V1, V2 and V3 are respectively VLCD-V4, VLCD-2V4 and 2V4.

As a result of this choice, the signal present at the terminals of each pixel during the half-cycle B is inverted with respect to the previous half-cycle A. The average value of the signal over a period encompassing the half cycles A, B is therefore effectively nothing.

Referring to the first signal of the figure 3C illustrating the signal FP4-BP1 present at the terminals of the pixel in the non-active state 11, it can be seen that during the first half-cycle A, this signal is at + V2 during the first sub-period of the half-cycle, and then varies between +/- V4 during the remaining twenty-three subperiods. During the next half-cycle B, the signal is inverted with respect to the previous half-cycle A.

Similarly, referring to the third signal of the figure 3C , illustrating the signal FP4-BP24 present at the terminals of the pixel in the non-active state 13, it is found that this signal is at + V2, respectively -V2, during the last sub-period of the first half-cycle A, respectively of the half next cycle B, this signal being at +/- V4 the rest of the time.

Referring to the second signal of the figure 3C , illustrating the signal FP2-BP8 present at the terminals of the pixel in the active state 12, it can be seen that during the half-cycles A, B, this signal is at + VLCD, respectively -VLCD, during the eighth sub-period of the half -cycle, and varies between +/- V4 during the other twenty-three sub-periods.

According to the present invention, in at least a second so-called standby mode of operation, a set of lines, said non-active, among the lines 101 to 124 of the display is deactivated. In the example shown in figure 2 , for example, it has been decided to deactivate the lines 109 to 124 of the display 10 and to keep active only the first eight lines of the display, namely the lines 101 to 108.

It will be understood of course that the skilled person is free to choose the number of lines to be disabled and what will actually be the lines of the display that will be disabled. The Figures 4A to 4C only illustrate one choice among others. For example, it may be possible to keep active the first line 101 (such as a line of symbols) as well as the last seven lines 118 to 124 of the display.

In the Figures 4A to 4C for the sake of simplification, it has been chosen to represent the signals with an identical number of activation and non-activation levels. These activation and non-activating levels are also designated VSS, VLCD and V1, V2, V3, V4 respectively. Note however that the distribution of non-activation levels V1 to V4 is different in this second mode of operation. In the example shown in Figures 4A to 4C , the non-activation voltages V1 to V4 are respectively defined at 90%, 80%, 20% and 10% of the activation voltage VLCD. The reasons for this choice, which is in no way restrictive, will be presented later. It will be sufficient for the moment to understand that this distribution of the non-activation voltage V1 to V4 is chosen in this way in order to compensate for the increase in contrast of the display when switching from the normal operating mode to the standby operating mode. .

It will be seen later that the reduction of the multiplexing rate leads in addition to reducing the activation voltage VLCD, this being an additional advantage over the state of the art in order to reduce the consumption of the display.

The signals applied to the columns 201 to 205 of the display as well as the signals applied to the active lines 101 to 108 of the display are similar to the signals applied during the first operating mode or normal mode. However, unlike the first mode of operation, the rate of multiplexing is reduced in proportion to the number of deactivated lines. In this embodiment of the present invention, the multiplexing rate is thus reduced as an example of 1:24, in normal operating mode, to 1: 8 in standby mode of operation. As a result, the appearance of the line signals BP1 to BP8 and the column signals FP1 to FP5 is modified as illustrated in FIGS. Figures 4A and 4B . Each half-cycle A, B of the line signals BP1 to BP8, respectively column signals FP1 to FP5, is thus decomposed, in this second mode of operation, into eight sub-periods.

The Figure 4A illustrates, in the second mode of operation of the display, the appearance of the line signals BP1 to BP24 applied to the row electrodes of the display. For the sake of simplification, in the Figure 4A only the line signals BP1, BP2, BP8 to BP10 and BP24 respectively applied to the electrodes of the lines 101, 102, 108 to 110 and 124 respectively have been shown. Those skilled in the art will be perfectly able to deduce the looks for the remaining line signals from the information given here.

The appearance of the line signals BP1 to BP8 applied in the second mode of operation to the active lines 101 to 108 of the display is similar to the appearance of the line signals BP1 to BP24 applied on the lines 101 to 124. in the first mode of operation. However, according to the embodiment of the invention used here by way of example, since the multiplexing rate is reduced to 1: 8 in this second mode of operation, it can be seen that the duration T during which each of the line signals BP1 to BP8 is brought to the activation level VSS, resp. VLCD is greater, in this second mode of operation, with respect to this same duration T, in the first mode of operation.

During the first half-cycle A, the line signals BP1 to BP8 vary between the activation voltage VSS and the non-activation voltage V1. During the next half-cycle B, the line signals BP1 to BP8 vary between the activation voltage VLCD and the non-activation voltage V4.

More specifically, the line signal BP1 is briefly brought, at the beginning from each half-cycle A, B, to the activation voltage VSS, resp. VLCD, during 1 / 8th of the period of the half cycle to activate the line 101 of the display, then remains constant at the voltage of no activation V1, resp. V4 during the rest of the half cycle.

In order to activate the line 102 of the display, the line signal BP2 is briefly brought to the activation voltage VSS, resp. VLCD, during each half cycle A, B, just after the passage of the BP1 line signal to these same activation levels. The line signals BP3 to BP8 are arranged analogously, the line signal BP8 thus being brought to the activation levels VSS, resp. VLCD, at the end of each half cycle A, B, as illustrated in the Figure 4A .

It will thus be understood that each line signal BP1 to BP8 is sequentially fed once during half a cycle A, B, during 1 / 8th of the period of half a cycle, to the activation voltage VSS, VLCD, of such that the active lines 101 to 108 of the display are sequentially activated once during a half-cycle period.

In order to keep the lines 109 to 124 of the display inactive, in this second mode of operation, the signals of non-line activation are applied to the electrodes of the corresponding lines 109 to 124. These signals are chosen so that, when combined with the column signals FP1 to FP5, each pixel in these idle lines 109 to 124 receives at its terminals a signal whose amplitude is too small to activate it. For this purpose, non-line activation signals are applied which, during the entire duration of the first half-cycle A, to the non-activation level V1, then, throughout the duration of the next half-cycle B, to the level of non-activation V1. de-activation V4.

The Figure 4B illustrates, also in the second mode of operation of the display, the appearance of the column signals FP1 to FP5 applied to the column electrodes (not shown) of the display 10 of the figure 2 . Also for the sake of simplification, in the Figure 4B only the column signals FP2 and FP4 respectively applied to the electrodes of the columns 202 and 204, that is to say the electrodes comprising in particular the pixels 11, 12 and 13 taken by way of example, have been represented. The skilled person will be perfectly able to deduce the pace of the remaining column signals from the figure 2 and some Figure 4B .

Apart from the activation and non-activation levels, the appearance of the column signals FP1 to FP5 applied in the second mode of operation to the columns 201 to 205 of the display is similar to the pace of the applied signals. on these same columns in the first mode of operation. However, according to the embodiment of the invention used here by way of example, since the rate of multiplexing is reduced to 1: 8 in this second mode of in operation, it can be seen that the time intervals during which the column signals FP1 to FP5 are brought to the activation levels VLCD, VSS in order to activate the desired pixels are greater, in this second mode of operation, with respect to these same intervals, in the first mode of operation.

It may be considered that the line signals BP1 to BP8 as well as the column signals FP1 to FP5, in the second mode of operation, are obtained by spreading the first eight half-cycles of the first eight cycles. sub-periods of these same signals, in the first mode of operation.

Referring now to the figure 4C the appearance of the signals across the pixels 11, 12, 13 resulting from the combination of the corresponding line and column signals will be examined.

It will be noted first of all that all the signals present at the terminals of the pixels have, over a period of two successive half-cycles, a mean value that is substantially zero. It will be seen, on the other hand, that the signals of the figure 4C have a similar appearance to the signals of the figure 3C , if we consider only the first eight sub-periods of these signals.

Referring to the first signal of the figure 4C illustrating the signal FP4-BP1 present at the terminals of the pixel in the non-active state 11, it can be seen that during the first half-cycle A, this signal is at + V2 during the first sub-period of the half-cycle, and then varies between +/- V4 during the remaining seven subperiods. During the next half-cycle B, the signal is inverted with respect to the previous half-cycle A.

Similarly, referring to the second signal of the figure 4C , illustrating the signal FP2-BP8 present at the terminals of the pixel in the active state 12, it is noted that this signal is at + VLCD, respectively -VLCD, during the eighth and last sub-period of the first half-cycle A, respectively of the next half-cycle B, this signal being at +/- V4 the rest of the time.

Referring to the third signal of the figure 4C illustrating the signal FP4-BP24 present at the terminals of the pixel in the non-active state 13, it will be seen that, following the reduction of the multiplexing rate, the signal present at the terminals of the pixel 13 varies only between +/- V4 and shows more peak at +/- V2 at the end of each half-cycle. This peak being due, in the first mode of operation, to the activation pulse of the line signal BP24 of the line 124 of the display, it obviously does not appear anymore since a signal of no line activation is applied on the same line during the second mode of operation.

It is now necessary to examine the influence of the reduction in the rate of multiplexing when switching from normal operating mode to standby operation mode. The specialist will generally seek to optimize, in this case, maximizing the contrast of the display, that is to say, maximize the ratio between the intensity of a pixel in the active state and the intensity of a pixel in the non-active state. In order to maximize this contrast, the values of the non-activation voltages V1 to V4 are used, or more exactly the distribution of these non-activation voltages. The description which follows will make it possible to demonstrate the existence of an optimum, in terms of contrast, for determined values of the non-activation voltages.

For purposes of explanation, it will be useful to set the non-enable voltages V1 to V4 as follows. By defining V4 as equal to a fraction of the activation voltage VLCD, ie V4 = α VLCD, where α is a distribution parameter, it is possible to define, in accordance with what has already been mentioned above, that V1 = ( 1 - α) VLCD, V2 = (1 - 2α) VLCD, and V3 = 2α VLCD. It will be noted that the distribution parameter α is between 0 and 50%.

$${\mathrm{V}}_{\mathrm{OFF},\mathrm{rms}}=\sqrt{\frac{\left(\mathrm{n}-1\right){\mathrm{\alpha }}^{\mathrm{2}}+{\left(\mathrm{1}-\mathrm{2}\mathrm{\alpha }\right)}^{\mathrm{2}}}{\mathrm{n}}}\cdot {\mathrm{V}}_{\mathrm{LCD}}$$

où n est défini comme le nombre de lignes actives de l'affichage, 1:n étant dans ce cas le taux de multiplexage.In addition, the rms or rms values of the signal present at the terminals of each pixel in the active state and in the active state, namely the following values V _{ON, rms} and V _{OFF, rms, respectively, will be defined} : $${\mathrm{V}}_{\mathrm{WE},\mathrm{rms}}=\sqrt{\frac{\left(\mathrm{not}-\mathrm{1}\right){\mathrm{<figure-callout\; id="2"\; label="\alpha "\; filenames="imgf0008.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}^{\mathrm{2}}+\mathrm{1}}{\mathrm{not}}}\cdot {\mathrm{V}}_{\mathrm{LCD}}$$

$${\mathrm{V}}_{\mathrm{OFF},\mathrm{rms}}=\sqrt{\frac{\left(\mathrm{not}-1\right){\mathrm{<figure-callout\; id="2"\; label="\alpha "\; filenames="imgf0008.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}^{\mathrm{2}}+{\left(\mathrm{1}-\mathrm{2}\mathrm{<figure-callout\; id="2"\; label="\alpha "\; filenames="imgf0008.png"\; state="\{\{state\}\}">\alpha </figure-callout>}\right)}^{\mathrm{2}}}{\mathrm{not}}}\cdot {\mathrm{V}}_{\mathrm{LCD}}$$

where n is defined as the number of active lines of the display, 1: n being in this case the multiplexing rate.

It will therefore be understood that the values V _ON , _rms and V _OFF , _rms mentioned above are directly dependent on the number of active lines of the display, ie the multiplexing rate. It will be further noted that these values V _{ON, rms} and V _{OFF, rms} increase during a reduction of the multiplexing rate.

In order to maximize the contrast, the non-activation voltages V1 to V4, or, in other words, the distribution parameter α will preferably be chosen such that the ratio V _{ON, rms} / V _{OFF, rms} is maximum . This optimum is obtained, after mathematical development, for a value of the parameter α such that $$\mathrm{\alpha }=\frac{\sqrt{\mathrm{not}}-\mathrm{1}}{\mathrm{not}-\mathrm{1}}$$

It can be seen that the optimum is different for each multiplexing rate. With a multiplexing rate of 1:24 for example, that is to say twenty-four active lines, this parameter α is about 17%. In such a case, the non-activation levels are thus preferably chosen such that V1 = 83% VLCD, V2 = 66% VLCD, V3 = 34% VLCD and V4 = 17% VLCD, as is for example illustrated in FIGS. FIGS. 3A to 3C .

Similarly with a multiplexing ratio of 1: 8, that is to say eight active lines, this parameter α is about 25%. In such a case, the non-activation levels are preferably chosen such that V1 = 75% VLCD, V2 = V3 = 50% VLCD and V4 = 25% VLCD, so that only three levels of non-activation are then necessary.

The FIGS. 5A to 5C illustrate, in the second mode of operation where the multiplexing ratio is 1: 8, other examples of the line signals BP1 to BP24, column signals FP1 to FP5 and the resulting signals present at the terminals of the pixels 11, 12, 13 in the case where the parameter α is chosen at 25% in order to optimize the contrast of the display for this multiplexing rate, only three levels of non-activation being thus required in this case. In the FIGS. 5A to 5C these non-activation levels are designated VA, VB and VC to avoid confusion, where VA = 75% VLCD, VB = 50% VLCD and VC = 25% VLCD. These signals will not be described again because they are analogous, apart from the distribution of the levels of non-activation, to the signals illustrated in Figures 4A to 4C . It will be noted simply that the column signals, such as the FP2 and FP4 signals illustrated in FIG. Figure 4B , have only one level of non-activation VB in this case.

According to a first variant, it is thus possible to choose to optimize the contrast of the display for each mode of operation and to choose accordingly the distribution (parameter α mentioned above) of the non-activation voltages. According to this first variant, however, it will be noted that the contrast (V _ON ratio _{, rms} / V _{OFF, rms} ) increases when switching from the normal operating mode to the standby operating mode. This increase in contrast may be deemed unpleasant for the user.

According to a preferred variant of the invention, the distribution of the non-activation voltages from one operating mode to the other is adjusted so as to maintain the substantially constant contrast. By way of example, by adopting a distribution of the levels of non-activation V1 to V4 according to the illustration of the FIGS. 3A to 3C such as the distribution parameter α = 17% in order to optimize the contrast in the normal operating mode, it can be determined that the distribution of the levels of no activation V1 to V4, in the standby operating mode where the multiplexing rate is 1: 8, according to the embodiment of the invention used here by way of example, must be such that the distribution parameter α is substantially equal to 10%. In such a case, the non-activation voltages V1 to V4 are thus respectively defined at 90%, 80%, 20% and 10% of the VLCD activation voltage according to the illustration of FIGS. Figures 4A to 4C .

It will of course be understood that other distributions of the non-activation voltages can be envisaged to make it possible to maintain the contrast of the display constant from one mode of operation to another.

The user may also decide not to adjust the contrast and tolerate a slight variation of the latter.

In any case, the reduction of the multiplexing rate when switching from the normal operating mode to the standby operating mode is also accompanied by a reduction of the activation voltage VLCD (the activation voltage VSS is chosen as a reference to 0 volts in both modes). Indeed, as already mentioned above, the rms or rms values V _{ON, rms} and V _{OFF, rms} increase during a reduction of the multiplexing rate. It will thus be necessary to adjust the activation voltage VLCD in order, for example, that the effective value V _OFF , _rms of the signal present at the terminals of a pixel in the non-active state, is substantially constant from an operating mode to the other.

By way of example, the variant illustrated in FIGS. 3A to 3C and 4A to 4C that is to say the variant where the distribution of the non-activation voltages V1 to V4 is such that α = 17% in the normal operating mode and α = 10% in the standby operating mode in order to maintain the contrast of the constant display, we get V _OFF , _rms = 21.4% VLCD in the normal operating mode and V _OFF , _rms = 29.8% VLCD in the standby operating mode. It is therefore possible to reduce the activation voltage VLCD in the standby operation mode to 21.4 / 29.8 = 71.8% of the voltage VLCD used in the normal operating mode. This reduction of the activation voltage VLCD ensures an additional reduction in the consumption of the display.

In general, it can be seen that the advantages of the present invention are multiple. In the first place, the reduction of the multiplexing rate and therefore of the signal multiplexing frequency makes it possible to reduce the number of switches on the row and column electrodes of the display. For example, according to the embodiment of the invention used here by way of example, when switching from the 1:24 multiplexing rate to the 1: 8 multiplexing rate, the multiplexing frequency is reduced by three. On the other hand, the reduction of the multiplexing rate allows to reduce the activation voltage VLCD pixels as already mentioned above. Finally, the reduction of the multiplexing rate generates an increase in the contrast of the display which may or may not be adjusted by the user.

The Applicant has found that for a multiplexed display device having twenty-four lines active in normal operating mode and eight lines active in standby mode of operation, a reduction in energy consumption of the order of two-thirds, as a minimum, was reached (the VLCD activation voltage being reduced when switching to the standby mode of operation).

The control method which has just been described can thus be applied so as to switch a multiplexed display between a first so-called normal operating mode (all the active lines) and at least one second so-called standby operating mode (one or more inactive lines). This switching between the modes can be carried out in a software way by means of a suitable programming of the control device or in a material way by the use of dedicated circuits. This switching can be automatic if desired.

We will now describe by means of figure 6 , according to another aspect of the invention, an embodiment of a control device of a multiplexed display for implementing the method described above.

The figure 6 thus schematically shows a device or control circuit of a multiplexed display, generally designated by the reference numeral 30. This device 30 comprises a mode switch 31, a programmable sequencer 32, a line signal generator 33, a means 34, a column signal generator 35, an activation and non-activation voltage generator 36 and a frequency generator 37.

The mode switch 31 provides, as its name implies, a switching, automatic or manual, between the normal operating mode and the standby operating mode. It controls the operation of the programmable sequencer 32, the activation and non-activation voltage generator 36 as well as the frequency generator 37.

The activation and non-activation voltage generator 36 is arranged to produce at its output the activation and non-activation voltages to be applied to the rows and columns of the display. In particular, this generator 36 produces at its output VON, BP activation and VOFF, BP activation voltages for the lines of the display. These voltages VON, BP and VOFF, BP are applied to the line signal generator 33. The generator also produces at its output VON activation voltages, FP and non-activation VOFF, FP for the columns of the display. These voltages VON, FP and VOFF, FP are applied to the column signal generator 35.

The voltages produced at the output of the activation and non-activation voltage generator 36 are alternated from one half-cycle to the other as seen above. The generator 36 is, as such, controlled by the programmable sequencer 32 so as to ensure this alternation of the activation and non-activation voltages.

The generator 36 is controlled by the mode switch 31 so that the levels of the activation and non-activation voltages are changed when switching from the normal operating mode to the standby operating mode. In particular, this generator 36 is arranged, on the one hand, to reduce the value of the activation voltage VLCD (VSS being chosen as a reference to 0 Volts) in response to the transition from the normal operating mode to the standby operating mode , and to modify, on the other hand, the distribution of the non-activation voltages V1 to V4 according to what has been described above.

More specifically, it is possible to decompose the activation and non-activation voltage generator 36 into a first block 361 controlled by the mode switch and making it possible to generate the VSS, VLCD and non-activation voltages V1 to V4, and a second block 362 controlled by the programmable sequencer 32 so as to alternate the activation and non-activation voltages from one half cycle to another.

The frequency generator 37 comprises an oscillator 371, a frequency divider circuit 372 and a frequency switch 373. The oscillator 371 and the frequency divider circuit 372 are arranged to produce a signal whose frequency determines the appearance of the row and column. In the particular case, the oscillator 371 and the frequency divider circuit 372 are arranged to deliver a first signal at a frequency f, referred to as multiplexing, intended for the first mode of operation and a second signal at a frequency f / 3 intended for the second mode of operation. The frequency switch 373, controlled by the mode switch 31, outputs at its output a frequency multiplexing signal f during the first mode and a frequency division multiplex signal f / 3 during the second mode. This multiplexing signal is applied to the mode sequencer 32 and the formatting means 34.

The programmable sequencer 32 provides the appropriate sequence for generating the signals intended to be applied to the row electrodes of the display, such as the signals BP1 to BP24 presented previously. This programmable sequencer 32 is thus connected to the line signal generator 33. In the example illustrated, the programmable sequencer 32 comprises twenty-four outputs, connected to the line signal generator 33, each of these outputs controlling the switching, in the line signal generator 33, between the activation voltages VON, BP and no activation VOFF, BP according to the sequence described above. The line signal generator 33 comprises twenty-four outputs, in this example, on which the line signals BP1 to BP24 are respectively produced.

In the normal operating mode, the sequencer 32 generates the appropriate sequence for sequentially activating all lines of the display, i.e. the twenty-four lines of the display in this example. The generator 33 produces in response twenty-four line signals BP1 to BP24 such as the signals illustrated in FIG. figure 3A .

In the figure 6 the state of the outputs of the sequencer 32 in the normal operating mode has been schematized over a period of half a cycle. The state of the outputs of the sequencer 32 during a half cycle can for example be schematized, in the normal operating mode by a diagonal matrix, here a 24x24 matrix in which "1" and "0" correspond to the switching of the signal of line corresponding respectively to the activation voltage and the non-activation voltage.

In the standby mode of operation, the sequencer 32 produces the appropriate sequence for activating the first eight lines of the display in this example. The last sixteen lines of the display are all held in an inactive state. To do this, the first eight outputs of the sequencer (from the left in the figure 6 ) sequentially controls the switching of the first eight corresponding outputs of the generator 33 between the activation and non-activation voltages in order to produce the appropriate signals BP1 to BP8 as illustrated in FIGS. Figures 4A or 5A . The last sixteen outputs of the sequencer 32 maintain the sixteen corresponding outputs of the generator 33 at the non-energizing voltage. The line signals BP9 to BP24 thus produced are in accordance with the illustrations of the Figures 4A or 5A .

In the standby mode of operation, it is thus possible to schematize the state of the first eight outputs (from the left) of the sequencer 32 by an 8x8 diagonal matrix, in this example, the other sixteen outputs being always maintained at "0".

The formatting means 34 ensures, according to the data to be displayed, the formatting of the column signals, in the example illustrated, the column signals FP1 to FP5. This shaping means 34 adequately controls the column signal generator 35.

Analogously to the line signal generator 33, the column signal generator 35 ensures the appropriate switching, for each column of the display of the column signals, here FP1 to FP5, between the activation voltages. VON, FP and no VOFF activation, FP produced by the voltage generator 36.

It will be understood that various modifications can be made to the control device illustrated in FIG. figure 6 without departing from the scope of the invention. In particular, it will be understood that it is perfectly possible to program the sequencer 32 so that eight other lines of the display are kept active in the second mode of operation, such as for example the first and the last seven lines of the display. On the other hand, both the total number of lines of the display as well as the number of lines remaining active during the second mode of operation can be changed. It will be recalled, however, that these changes in particular influence the multiplexing frequency of the device as well as the activation and non-activation voltages required.

It will be understood further that the multiplexing rate in normal operating mode is essentially fixed by the number of lines of the display. The rate of multiplexing in standby mode of operation can be perfectly programmable so as to be modified according to the wishes of the user or the designer of the display.

Alternatively, it will be understood that the present invention can be adapted so that the display can occupy more than one standby mode of operation, for example a first standby mode of operation in which the multiplexing rate is reduced by two, a second standby mode of operation in which the multiplexing rate is reduced by three, etc. Everything can be programmed perfectly. The present invention is therefore in no way limited to a display that can occupy only a normal operating mode and a single standby operating mode, but applies analogously if it is desired to provide more than one operating mode. Eve.

It will also be understood that the method and the control device are not limited to the particular modes of implementation described in the present description. In particular, the method or the device obviously applies in a manner similar to a display comprising a number of active lines different from twenty-four in normal operating mode and a number of active lines different from eight in standby operation mode. . It will be recalled again that the figures illustrate only some particular and non-limiting embodiments of the present invention.

Claims (10)

1. Control method for a multiplexed display (10) comprising a plurality of pixels (11, 12, 13) arranged in lines (101 to 124) and in columns (201 to 205) and coupled to line electrodes and column electrodes, each of said pixels (11, 12, 13) being selectively activated or deactivated by a determined combination of a line signal (BP1 to BP24) and of a column signal (FP1 to FP5) respectively applied to the corresponding line and column electrodes, so-called active lines of the display being sequentially activated once during a period of a half-cycle (A, B), a cycle being formed by a first half-cycle corresponding to a first frame applied to a line electrode or to a column electrode, and by a second half-cycle corresponding to a frame reversed with respect to the first frame, the first frame and the reversed frame succeeding alternately such that the mean resulting voltage at a pixel is zero, display control method according to which said display is operated in a first so-called normal operating mode, in which all the lines of the display are activated, said line and column signals having a first so-called normal multiplex rate in said first operating mode, and said display is switched into at least a second so-called standby operating mode, where so-called non-active lines of the display are deactivated by applying, to the corresponding line electrodes, so-called non-activation signals, said display being such that, in the at least second operating mode, one acts on the line signals (BP1 to BP8) applied to the active lines and on said column signals (FP1 to FP5) such that they have a second multiplex rate whose value is reduced, with respect to said first multiplex rate, in proportion to the number of non-active lines, characterized in that:

   - an elementary duration (T) is determined during which the column signal (BP1 to BP24; BP1 to BP8) is brought to the activation voltage, this duration being determined by the duration of each half-cycle (A, B), and being divided by the number of lines of the display;

   - the column signal (FP1 to FP5) is brought to the activation voltage during the said same elementary duration (T) defined with respect to the line signals (BP1 to BP24; BP1 to BP8);

   - in the at least second so-called standby operating mode, each non-activation line signal is determined such that when said appropriate line signal is combined with the corresponding column signal (FP1 to FP5), each pixel of said non-active lines receives at its terminals a signal whose amplitude is too low to activate said pixel.
2. Method according to claim 1, characterised in that:

   - said line signals (BP1 to BP24; BP1 to BP8) vary, during a first half-cycle (A), between the ground voltage (VSS) and a first non-activation voltage (V1; VA), and, during a following half-cycle (B), between an activation voltage (VLCD) and a second non-activation voltage (V4, VC),

   - said column signals (FP1 to FP5) vary, during the first half-cycle (A), between said activation voltage (VLCD) and a third non-activation voltage (V2; VB), and, during the following half-cycle (B), between said ground voltage (VSS) and a fourth non-activation voltage (V3, VB),

   - said non-activation line signals are brought, during the entire duration of said first half-cycle (A), to said first non-activation voltage (V1; VA), and, during the entire duration of said following half-cycle (B), to said second non-activation voltage (V4, VC), said activation (VLCD) and non-activation (V1 to V4; VA to VC) voltages being chosen such that, over a period of two successive half-cycles, the mean value of the signal present at the terminals of each pixel is substantially zero.
3. Method according to claim 2, characterized in that, during the passage from the first to said at least second operating mode, the value of said activation voltage (VLCD) is reduced so as to compensate for the increase in the effective value (V_OFF,_rms) of the signal present at the terminals of a non-active pixel.
4. Method according to claim 2 or 3, characterized in that said non-activation voltages (V1 to V4) are defined such as V4=αVLCD, V1=(1- α)VLCD, V2=(1- 2α)VLCD, and V3=2 αVLCD, where α is a distribution parameter comprised between 0 and 50%.
5. Method according to claim 4, characterized in that the distribution parameter α is given by the formula $$\mathrm{\alpha }=\frac{\sqrt{\mathrm{n}}-\mathrm{1}}{\mathrm{n}-\mathrm{1}}$$

   

   where n is defined as the number of active lines of the display.
6. Control device for a multiplexed display (10) comprising a plurality of pixels (11, 12, 13) arranged in lines (101 to 124) and in columns (201 to 205) and coupled to line electrodes and column electrodes, each of said pixels (11, 12, 13) being selectively activated or deactivated by a determined combination of a line signal (BP1 to BP24) and of a column signal (FP1 to FP5) respectively applied to the corresponding line and column electrodes, so-called active lines of the display being sequentially activated once during a period of a half-cycle (A, B), said device being able to operate in a first so-called normal operating mode wherein all the lines of the display are activated, said line and column signals having a first so-called normal multiplex rate in said first operating mode, said control device including:

   - means (32, 33) for generating said line signals (BP1 to BP24) controlled by said multiplexing signal, and

   - voltage generating means (36) for generating activation (VON,BP, VON,FP) and non-activation (VOFF,BP, VOFF,FP) voltages intended for said line and column signal generating means (32, 33, 34, 35);

   - means (34, 35) for generating said column signals (FP1 to FP5) controlled by said multiplexing signal; and

   - frequency generator means (37) for generating a multiplexing signal having a frequency (f), in said first operating mode, determining said first multiplex rate, said frequency generating means (37) are arranged to reduce the frequency of the multiplexing signal in proportion to the number of non-active lines, in response to the passage into said at least second operating mode, such that the line signals (BP1 to BP8) applied to the active line electrodes and said column signals (FP1 to FP5) have a second multiplex rate whose value is reduced, with respect to said first multiplexing mode, in proportion to the number of non-active lines,

   - mode switching means (31) arranged for switching the device between said first operating mode and at least a second so-called standby operating mode, where so-called non-active lines of the display are deactivated,

   characterized in that:

   - the mode switching means (31) are capable of controlling said line signal generating means (32, 33), and said frequency generating means (37),

   - said frequency generator means (37) are arranged to generate an elementary duration (T) during which the line signal and the column signal are brought to the activation voltage, said elementary duration (T) being determined by the duration of each half-cycle (A, B) and being a function of the number of lines of the display;

   - said means (32, 34) for generating line signals are arranged to produce, in the at least second operating mode, so-called non-activation line signals on the electrodes of the non-active lines, these non-activation line signals being determined such that, when the appropriate line signals are combined with the column signals (FP1 to FP5), each pixel of said non-active lines receives at the terminals thereof a signal whose amplitude is too low to activate said pixel.
7. Device according to claim 6, characterised in that said voltage generating means (36) are arranged to generate a ground voltage (VSS), an activation voltage (VLCD) and first, second, third and fourth non-activation voltages (V1 to V4, VA to VC),

   - said line signals (BP1 to BP24; BP1 to BP8) are capable of varying, during a first half-cycle (A), between said ground voltage (VSS) and said first non-activation voltage (V1; VA) and, during a following half-cycle (B), between said activation voltage (VLCD) and said second non-activation voltage (V4, VC),

   - said column signals (FP1 to FP5) are capable of varying, during the first half-cycle (A), between said activation voltage (VLCD) and said third non-activation voltage (V2; VB), and, during the following half-cycle (B), between said ground voltage (VSS) and said fourth non-activation voltage (V3, VB),

   - said non-activation line signals are brought, during the entire duration of said first half-cycle (A), to said first non-activation voltage (V1; VA), and, during the entire duration of said following half-cycle (B), to said second non-activation voltage (V4, VC),

   said activation (VLCD) and non-activation (V1 to V4; VA to VC) voltages being chosen such that, over a period of two successive half-cycles, the mean value of the signal present at the terminals of each pixel is substantially zero.
8. Device according to claim 7, characterised in that said mode switching means (31) are additionally capable of controlling said frequency generator means such that the value of said activation voltage (VLCD) is reduced, during transition from the first to said at least second operating mode, to compensate the increase of the effective value (V_OFF,_rms) of the signal present at the terminals of a non-active pixel.
9. Device according to claim 7 or 8, characterised in that said non-activation voltages (V1 to V4; VA to VC) are defined such as V4=αVLCD, V1=(1-α)VLCD, V2=(1- 2α)VLCD, and V3=2 αVLCD, where α is a distribution parameter comprised between 0 and 50%.
10. Device according to claim 9, characterized in that the distribution parameter α is a function of the number of active lines of the display.

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