EP1092188A4 - Split directory-based cache coherency technique for a multi-processor computer system - Google Patents

Split directory-based cache coherency technique for a multi-processor computer system

Info

Publication number
EP1092188A4
EP1092188A4 EP99917460A EP99917460A EP1092188A4 EP 1092188 A4 EP1092188 A4 EP 1092188A4 EP 99917460 A EP99917460 A EP 99917460A EP 99917460 A EP99917460 A EP 99917460A EP 1092188 A4 EP1092188 A4 EP 1092188A4
Authority
EP
European Patent Office
Prior art keywords
computer system
cache coherency
processor computer
based cache
coherency technique
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99917460A
Other languages
German (de)
French (fr)
Other versions
EP1092188A1 (en
Inventor
Jonathan L Bertoni
Lee A Burton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRC Computers LLC
Original Assignee
SRC Computers LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SRC Computers LLC filed Critical SRC Computers LLC
Publication of EP1092188A1 publication Critical patent/EP1092188A1/en
Publication of EP1092188A4 publication Critical patent/EP1092188A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
EP99917460A 1998-06-30 1999-04-13 Split directory-based cache coherency technique for a multi-processor computer system Withdrawn EP1092188A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/108,088 US6295598B1 (en) 1998-06-30 1998-06-30 Split directory-based cache coherency technique for a multi-processor computer system
PCT/US1999/008065 WO2000000891A1 (en) 1998-06-30 1999-04-13 Split directory-based cache coherency technique for a multi-processor computer system
US108088 2002-03-27

Publications (2)

Publication Number Publication Date
EP1092188A1 EP1092188A1 (en) 2001-04-18
EP1092188A4 true EP1092188A4 (en) 2003-04-16

Family

ID=22320225

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99917460A Withdrawn EP1092188A4 (en) 1998-06-30 1999-04-13 Split directory-based cache coherency technique for a multi-processor computer system

Country Status (5)

Country Link
US (1) US6295598B1 (en)
EP (1) EP1092188A4 (en)
JP (1) JP2002519785A (en)
CA (1) CA2335307A1 (en)
WO (1) WO2000000891A1 (en)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6526110B1 (en) * 1999-09-14 2003-02-25 Mitsubishi Electric Research Laboratories Inc. Embedded RAM based digital signal processor
US6587964B1 (en) * 2000-02-18 2003-07-01 Hewlett-Packard Development Company, L.P. Transparent software emulation as an alternative to hardware bus lock
US6725334B2 (en) * 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US6668308B2 (en) * 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
JP3787491B2 (en) * 2000-11-20 2006-06-21 株式会社日立グローバルストレージテクノロジーズ Magnetic disk unit
US6925634B2 (en) * 2001-01-24 2005-08-02 Texas Instruments Incorporated Method for maintaining cache coherency in software in a shared memory system
FR2820850B1 (en) * 2001-02-15 2003-05-09 Bull Sa CONSISTENCY CONTROLLER FOR MULTIPROCESSOR ASSEMBLY, MODULE AND MULTIPROCESSOR ASSEMBLY WITH MULTIMODULE ARCHITECTURE INCLUDING SUCH A CONTROLLER
US6965972B2 (en) * 2002-09-25 2005-11-15 International Business Machines Corporation Real time emulation of coherence directories using global sparse directories
US6868485B1 (en) * 2002-09-27 2005-03-15 Advanced Micro Devices, Inc. Computer system with integrated directory and processor cache
US7096323B1 (en) 2002-09-27 2006-08-22 Advanced Micro Devices, Inc. Computer system with processor cache that stores remote cache presence information
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US8516179B2 (en) * 2003-12-03 2013-08-20 Digital Rna, Llc Integrated circuit with coupled processing cores
US7711901B2 (en) * 2004-02-13 2010-05-04 Intel Corporation Method, system, and apparatus for an hierarchical cache line replacement
US7299339B2 (en) 2004-08-30 2007-11-20 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
US8135910B2 (en) * 2005-02-11 2012-03-13 International Business Machines Corporation Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory
US7522168B2 (en) * 2005-09-27 2009-04-21 Sony Computer Entertainment Inc. Cell processor task and data management
US8037474B2 (en) * 2005-09-27 2011-10-11 Sony Computer Entertainment Inc. Task manager with stored task definition having pointer to a memory address containing required code data related to the task for execution
US7734827B2 (en) * 2005-09-27 2010-06-08 Sony Computer Entertainment, Inc. Operation of cell processors
US8141076B2 (en) * 2005-09-27 2012-03-20 Sony Computer Entertainment Inc. Cell processor methods and apparatus
US8316220B2 (en) * 2005-09-27 2012-11-20 Sony Computer Entertainment Inc. Operating processors over a network
US7506123B1 (en) * 2005-09-27 2009-03-17 Sony Computer Entertainment Inc. Method and system for performing memory copy function on a cell processor
US7975269B2 (en) * 2005-09-27 2011-07-05 Sony Computer Entertainment Inc. Parallel processor methods and apparatus
US20070094336A1 (en) * 2005-10-24 2007-04-26 Microsoft Corporation Asynchronous server synchronously storing persistent data batches
US8595747B2 (en) * 2005-12-29 2013-11-26 Sony Computer Entertainment Inc. Efficient task scheduling by assigning fixed registers to scheduler
US7475193B2 (en) * 2006-01-18 2009-01-06 International Business Machines Corporation Separate data and coherency cache directories in a shared cache in a multiprocessor system
US20070168620A1 (en) * 2006-01-19 2007-07-19 Sicortex, Inc. System and method of multi-core cache coherency
US7991963B2 (en) * 2007-12-31 2011-08-02 Intel Corporation In-memory, in-page directory cache coherency scheme
EP2416253B1 (en) * 2009-03-31 2014-07-23 Fujitsu Limited Data transmission circuit and data transmission method
US8325601B2 (en) * 2009-05-08 2012-12-04 Canon Kabushiki Kaisha Reliable network streaming of a single data stream over multiple physical interfaces
US8880716B2 (en) * 2009-05-08 2014-11-04 Canon Kabushiki Kaisha Network streaming of a single data stream simultaneously over multiple physical interfaces
US8396960B2 (en) * 2009-05-08 2013-03-12 Canon Kabushiki Kaisha Efficient network utilization using multiple physical interfaces
US8068514B2 (en) * 2009-05-22 2011-11-29 Canon Kabushiki Kaisha Efficient bandwidth utilization when streaming data over multiple network interfaces
US8356109B2 (en) 2010-05-13 2013-01-15 Canon Kabushiki Kaisha Network streaming of a video stream over multiple communication channels
JP5121896B2 (en) 2010-08-11 2013-01-16 株式会社東芝 Multi-core processor system and multi-core processor
US20130111149A1 (en) * 2011-10-26 2013-05-02 Arteris SAS Integrated circuits with cache-coherency
US20130157639A1 (en) 2011-12-16 2013-06-20 SRC Computers, LLC Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption
JP5929420B2 (en) * 2012-03-29 2016-06-08 富士通株式会社 Arithmetic processing apparatus, control method for arithmetic processing apparatus, and information processing apparatus
US10741226B2 (en) 2013-05-28 2020-08-11 Fg Src Llc Multi-processor computer architecture incorporating distributed multi-ported common memory modules
US9530483B2 (en) 2014-05-27 2016-12-27 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
US9153311B1 (en) 2014-05-27 2015-10-06 SRC Computers, LLC System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers
US9866498B2 (en) * 2014-12-23 2018-01-09 Intel Corporation Technologies for network packet cache management
US10445271B2 (en) * 2016-01-04 2019-10-15 Intel Corporation Multi-core communication acceleration using hardware queue device
WO2018001495A1 (en) 2016-06-30 2018-01-04 Huawei Technologies Co., Ltd. Systems and methods for managing databases
US11119926B2 (en) 2017-12-18 2021-09-14 Advanced Micro Devices, Inc. Region based directory scheme to adapt to large cache sizes
US10705959B2 (en) 2018-08-31 2020-07-07 Advanced Micro Devices, Inc. Region based split-directory scheme to adapt to large cache sizes
US10922237B2 (en) 2018-09-12 2021-02-16 Advanced Micro Devices, Inc. Accelerating accesses to private regions in a region-based cache directory scheme

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0427250A2 (en) * 1989-11-10 1991-05-15 International Business Machines Corporation Method and apparatus for exploiting communications bandwidth as for providing shared memory
US5537569A (en) * 1993-03-02 1996-07-16 Kabushiki Kaisha Toshiba Multiprocessor system utilizing a directory memory and including grouped processing elements each having cache
EP0764905A1 (en) * 1995-09-25 1997-03-26 International Business Machines Corporation An invalidation bus optimisation for multiprocessors using directory-based coherence protocols
US5634110A (en) * 1995-05-05 1997-05-27 Silicon Graphics, Inc. Cache coherency using flexible directory bit vectors
WO1999026144A1 (en) * 1997-11-17 1999-05-27 Cray Research, Inc. Multi-dimensional cache coherence directory structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5058006A (en) * 1988-06-27 1991-10-15 Digital Equipment Corporation Method and apparatus for filtering invalidate requests
US5197146A (en) * 1989-06-21 1993-03-23 Hewlett-Packard Company Method for maintaining cache coherence in a multiprocessor computer system
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
JPH0619785A (en) 1992-03-27 1994-01-28 Matsushita Electric Ind Co Ltd Distributed shared virtual memory and its constitution method
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
US5680576A (en) * 1995-05-05 1997-10-21 Silicon Graphics, Inc. Directory-based coherence protocol allowing efficient dropping of clean-exclusive data
US5787476A (en) * 1995-05-05 1998-07-28 Silicon Graphics, Inc. System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
US5829035A (en) * 1995-12-22 1998-10-27 Apple Computer, Inc. System and method for preventing stale data in multiple processor computer systems
US5900015A (en) * 1996-08-09 1999-05-04 International Business Machines Corporation System and method for maintaining cache coherency using path directories
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0427250A2 (en) * 1989-11-10 1991-05-15 International Business Machines Corporation Method and apparatus for exploiting communications bandwidth as for providing shared memory
US5537569A (en) * 1993-03-02 1996-07-16 Kabushiki Kaisha Toshiba Multiprocessor system utilizing a directory memory and including grouped processing elements each having cache
US5634110A (en) * 1995-05-05 1997-05-27 Silicon Graphics, Inc. Cache coherency using flexible directory bit vectors
EP0764905A1 (en) * 1995-09-25 1997-03-26 International Business Machines Corporation An invalidation bus optimisation for multiprocessors using directory-based coherence protocols
WO1999026144A1 (en) * 1997-11-17 1999-05-27 Cray Research, Inc. Multi-dimensional cache coherence directory structure

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"RESIDENCE GROUP RECORDING FOR MULTIPROCESSOR CACHES", IBM TECHNICAL DISCLOSURE BULLETIN,IBM CORP. NEW YORK,US, vol. 36, no. 7, 1 July 1993 (1993-07-01), pages 529 - 530, XP000383724, ISSN: 0018-8689 *
HANAWA T ET AL: "MINC: MULTISTAGE INTERCONNECTION NETWORK WITH CACHE CONTROL MECHANISM", IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO,JP, vol. E80-D, no. 9, 1 September 1997 (1997-09-01), pages 863 - 870, XP000723737, ISSN: 0916-8532 *
See also references of WO0000891A1 *
STEVE Y. LAU, WILLIAM S. WU: "Sebring Ring technology breaks through I/O bottleneck while adding fault tolerance and hot swap capability to standard PCI bus", REAL TIME MAGAZINE, vol. 98, no. 4, 31 December 1998 (1998-12-31), Belgium, pages 69 - 75, XP002170152 *

Also Published As

Publication number Publication date
CA2335307A1 (en) 2000-01-06
JP2002519785A (en) 2002-07-02
WO2000000891A1 (en) 2000-01-06
EP1092188A1 (en) 2001-04-18
US6295598B1 (en) 2001-09-25

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