EP1090422A1 - Method for producing thin substrate layers - Google Patents

Method for producing thin substrate layers

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Publication number
EP1090422A1
EP1090422A1 EP99939373A EP99939373A EP1090422A1 EP 1090422 A1 EP1090422 A1 EP 1090422A1 EP 99939373 A EP99939373 A EP 99939373A EP 99939373 A EP99939373 A EP 99939373A EP 1090422 A1 EP1090422 A1 EP 1090422A1
Authority
EP
European Patent Office
Prior art keywords
characterized
substrate
channel
layer
method according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99939373A
Other languages
German (de)
French (fr)
Inventor
Karl Haberger
Andreas Plettner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19827717 priority Critical
Priority to DE19827717 priority
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority to PCT/DE1999/001826 priority patent/WO1999067820A1/en
Publication of EP1090422A1 publication Critical patent/EP1090422A1/en
Application status is Withdrawn legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063Electrolytic etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/967Semiconductor on specified insulator

Abstract

The invention relates to a method for producing very thin substrate layers, especially thin semiconductor regions, which can contain integrated circuits. According to the invention, two substrates (1, 2) are joined with the front sides thereof by means of one or more intermediate joining layers (3, 4). At least one of the joining layers or the front side of one of the substrates is structured beforehand such that channel-shaped recesses (5) are formed which permit an etching agent to penetrate in a lateral manner. The resulting wafer stack is thinned from one side until the desired layer thickness is obtained. Finally, this thin layer is removed from the remaining substrate by introducing the etching agent into the channel-shaped recesses. This removal process is an economical, wet chemical process which does not jeopardize the chip and the added-value integrated thereon.

Description

A process for the production of thin layers of substrate

The invention relates to a process for the production of thin layers of substrate, in particular semiconductor thin areas that may contain integrated circuits.

For many present and future applications of electronic components and in particular of integrated circuits (IC), it may be advantageous to limit the total thickness of these ICs or the semiconductor regions with the ICs to a few micrometers. Such thin circuits have a very low mass and a very low profile. They are mechanically flexible, adapt to the thermomechanical behavior of a pad and reduce due to their low volume disposal problems. All these benefits can in any future disposable electronics even more important. Already today are thin electronic devices and circuits for Anwendungsfeider as flat panel

Displays in which ICs are bonded to glass, the mechatronics, be bonded in the ICs on metal, and the power electronics (transistors, thyristors, diodes with a vertical line) of great interest.

In silicon technology are integrated circuits on substrates, the so-called wafers manufactured. These wafers are made of monocrystalline silicon of typically 700 microns thickness and diameters of currently 200 mm, 300 mm soon. The determination of the thickness of the substrates to 700 microns has various procedural and physical aspects. To play the one hand the precision and yield when sawing the pulled from the melt, crystal rods into wafers and their subsequent polishing a roll, on the other hand, the mechanical stability and sufficient thermal mass must be ensured during the actual processing of the IC. After the semiconductor manufacturing technology for the production of the circuits or devices, the wafer and thus, the individual chips of the wafer to rest thicknesses of 200 microns to be thinned down to 120 microns at the moment to in the housing or in particular chip cards can be installed.

A processing of the components or circuits on cantilevered already thin wafer coming off a rule, since the mechanical stability, thermal capacity, etc. therefor below a thickness of 50 microns by no means sufficient. In addition, the process development and overall Fertigungsund Equipment equipment are furnished to conventional thick wafers.

The thinning of the fully processed wafer is usually done by grinding. The backside of the wafer is removed mechanically by means of an abrasive paste and abrasive suitable carriers to the desired residual thickness. Silicon as monocrystalline substance can not be machined. Instead, so-called micro cracks occur during grinding due to the crystalline nature, which continue at unsuitable process control devices to the region of the wafer and destroy the functionality of the circuits. Due to these circumstances, the attainable by grinding residual thickness of the silicon substrates is restricted, in generally have a thickness times the 5- to 10 corresponds to the abrasive grain size.

One way to solve this problem is to use very fine abrasive grains down to diameters of a few hundred nanometers. However, this entails a drastic decrease in the removal rate with them, so that the thinning process takes a very long time.

For falling below the residual thickness encountered during conventional grinding process is usually very gentle polishing process must be used. A corresponding process, called the advantages of grind, wet chemical etching, and. CMP (Chemical Mechanical Polishing) attempts to combine, for example, in D. Bollman et al. , Abstract no. 2115, Proceedings, The Electrochemical Society Meeting, Paris 1997, published. Alternatively, wet and dry etching processes also have been tested. However, the latter cause a high thermal stress on the substrate and the components thereon in the required level of the removal rate.

the thinning of the wafer is effected in principle in this method after processing of the circuits. So the leaders of thinning processes carried out on a wafer, which already has the entire, high value chip production accumulated on its surface. Accordingly, erroneous thinning leads to the reduction in the yield and thus losses to high value. Furthermore, the maintenance of the desired residual thickness is difficult because of the thickness measurement disturbed by the implemented components possibility of (local) residual.

A fundamental solution to the problem of thinning of wafers with a high cumulative value and the complicated thickness measurement is the use of so-called SOI wafers. SOI wafer bearing a dense buried under the surface insulating layer, usually in the form of a Si0 layer. There are several methods for manufacturing such SOI wafer (see, eg WP Maszara et al. "SOI material for mainstream CMOS Technology", in SOI Technology and Devices VIII, ed .: S. Christoloveanu, The Electrochemical Society Proceedings 97-23 , 1997), which are outlined below.

In the SOS technique (Silicon On Sapphire) is epitaxially deposited on a polished Al 2 0 3 crystal, a silicon layer. This is possible due to the almost same lattice constant of both materials. However, crystalline Al must be used 2 0 3 wafer, which makes this process very expensive and can be generally used only in extreme high-price applications. In the ZMR technique (Zone Melting Recrystal- neutralization) is polysilicon deposited and then crystallized by a local melting and solidification process on a wafer covered with Si0 2. The crystal quality, crystallite size, etc. of these wafers, however, no longer meets the demands of today's CMOS technology.

In the SIMOX technique (Separation by Implanted Oxygen) generates a high-dose ion implantation near the surface of the silicon wafer, a stoichiometric Si0 layer which, with suitable process control, that annealing the crystal damage caused by the implantation, the overlying, extremely thin and later can monocrystalline silicon layer bearing components.

When the BESOI technique (Bonded Etched-back Silicon On Insulator), two oxidized silicon wafers firmly connected by thermal bonding and co-valent bonds therewith. Then one of the two wafers is rückgedünnt the useful thickness. A special variant of BESOI technology ( "SmartCut®" or IonCut) used special method of thinning, the one generated by Ionenimplan- tation buried on the implementation of the surface

based layer, along which the on the second wafer (handle wafer) bonded wear layer is split off. This can be through the formation of gas bubbles by means of hydrogen or helium implantation (see EP-A 0,533,551 or M. Bruel et al. "Unibond SOI wafer Achieved by Smart-Cut® process" in SOI Technology and Devices VIII, ed .: S . Christoloveanu, The Electrochemical Society Proceedings 97-23, 1997) or (by detachment of a refractory intermediate layer carried see DE 195 46 179 AI). In both cases, the preparation of a BESOI wafer without return loops or back etching of large parts of a monocrystalline wafer previously generated with difficulty succeeds.

SOI wafer after the SIMOX and BESOI methods have been developed in recent years to market. They are increasingly used in the application fields of high-temperature electronics and "low power electronics" and are commercially available in large quantities.

Such SOI wafers can be used for the production of extremely thin IC. Subsequent removal of the thick carrier wafer by grinding wet- or dry-chemical etching, etc. can be advantageous stopped at the buried layer. In the case of the mechanical grinding, and especially its more sophisticated form of the chemical mechanical

Polishing (CMP) can be used as a 2 layer mechanically hard stop layer, the buried Si0. In addition, mechanical defects such as micro cracks can not or hardly cross the amorphous layer Si0-. In the case of wet chemical etching back the high selectivity leads (better than 1: 100) of the generally oxidising silicon etching a reliable etch stop at the buried oxide layer. In the case of less selective dry etching, for example by means of NF 3 plasma, the Si0 may also serve as a selective stop layer 2 layer. In addition, a local self-limitation of the etching process can be used due to the decreasing lateral conductivity.

An advantage of the use of SOI wafers that the leading to the subsequent thinning process, namely the implementation of a buried layer below the silicon of the usable wafer, takes place before the actual semiconductor technical processing. Thus, no high added value at risk on the one hand, and on the other very simple, optical or acoustic Schichtdickenmeßverfahren can be used, since the wafer is still wearing at this stage no local structures, metals, etc., make it difficult to contact and precise thickness measurements or exclude.

However, the removal of the thick handle wafer by grinding or etching means a destruction of the monocrystalline silicon in considerable thickness with a consequent expenditure of time.

The object of the present invention is to provide an inexpensive and quick method for the production of thin layers of substrate which is suitable for the production of extremely thin IC and which avoids the above problems.

The object is achieved with the method of claim. 1 Advantageous embodiments of the method are subject of the subclaims. Furthermore, 29 to 47 substrate arrays are shown in the claims, which are an essential key product in carrying out the process.

According to the invention, hereinafter referred to as RevSOI (reversible SOI) designated method, a first and a second substrate with their front sides connected via one or more intermediate tie layers. At least one of the tie layers or the front one of the substrates is formed such that it has channel-shaped depressions, the lateral

enable penetration of an etchant. Subsequently, the first substrate from the back until a thin substrate layer thinned. This thin substrate layer is finally separated from the second substrate by introducing the etchant in the channel-shaped recesses.

Preferentially the two substrates semi- conductor wafer is for the production of ICs.

The processing of these wafers is like within the IC or discrete components manufacturing usual. Deflections of the wafer do not occur as long as the width of the channels (preferably 0.1 to 2 .mu.m) in a fraction of the Wear layer thickness of the semi-conductor layer (typically 0.5 to 20 microns) is located.

After processing the structured connection layer serves as a sacrificial layer. This layer is either anytime laterally accessible from the side of the wafer or, in the case of a preferred exemplary form as soon as the hermetically sealed wafer edge is removed / opened. This is done especially automatically when the wafer into chips is separated. Previously, the thin chips are fixed on a carrier substrate advantageously.

The separation of useful and bulk layer is preferably carried out by wet chemical etching. In this case, the etchant (for example HF) is sucked by capillary forces into the channels. Driving forces are the chemical reaction and the surface tension. The flow rate or enforced amount is approximately described by the Hagen-Poiseuille law and depends on the 4th power of the channel lumen. For large chips or generally in the separation of large-area wafer areas, the removal of the reaction products (eg, SiF 4) by ultrasonic, centrifugal, thermal gradients (for example, by means of IR laser radiation generated), etc. are supported.

Furthermore, vertical holes or slots in the wear layer for the supply and discharge of the etchant can be provided or are etched.

Advantageously, the etchant of the scoring produced between the chips is used or saw frame for the supply and discharge.

The channel-shaped depressions do not necessarily extend linearly. They also need not necessarily have a rectangular cross-section. In particular, the vertical walls or edges of the channels may also have a deviating direction of 90 degrees relative to the surface. This Kantenanschrägung may arise due to the technical features of the etching process, particularly the etching of the mask in wet chemical etching, by itself. special procedures for chamfer or edge overhang but it can be applied. An edge overhang leads to the advantage of a relative magnification of the bonded oxide surface. A method for influencing the Ätzkantenschräge are known to those skilled in the context of wet and dry etching technique used in the semiconductor technology.

The procedure described can be extended or modified in that the channels are not generated or not exclusively in the layers or the connecting, but wholly or partially in the substrates themselves. This can result in a rectangular cross section to an enlargement of the lumen. A practical limit is set by the mechanical behavior of the substrates (bending under thermal stress, Warp).

In particular, at least to dispense with an oxide coating on one of the two mating wafer. In this case, serves to air-exposed wafers always present natural oxide as a bonding surface.

In a preferred embodiment utilizes the fact that in BESOI wafer, the buried insulating layer is freely accessible prior to assembly of the two wafers to BESOI composite. It is also particularly amenable to structuring the bonded oxide. One or both of wafer carrying this case a typically about 1 micron thick Si0 2 - layer. Before the joining into one or both oxides trenches are etched, wherein the edge of the wafer carries a continuous annular oxide region. Then, both wafers are thermally bonded together as usual, and one of the two wafers is thinned to the desired Wear layer thickness by means of one of the conventional thinning methods described in the BESOI technique (grinding, etching, IonCut).

On this BESOI wafer circuits are manufactured then in the conventional technology. During the production, employing thermal and in particular vacuum or gas-phase processes, the wafer on the edge by the oxide ring is hermetically sealed. After the completion of the circuits and opening the wafer located on contiguous boundary layer or dicing the wafer into chips, the buried oxide layer, particularly the channels present therein in the oxide, accessible from the side. An etchant, such as hydrofluoric acid can penetrate into these channels and the connecting aufätzen oxide. The detachment of the thin chips, which is preferably previously fixed to the mechanical support to the front side on a supporting substrate, is carried out at an edge length of about 10 mm is typically in the range of minutes.

The replacement is a low-cost, wet-chemical process which hardly threatened the chip and the integrated value on it.

The control of the layer thickness in the thinning of the BESOI wafer can by the presence of the buried cavities by means of acousto-microscopy (trenches) particularly simple and resolved locally.

Alternatively, the IonCut technique is applicable that avoids grinding and the layer thickness measurement.

Present in the interconnect layer trenches have a beneficial effect on the bonding process. It is known that superficially scratched wafer bonding better. This is so due to the facilitated diffusion of residual gases, adsorbed Feuchigkeit during the beginning of the bonding operation, for the presence of water (hydrophilic surface) is advantageous.

The edge of the wafer or, if necessary, various sub-areas are preferably free of lateral continuous channels. This is easily seen both in Fig. 2b and in FIG. 3. The wafer is characterized to be hermetically sealed after the bonding and tolerate all processes used in a semiconductor device fabrication. In particular, the BESOI-bonding can be carried out under vacuum, or under special forming oxidising or reducing atmospheres.

An advantage of the accessibility of the sacrificial layer or "zipper layer" during the manufacture of RevSOI wafer is that a filling of the cavities can be done with special gases.

In an advantageous embodiment of the bonding process with the addition of trace gases, in particular helium, is performed. By the trapped gas, for example, a particularly simple leak test (helium leak test) of the bonded wafers can be done.

In another embodiment, dopant gases be included for producing a highly doped buried layer or a gettering layer.

The essential characteristic of the lateral accessibility of the insulating oxide layer can also be exploited in order to metallize means of a liquid or a gaseous metal compound, in particular organometallic compounds, the internal surfaces of the channels.

The invention will in the following with reference to

explained embodiments in conjunction with the figures again. In the drawing: Figure 1 schematically illustrates an example of a flowchart of the manufacturing process according to the invention;

2 shows examples of the structure of the interconnection layers on the substrate surface; and Figure 3 is a further example of the structuring, and examples of the sectional shape of the channel-shaped recesses on the connecting surfaces of the substrates.

An example of a flowchart of the overall manufacturing process is shown in FIG. 1.

First, two wafers (1, 2) each having an oxide layer (3, 4) bear on a surface is provided. The oxide layer (4) of the wafer is structured such that strip-shaped channels (5) are formed, which extend over the entire surface. The structures are transferred by one or two preferably unadjusted photographic techniques in the oxide (4). The two wafers are connected to their oxy-founded surfaces, preferably shown by SFB (Silicon fusion bonding), as shown in FIGS. La and lb.

The following is a process as in the BESOI production, wherein the resulting by the bonding wafer stack from the rear of one of the substrates to the desired thickness of the semiconductor region (la) is thinned (Fig. Lc).

Then, the normal IC process, for example a CMOS process, for the manufacture of circuits and / or discrete components (6) in the semiconductor layer (la) of the thinned substrate (1) can be carried out (Fig. Ld). Subsequently, as shown in Fig. le, a dry etching or wet etching of trenches (7) for subsequent separation of the chips, although the trenches be considerably narrower than usual, mechanically generated saw streets. The trenches (7) extending to the buried, patterned oxide layer (4). Even a mechanical sawing of the trenches is possible.

In this etching process, the surface of the ICs (6) must be protected. This is done by applying a layer (8), for example of nitride or photoresist. This protective layer (8) may then be either pulled off or remains as a protective layer for the detachment process of the chips. If the layer (8) removed beforehand, a new protective layer (10) has in front of the detachment process, preferably of photoresist is applied, as shown in Fig. If.

By the preceding etching of the trenches, the channels (5) in the buried oxide layer (4) were exposed (Fig. Le), so that in the subsequent peeling process, which is preferably carried out with HF to penetrate the etching liquid in the channels (5) and the individual chips (9) can be detached from the bottom, as shown in Fig. If. In this detachment process, the selectivity of oxide is utilized to silicon in the etching.

The wafer can be mechanically supported by a handling wafer before the peeling from the front. This handling wafer, however, should have appropriate channels for introducing the etchant. The isolated, fully processed chips (9) can subsequently on a support (11) are applied (Fig. Ig).

A particularly advantageous configuration is shown in Fig. 2a, each of which shows the wafer used in top view and in cross-section. Both wafers (1, 2) carry an about 1 micron-thick Si0 2 layer (3, 4) with typical line widths (s, b) is structured of about 1-2 microns. As an example, also the starting wafer (1) is shown on the right side of the figure before the patterning. The structuring of the layer is wet chemically and unadjusted, is so inexpensive to perform. Limitations in structure and orientation of this orientation Si0 trenches or channels may occur due to the anisotropic mechanical properties of the crystalline wafer (wafer deflection).

In this example, the layers are on both Si wafers (1, 2) is structured such that the trenches after the joining of the wafers extend at an angle of 90 ° to each other. This can achieve the later detachment process a better distribution of the etching liquid. In this example to illustrate two different grave structures were selected. Thus, the Si0 2 layer of a wafer (1) trenches that penetrate the entire layer thickness hl, while in the other layer of the wafer (2), the trenches having a depth only h.3 so that a residual thickness h.2 (h3 + h2 = hl) of the layer remains over the entire surface obtained.

2b, finally, shows a modification of the structure of the two layers of the wafer. Here, the layers in the edge area of ​​the wafer were each brushed so that after bonding of the wafers, a hermetically sealed wafer stack is present.

These wafers shown in Fig. 2 are connected to each other and, as explained in connection with Fig. 1, thinned from one side. The resulting wafer with a thin semiconductor region (la) as a wear layer and built-in "zipper layer" ( "zipper layer") forms the basis of RevSOI (Reversible SOI) technique according to the invention.

In all embodiments, the geometric design of the channels (5), in particular the shape of the lateral course, the partition completely freely against each other in hermetically sealed portions, the formation of islands, etc. bond. However, you should have the necessary for a stable bonding constraints bond force and wafer or substrate bending into account while ensuring an efficient Ätzmitteltransport.

Exemplary shapes of the channels (5) in the two substrates are rectangular structures, circular, meander-shaped or polygon-like structures. The structure is designed to provide on the one hand the silicon membrane (la) maximum mechanical stability and make the other hand, the stripping process as easy and quick as possible. This means that the etching liquid attack after penetration into the channels (5) as homogeneous as possible at all points and is intended to ensure a quick replacement of the ICs. Also, the distances between the channels are variable. Examples of different cross-sectional shapes of the ducts (5) are shown in Fig. 3 wherein the structuring can also be carried into the substrate itself.

The link layer can island-like structured manner or formed strip- or point-shaped. In Fig. 3 a inseiförmige structuring in the form of a lattice structure in this case is shown (right side: unpatterned layer; left side: structured layer). The island-shaped structure in addition to the better distribution of etchant the advantage that mechanical stresses in the wafer can be avoided. Continuous strip as channels hereby have a greater influence than one island-like patterned interconnection layer.

The cross-section through the channels can also under the above point of view, ie, mechanical stability and rapid release of the ICs to be optimized.

Either the surfaces of both to be structured to be connected to wafer or substrates, or only one. For better connection of the two wafers should both have an oxide layer. but this is not mandatory.

Instead of pure oxide in particular the PSG used in CMOS processes, TEOS, PECVD, LPCVD, APCVD BPSG and oxides can be used as materials for the interconnect layers and doped oxides. In this way, the etching rate can be increased if the chip detachment. As a variant of the method for separating or detaching the anodic oxidation can be used in particular for silicon wafers. In this case, to both, on the insulator layer and the silicon wafer connected - applied layers of an electrical voltage which leads to a current and an electrolytic decomposition of the electrodes by anodic oxidation. Here, the compound oxide is infiltrated, and the result by the increase in volume of the oxide forming a detachment and separation of the two silicon wafers part.

The bond strength inventively structured wafer is reduced by the reduced bonding area. While the normal bonding force of conventional

BESOI wafer is> 800 kp / cm 2, it is at said given in FIG. 3 superlattice structure due to the reduced to 25% bond area factor about 200 kp / cm 2. This is sufficient in any case, the thermal stresses during Weiterprozessierung (thermal budget chip production) and the expansion pressure of the enclosed in the bonding gas (max. 4 bar at 1200K) to resist. A channel web width (pitch) of typically 1 micrometer leads at a useful thickness of the silicon of typically 10 microns to no disturbing local or global bending.

Claims

claims
1. A process for the production of thin substrate layers, wherein:
- a first (1) and a second substrate (2) are connected with their front sides via one or more intermediate tie layers (3, 4), wherein at least one of the interconnection layers (3, 4) or the front one of the substrates (1, 2 has) channel-shaped depressions (5) which permit a lateral penetration of an etchant;
- the first substrate (1) from the rear side to a substrate layer (la) is thinned; and
- the substrate layer (la) of the second substrate (2) by introducing the etchant is separated in the channel-shaped recesses (5).
2. The method of claim 1, characterized in that the channel-shaped recesses (5) are produced in the form of a stripe pattern.
3. A method according to claim 1, characterized in that the channel-shaped recesses (5) are produced in the form of a lattice structure.
4. The method according to any one of claims 1 to 3, characterized in that the channel-shaped recesses (5) in the joining layer (3, 4) are generated such that they (3, 4), the connection layer completely penetrate.
5. The method according to any one of claims 1 to 4, characterized in that the channel-shaped recesses (5) are formed with a cross section in the range of 0.1 to 10 microns. 2
6. A method according to any one of claims 1 to 5, characterized in that the first substrate (1) to a substrate layer (la) is thinned to a thickness of less than 50 microns.
7. The method according to any one of claims 1 to 6, characterized in that the channel-shaped recesses (5) are generated so that it does not extend up to the edge of the substrates (1, 2), so that the formed by the channel-shaped recesses space between both substrates is hermetically sealed by the joining of the substrates.
8. The method according to any one of claims 1 to 7, characterized in that the channel-shaped recesses (5) are generated such that a plurality of closed inner spaces are formed between the two substrates which are hermetically sealed.
9. A method according to any one of claims 1 to 8, characterized in that the first substrate (1) a semiconductor substrate is used.
10. A method according to any one of claims 1 to 9, characterized in that a quartz substrate is used as the second substrate (2).
11. The method according to any one of claims 1 to 9, characterized in that the first and second substrates (1, 2), the two partial substrates of a BESOI wafer are used, wherein the compound layers (3, 4), the insulator layers of the BESOI wafer ,
12. The method according to any one of claims 9 to 11, characterized in that the substrate layer (la) prior to stripping to processing for the production of components and / or integrated circuits (6) in the substrate layer (la) is subjected.
13. The method according to claim 12, characterized in that the bonded substrates (la, 2) prior to stripping into smaller units, in particular chips (9) with individual circuits (6) are cut.
14. The method according to claim 12, characterized in that the bonded substrates (la, 2) prior to stripping into smaller cellular units having a line width of a chip or
And multiple line lengths of several chips up to the full width of the substrate, are cut.
15. The method according to any one of claims 1 to 12, characterized in that in the substrate layer (la) is prior to stripping vertical openings or trenches (7), in particular in the form of saw paths between individual integrated circuits (6), generated on the takes place the introduction of the etchant.
16. The method according to any one of claims 1 to 15, characterized in that the connecting layer (3, 4) is an oxide layer or SiC layer.
17. The method according to claim 16, characterized in that an insulating layer of Si0 2 is used in pure or doped form, particularly BSG or BPSG as an oxide layer.
18. The method according to any one of claims 1 to 17, characterized in that is used as an etchant of hydrofluoric acid or a hydrofluoric acid containing etching solution substantially.
19. A method according to any one of claims 1 to 17, characterized in that a suitable gas is used for etching or plasma as the etchant, which burns in the cavities between the two substrates by applying an electric field.
20. The method according to any one of claims 1 to 19, characterized in that, the joining of the two substrates (1, 2) is effected by a bonding process in the presence of a particular gas so that this gas is included in the channel-shaped recesses (5).
21. The method according to claim 20, characterized in that an inert, an oxidizing or a reducing gas may be used.
22. The method according to claim 20, characterized in that a material suitable for a leak test of the compound gas, in particular helium, is used alone or in admixture.
23. The method according to claim 20, characterized in that in the channel-shaped recesses (5) in connecting the substrates of a silicon doping gas serving as PH 3, B 2 H 6 or POC1 included.
24. The method according to any one of claims 1 to 23, characterized in that the etchant is performed by means of pressure through the channel-shaped recesses (5).
25. The method according to any one of claims 1 to 24, characterized in that the detachment by an electric current, which leads to chemical reactions at the two through the connection layer held together substrates is supported.
26. The method according to any one of claims 1 to 25, characterized in that the detachment by ultrasonic, heat, and / or centrifugal force supports and thus accelerated.
27. The method according to any one of claims 1 to 26, characterized in that the channel-shaped recesses are coated entirely or partially on laterally directed surfaces by action of a metal-containing compound with a thin metal lining (5).
28. The method according to claim 27, characterized in that the coating thermally decomposing organometallic compound or an electroless or galvanic deposition takes place by means of a.
9. substrate assembly of a first (1) and a second substrate (2), which are connected with their front sides via one or more intermediate tie layers (3, 4), wherein at least one of the interconnection layers (3, 4) or the front of the comprises substrates channel-shaped depressions (5) having a cross-section and mutual spacings such that a lateral penetration of an etchant and a fast etching away the bonding layer is made possible between the wells.
30, substrate assembly according to claim 29, characterized in that the channel-shaped depressions (5) form a striped pattern.
31, substrate assembly according to claim 29, characterized in that the channel-shaped depressions (5) form a lattice structure.
32. Substrate arrangement according to one of claims 29 to 31, characterized in that the channel-shaped recesses (5), the bonding layer (3, 4) penetrate completely.
33. Substrate arrangement according to one of claims 29 to 32, characterized in that the channel-shaped recesses (5) have a cross section in the range of 0.1 to 10 microns. 2
34. Substrate arrangement according to one of claims 29 to 33, characterized in that the channel-shaped recesses (5) does not extend to the edge of the substrates (1, 2), so that the intermediate space formed by the channel-shaped recesses between both substrates hermetically sealed is.
35. Substrate arrangement according to one of claims 29 to 34, characterized in that the channel-shaped recesses (5) are formed such that a plurality of closed inner regions between two substrates produced which are hermetically sealed.
36. Substrate arrangement according to one of claims 29 to 35, characterized in that the first substrate (1) is a semiconductor substrate.
37. Substrate arrangement according to one of claims 29 to 36, characterized in that the first substrate (1) forms a thin substrate layer (la).
38. Substrate arrangement according to claim 37, characterized in that the substrate layer (la) has a thickness of less than 50 microns.
39. Substrate arrangement according to one of claims 29 to 38, characterized in that the second substrate (2) consists of quartz.
40. Substrate arrangement according to one of claims 37 to 39, characterized in that the substrate layer (la) components and / or integrated circuits (6).
41. Substrate arrangement according to one of claims 29 to 40, characterized in that the bonding layer (3, 4) is an oxide layer or SiC layer.
42. Substrate arrangement according to one of claims 29 to 40, characterized in that the connecting layer (3, 4) is an insulator layer of Si0 2 in pure or doped form, particularly BSG or BPSG.
43. Substrate arrangement according to one of claims 29 to 42, characterized in that a gas is enclosed in the channel-shaped recesses (5).
44. Substrate arrangement according to claim 43, characterized in that the gas is an inert, an oxidizing or a reducing gas.
45. Substrate arrangement according to claim 43, characterized in that the gas contains a for a leak test of the compound of substrates suitable gas, in particular helium.
46. Substrate arrangement according to claim 43, characterized in that in the channel-shaped recesses (5) of the silicon doping serving gas such as PH 3, B 2 H 6 or P0C1 included.
47. Substrate arrangement according to one of claims 29 to 46, characterized in that the channel-shaped recesses (5) are coated entirely or partially on laterally directed surfaces with a thin metal coating.
EP99939373A 1998-06-22 1999-06-22 Method for producing thin substrate layers Withdrawn EP1090422A1 (en)

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PCT/DE1999/001826 WO1999067820A1 (en) 1998-06-22 1999-06-22 Method for producing thin substrate layers

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DE19840421A1 (en) 1999-12-23

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