EP1086485A2 - Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece - Google Patents
Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpieceInfo
- Publication number
- EP1086485A2 EP1086485A2 EP99922934A EP99922934A EP1086485A2 EP 1086485 A2 EP1086485 A2 EP 1086485A2 EP 99922934 A EP99922934 A EP 99922934A EP 99922934 A EP99922934 A EP 99922934A EP 1086485 A2 EP1086485 A2 EP 1086485A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- tool set
- layer
- copper
- metallization
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000001465 metallisation Methods 0.000 title claims abstract description 206
- 238000000034 method Methods 0.000 title claims abstract description 205
- 230000008569 process Effects 0.000 title claims abstract description 179
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 117
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims description 525
- 238000012545 processing Methods 0.000 claims description 323
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 205
- 229910052802 copper Inorganic materials 0.000 claims description 203
- 239000010949 copper Substances 0.000 claims description 203
- 230000004888 barrier function Effects 0.000 claims description 152
- 238000000151 deposition Methods 0.000 claims description 109
- 230000008021 deposition Effects 0.000 claims description 79
- 239000000463 material Substances 0.000 claims description 72
- 229920002120 photoresistant polymer Polymers 0.000 claims description 62
- 238000009713 electroplating Methods 0.000 claims description 61
- 238000005530 etching Methods 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 37
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 28
- 238000004070 electrodeposition Methods 0.000 claims description 28
- 230000001590 oxidative effect Effects 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 22
- 238000001771 vacuum deposition Methods 0.000 claims description 22
- 230000003750 conditioning effect Effects 0.000 claims description 21
- 239000011253 protective coating Substances 0.000 claims description 21
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 19
- 239000005751 Copper oxide Substances 0.000 claims description 19
- 229910000431 copper oxide Inorganic materials 0.000 claims description 19
- 238000007689 inspection Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000003989 dielectric material Substances 0.000 claims description 18
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 17
- 239000011651 chromium Substances 0.000 claims description 17
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 239000008151 electrolyte solution Substances 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 12
- 229910018487 Ni—Cr Inorganic materials 0.000 claims description 12
- 229910052715 tantalum Inorganic materials 0.000 claims description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 238000009877 rendering Methods 0.000 claims 16
- 238000012546 transfer Methods 0.000 abstract description 17
- 239000010408 film Substances 0.000 description 46
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 12
- 239000004020 conductor Substances 0.000 description 12
- 238000000059 patterning Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 239000000126 substance Substances 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000002243 precursor Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- -1 halide compounds Chemical class 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000011161 development Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- 230000001934 delay Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000001143 conditioned effect Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910001080 W alloy Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000012993 chemical processing Methods 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000001311 chemical methods and process Methods 0.000 description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 229910000457 iridium oxide Inorganic materials 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- BEKIOVUSGKFJMC-UHFFFAOYSA-N [Cu+2].[O-2].[Ta+5] Chemical compound [Cu+2].[O-2].[Ta+5] BEKIOVUSGKFJMC-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
Definitions
- An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material.
- Devices which may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors.
- Devices which may be formed within the dielectric include thin-film resistors and capacitors.
- more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer.
- the devices utilized in each dice are interconnected by conductor paths formed within the dielectric.
- two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections.
- an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric. Delays in propagation of electrical signals between devices on a single
- UBSTTTUTE SHEET dice limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
- signal propagation delay may be characterized by a time delay ⁇ .
- R and C are, respectively, an equivalent resistance and capacitance for the interconnect path
- IS AT and VSA T are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path.
- the path resistance is proportional to the resistivity, p, of the conductor material.
- the path capacitance is proportional to the relative dielectric permittivity, Ke, of the dielectric material.
- SUBSI TE SHEET (RULE 26) follows, therefore, that a low-p conductor which can carry a high current density and a low-K e dielectric should be utilized in the manufacture of high-performance integrated circuits.
- copper interconnect lines within a low- K e dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to follow", Semiconductor International, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 ⁇ cm. while resistivities of aluminum-alloy films are higher in the range of 3.0 to 3.5 ⁇ cm.
- Diffusion of copper is one such problem. Under the influence of an electric field, and at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper also moves rapidly through low-Ke dielectrics. Such copper diffusion causes failure of devices formed within the silicon.
- Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed an to oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when
- SllBSTPTE SHEET (RULE 26) compared to a similarly dimensioned non-oxidized copper path.
- a still further problem with using copper in integrated circuits is that it is difficult to use copper in a multi-layer, integrated circuit structure with dielectric materials. Using traditional methods of copper deposition, copper adheres only weakly to dielectric materials.
- FIG. 1 illustrates the process steps generally required for implementing the dual damascene architecture.
- the present inventors have found that the dual damascene architecture may often be difficult for semiconductor manufacturers to implement in large- scale manufacturing processes. It is difficult to deposit a thin silicon nitride etch-
- S BS TTUTE SHEET (RULE 26) stop layer without damaging the underlying low K e material.
- the art of plasma etching dielectric materials is well established, but etching sub-half-micrometer features in a low-Ke dielectric while maintaining selectivity to silicon nitride is difficult.
- the etch-stop layer typically comprised of silicon nitride, has a high dielectric permittivity; thus, unless the etch-stop layer is very thin compared to the line thickness, capacitance between metal lines in the same interconnect level is dominated by coupling through the etch stop.
- Conductivities of known barrier materials are negligible compared to the conductivity of copper; thus the conductance of narrow interconnect lines is markedly reduced by the barrier layer that must be interposed between the copper and dielectric.
- FIG. 2 A processing tool architecture suitable for implementing the dual- damascene process steps illustrated in Fig. 1 is shown in Fig. 2.
- the dual damascene architecture can be implemented with ten tool sets. Formation of each interconnect level generally requires two precision photolithographic processes, two precision etches, four dielectric depositions, barrier and seed layer depositions, a copper deposition, CMP and a post-CMP clean. Both small vias and small trenches must be etched; thus, an etch tool is required to define via features in the silicon nitride film, and a second etch tool is required to define via openings and trench features in the low-Ke dielectric. Using the traditional processing tool architecture of Fig.
- each metallization level requires at least 13 workpiece movements among the tool sets.
- the substantial number of wafer movements used to form a dual- damascene interconnect metallization structure reduces the reliability and yield of to manufacturing process. As the number of wafer movements increases, so does the potential for mis-handling of one or more wafers. Further, implementing a manufacturing facility for applying dual-damascene interconnect metallization structures requires a substantial capital outlay for above purchase of the required tool sets. Such reliability and capital equipment outlay issues are addressed by at least one aspect of the present invention.
- the present inventors have also recognized that copper metallization layers need an effective barrier material to prevent copper diffusion and an effective protective layer over the copper metallization to prevent oxidation of the copper.
- Existing processes for manufacturing such metallization layers are inefficient and are not economically viable for use in large-scale manufacturing operations.
- a semiconductor manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.
- the tool configuration comprises a film deposition tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set.
- the film deposition tool set is used to deposit a conductive barrier layer exterior to the planar dielectric surface of the semiconductor workpiece and a conductive seed layer exterior to the barrier layer.
- the pattern processing tool set is used to provide an interconnect line pattern over the seed layer and to provide a post pattern over interconnect line metallization formed using the interconnect line pattern.
- the wet processing tool set is used to perform at least the following wet processing operations: applying copper metallization, using an electrochemical deposition process, into the interconnect line pattern and the post pattern formed by the pattern processing tool set; removing material applied by the pattern processing tool set to form the interconnect line pattern and the post pattern; and removing portions of the seed layer and the barrier layer that are not overlied by interconnect line metallization.
- the dielectric processing tool set is used to deposit a dielectric layer over the interconnect line metallization and post metallization and for etching the deposited dielectric layer to expose upper connection regions of the post metallization.
- a single metallization level may be formed using a plurality of workpiece movements between the tool sets. Preferably, no more than ten workpiece movements between the tool sets are used, and, even more preferably, no more than five workpiece movements between the tool sets are used. In some instances, it may be necessary or desirable to use a hard mask for the patterning of the interconnect metallization.
- an alternative tool configuration comprises a film deposition tool set, a hard mask formation tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set.
- the film deposition tool set is used to deposit a conductive barrier layer exterior to the planar dielectric surface of the workpiece and a conductive seed layer exterior to the barrier layer.
- the hard mask formation tool set is used to form a hard mask dielectric layer exterior to the seed layer in accordance with one of the disclosed processes, and to form a still further hard mask dielectric layer exterior to the hard mask dielectric layer.
- the pattern processing tool set is used to provide an interconnect line pattern over the hard mask dielectric layer and to provide a post pattern over interconnect line metallization formed using the interconnect line pattern.
- the pattern processing tools set is used to provide a post pattern over the further hard mask dielectric layer so that the post pattern is ultimately formed in the further hard mask dielectric layer.
- the hard mask etching tool set is used to etch exposed regions of the hard mask dielectric layer after formation of the interconnect line pattern thereover and, in accordance with the second disclosed process, the exposed portions of the further hard mask dielectric layer after the formation of the post pattern thereover.
- the wet processing tool set performs at least the following wet processing operations: 1) applying copper metallization, using an electrochemical deposition process, into the interconnect line pattern and the post pattern formed by the pattern processing tool set, 2) removing material applied by the pattern processing tool set to form the interconnect line pattern and the post pattern, 3) removing the hard mask dielectric layer and, if necessary, the further hard mask dielectric layer, and 4) removing portions of the seed layer and the barrier layer that are not overlied by interconnect line metallization.
- the dielectric processing tool set is used to deposit a dielectric layer over the interconnect line metallization and post metallization and for etching the deposited dielectric layer to expose upper connection regions of the post metallization.
- an inspection tool set may also be included.
- the semiconductor workpieces are transferred to the inspection apparatus at various intermediate stages of the metallization process to insure, for example, proper registration of the pattern layers and resulting metallization structures.
- a single metallization level may be formed using no more than ten workpiece movements between the tool sets.
- a process for providing one or more protected copper elements on a surface of a workpiece is also set forth.
- a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is applied over the surface of the barrier layer.
- One or more copper elements are then electroplated on selected portions of the seed layer or, if suitable, the barrier layer. If used, the seed layer is then substantially removed. At least a portion of a surface of the barrier layer is rendered unplatable while leaving the copper elements suitable for electroplating.
- a protective layer is then electroplated onto surfaces of the one or more copper elements.
- a tool architecture for implementing the foregoing process is also set forth.
- the disclosed tool architecture may be used to minimize the number of wafer movements between the tool sets required to form a complete metallization layer structure.
- Fig. 1 is a process flowchart illustrating one manner of implementing a dual-damascene interconnect architecture.
- Fig. 2 illustrates a tool set architecture and corresponding workpiece movements for implementing the process shown in Fig. 1.
- Fig. 3 illustrates one manner of configuring tool sets for the tool set architecture of the present invention.
- Fig. 4 is a process flow chart illustrating one manner of implementing an interconnect metallization structure using a minimal number of workpiece movements between the tool sets of Fig. 3.
- Figs. 5A - 5K illustrate an interconnect metallization structure formed using the process of Fig. 4 at the various stages of the metallization level development.
- Fig. 6 illustrates a tool set architecture and corresponding workpiece movements for implementing the process shown in Fig. 4.
- Fig. 7 illustrates a tool set architecture and corresponding workpiece movements for implementing the process shown in Fig. 4 wherein an inspection tool set is used to check the semiconductor workpieces at intermediate stages of the metallization processing.
- Figs. 8 illustrates one manner of configuring tool set configuration for implementing another process architecture of the present invention in which a hard mask is used for interconnect patterning.
- Figs. 9 and 10 illustrate specific embodiments of tools sets that may be used in the tool set configuration of Fig. 8.
- Fig. 15 is a process flow chart illustrating one manner of forming an interconnect metallization structure using a minimal number of workpiece movements between the tool sets shown in Fig. 8.
- Figs. 12 - 14 illustrate an interconnect metallization structures formed using the process of Fig. 11 at selected stages of the metallization level development.
- Fig. 15 is a process flow chart illustrating a further manner of implementing an interconnect metallization structure using a minimal number of workpiece movements and hard mask patterning.
- Fig. 16 illustrates a tool set configuration and corresponding workpiece movements for implementing the process shown in Fig. 15.
- Figs. 17 and 18 illustrate an interconnect metallization structure formed using the process of Fig. 15 at selected stages of the metallization level development.
- Figs. 19 and 20 illustrate a tool set configuration and corresponding workpiece movements for implementing the processes shown in Figs. 11 and 15, respectively, wherein an inspection tool set is used to check the workpieces at intermediate stages of the metallization processing.
- Single Metallization Level is defined as a composite level of a workpiece that is exterior to the substrate.
- the composite level comprises one or more interconnect lines and one or more interconnect posts that are substantially covered by a dielectric layer so that the dielectric layer insulates selected interconnect lines and interconnect posts that are not designed to be interconnected from one another.
- Substrate is defined as a base layer of material over which one or more metallization levels are disposed.
- the substrate may be, for example, a semiconductor wafer, a ceramic block, etc.
- Workpiece is defined as an object that at least comprises a substrate, and may include further layers of material or manufactured components, such as one or more metallization levels, disposed on the substrate.
- the present invention employs a novel approach to applying copper metallization to a workpiece, such as a semiconductor article.
- the approach results in a copper metallization level that is readily manufactured using a minimal number of processing tool sets and a minimal number of workpiece movements between the tool sets.
- the manufacturing process steps used to construct the resulting copper interconnect level avoids many of the inherently problematic processing steps associated with damascene interconnect structures. For example, seed layers, copper metallization layers, and barrier layers no longer need to be deposited into high aspect ratio trenches and vias using non-conformal vapor deposition processes. Rather, the barrier and metal seed layers are preferably applied to the workpiece in a blanket deposition process over planarized surfaces of the workpiece.
- Subsequent deposition of the copper metallization used to form at least the lines is accomplished using an electrochemical deposition process in which the copper is deposited beginning at the bottom of an opening in a patterned hard mask layer, thereby ensuring that the resulting line is completely formed and eliminating the pinch-off problems associated with the three-dimensional filling of the trench and via employed in damascene processing.
- deposition of the copper metallization used to form the posts is accomplished using an electrochemical deposition process in which the copper is deposited beginning at the bottom of an opening in either a patterned hard mask layer or a patterned photoresist layer.
- chemical mechanical polishing processes may be avoided in favor of electrochemical planarization and/or etching processes.
- Manufacturing of the disclosed interconnect level architecture is accomplished with a minimal number of workpiece processing tool sets and with a minimal number of workpiece movements between the tool sets. As such, the cost of capital equipment in the design of a manufacturing facility used for the generation of such interconnects structures may be minimized. Further, by reducing the number of workpiece movements between the tool sets, the risk of damage to the workpieces is substantially decreased.
- the basic tool sets for implementing a tool architecture in accordance with one embodiment of the present invention is illustrated in Fig. 3. As shown, the tool sets comprise a film deposition tool set 20, a pattern processing tool set 25, a wet processing tool set 30, and a dielectric processing tool set 35.
- the film deposition tool set 20 is preferably a vacuum deposition tool set.
- the film deposition tool set 20 deposits one or more films on generally planar surfaces of the semiconductor workpiece.
- Such film deposition is preferable to depositing the films in the micro-recessed features employed in damascene processing.
- low cost vacuum deposition techniques such as physical vapor deposition (PVD)
- PVD physical vapor deposition
- CVD chemical vapor deposition
- the particular embodiment of the film deposition tool set 20 shown in Fig. 3 includes an input station 40 disposed to receive semiconductor workpieces.
- the input station 40 may be configured to accept the semiconductor workpieces in multi-workpiece cassettes or in multi-workpiece or single-workpiece hygienic pods. Semiconductor workpieces are transferred from the input station 40 to a
- the semiconductor workpieces are first transferred to a conditioning station 45 where the surface of a generally planar dielectric layer disposed exterior to the semiconductor workpiece substrate is treated to enhance adhesion of a subsequent film layer.
- a conditioning station 45 where the surface of a generally planar dielectric layer disposed exterior to the semiconductor workpiece substrate is treated to enhance adhesion of a subsequent film layer.
- adhesion enhancement of the dielectric layer can be accomplished using any one or more known dry chemical processes. Depending on the characteristics of the dielectric layer and the subsequent film layer, adhesion enhancement may not be necessary.
- the conditioning station 45 need not be included in the film deposition tool set 20.
- Each semiconductor workpiece is then provided to a bonding film application station 50 where an optional bonding layer is applied exterior to (preferably, directly on) the dielectric layer.
- Materials suitable for the bonding layer include aluminum, titanium, and chromium.
- materials for the bonding layer are deposited using a vapor deposition technique, such as PVD or CVD.
- the bonding layer may not be desired and, as such, the bonding film application station 50 need not be included in the film deposition tool set 20.
- a barrier layer application station 55 is disposed within the film deposition tool set 20 to apply a barrier layer material exterior to the dielectric material of the semiconductor workpiece.
- the barrier layer may be comprised of tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy, or tungsten nitride.
- the interconnect level makes contact to terminals of semiconductor devices, it is advantageous to employ a composite barrier comprised of two layers, as taught by Stevens in U.S. Patent No. 4,977,440 and in U.S. Patent No. 5,070,036.
- the barrier layer may be formed using a vacuum deposition process such as PVD or CVD.
- the film deposition tool set 20 preferably includes a seed layer application station 60.
- the seed layer application station 60 preferably deposits the seed layer using a PVD or CVD process.
- the seed layer is preferably copper, but seed layers may also be comprised of metals such as nickel, iridium, platinum, palladium, chromium, vanadium, or other conductive materials such as iridium oxide.
- the semiconductor workpieces are transferred to an output station 62 for subsequent transfer to other semiconductor processing tool sets.
- the pattern processing tool set 25 includes a plurality of processing stations which are used to provide an interconnect line pattern over the seed layer applied by the film deposition processing tool set 20.
- the pattern processing tool set 25 is also used to provide a post pattern over the interconnect metallization that is formed using the interconnect line pattern.
- the interconnect line pattern defines the regions in which primary conductor paths are provided for horizontal electrical interconnection in a plane of the semiconductor workpiece
- the post pattern defines the regions in which primary conductor paths are provided for vertical electrical connections between adjacent planes of the semiconductor workpiece.
- the pattern processing tool set 25 is a photolithography tool set.
- the semiconductor workpieces undergo standard photolithographic conditioning, coating, and baking processes at processing stations 70, 75, and 80, respectively. After the photoresist is baked onto the semiconductor workpiece at station 80, the workpiece is transferred to the input station 85 of a photoresist exposure apparatus 90.
- the photoresist exposure apparatus 90 may be, for example, a step and repeat apparatus that exposes the photoresist to ultra-violet light in a manner that selectively affects the photoresist layer so that portions of the photoresist layer may be subsequently removed to form the interconnect line or post patterns.
- the semiconductor workpiece is provided to the output station 95 of the apparatus 90 for transfer to further processing stations that selectively remove the photoresist layer to form a pattern in the layer consistent with the pattern exposure in the photoresist exposure apparatus 90.
- processing stations include a photoresist development station 100 and a plasma cleaning ("de-scum") station 105.
- the semiconductor workpieces may be transferred to an output station 110 or, optionally, to an output station.
- TE SHEET RULE 26 intermediate UV cure station 107 and therefrom to output station 110 for provision to one or more further tool sets.
- the wet processing tool set 30 implements a wide range of processes used to form the interconnect line metallization and post metallization structures.
- the wet processing tool set 30 may be implemented in an LT-210TM brand copper plating tool available from Semitool, Inc., of Kalispell, Montana.
- Such a wet processing tool set preferably includes input station 115 for receiving semiconductor workpieces in multi-workpiece cassettes or in single-workpiece or multiple- workpiece pods, and an output station 120 for supplying processed workpieces in pods or cassettes to one or more subsequent tool sets. Stations 115 and 120 are preferably combined into a single input/output station.
- Dual robot arms 125a and 125b are disposed for travel in the direction of arrows 130 and are used to transfer the semiconductor workpieces between a plurality of processing stations and to and from the output station 120 and input station 115.
- the processing stations of the wet processing tool set 30 perform at least three primary wet processing operations.
- the wet processing tool set 30 includes processing stations used to apply copper metallization, using an electrochemical deposition process, into the interconnect line pattern and the post pattern formed by the pattern processing tool set 25.
- electrochemical deposition stations 135 and 140 are provided.
- a conditioning station 145 may be employed to condition surfaces of the semiconductor workpiece that are to be electrochemically deposited with copper.
- the wet processing tool set 30 includes one or more processing stations used to remove the material that is used to form the interconnect line pattern and the post pattern that is applied by the pattern processing tool set 25. Processing station 150 and rinse/dry stations 155 and 160 are included for this purpose. Finally, one or more processing stations are employed to either remove portions of the seed layer and/or barrier layer that are not overlied by interconnect lines of metallization and/or to otherwise render such portions non-conductive. As will be set forth in further detail below, oxidizing station 165, etching station 170, and electrochemical removal station 175 may be used for such seed layer and barrier layer processing. Oxidizing station 165 and etching station 170 may be consolidated into a single processing station.
- the processing tool 30 may be used to apply a protective coating over the interconnect line metallization and post metallization.
- electrochemical deposition station 180 may be used for this purpose.
- Materials for the protective coating are preferably those which impede both copper migration into the dielectric and oxidation of the coated copper.
- Materials that may be employed for the protective coating include, for example, nickel, nickel alloys and chromium.
- the dielectric processing tool set 35 includes a plurality of processing stations that are used to deposit a dielectric layer over the interconnect line metallization and post metallization. Additionally, the dielectric processing tool set 35 includes one or more processing stations for etching the deposited dielectric layer to expose upper connection regions of the post metallization. In the illustrated embodiment, the dielectric processing tool set 35 includes an input station 185 that is adapted to receive semiconductor workpieces in multi- workpiece cassettes or in single-workpiece or multiple-workpiece hygienic pods. Semiconductor workpieces are provided from the input station 185 to a coating station 190 where the surface of each semiconductor workpiece is coated with a dielectric precursor or the like.
- the separate input and output stations 40 and 62 for tool set 20 may optionally be combined in a single input/output station.
- separate input and output stations 65 and 110 of tool set 25 may optionally be combined in a single input/output station, and the single input/output station 115 for tool set 30 may optionally be divided into separate input and output stations.
- One or more cassettes or pods may be resident in the the input/output stations at any time.
- Separate input and output stations 185 and 210 for tool set 35 may also optionally be combined in a single input/output station.
- SUBSTTTUTI SHEET (RULE 26) with Fig. 3 may be used to implement the manufacturing process procedures described below in connection with Fig. 4 with a minimal number of workpiece movements between the tool sets.
- Process steps 215, 225, 237 and 260 of Fig. 4 may be implemented in the film deposition tool set 20.
- Process steps 270 and 300 may be implemented in the pattern processing tool set 25.
- Process steps 280, 290, and 308 through 380 may be implemented in the wet processing tool set 30.
- Process steps 400 through 425 are implemented in the dielectric processing tool set 35.
- a single interconnect metallization level may be formed with no more than ten and, preferably no more than five workpiece movements between the tool sets, substantially less than the 13 workpiece movements required for the dual-damascene process described above.
- a single workpiece movement designated at arrow 500 of Fig. 6, is employed for transferring the workpieces between the film deposition tool set 20 and the pattern processing tool set 25.
- Three workpiece movements, designated at arrows 505, 510, and 515, are employed to transfer the workpieces between the pattern processing tool set 25 and the wet processing tool set 30.
- a single workpiece movement is employed to transfer the workpieces between the wet processing tool set 30 and the dielectric processing tool set 35.
- a single workpiece movement is employed to transfer the workpieces between the wet processing tool set 30 and the dielectric processing tool set 35.
- a dielectric layer 210 is provided over a substrate 215, such as a semiconductor wafer.
- the dielectric layer 210 likely includes contacts to metal-filled vias exposed at the top of the dielectric layer that have been planarized and that provide an electrical connection between one or more components below the planarized surface of the dielectric layer.
- the one or more components below the planarized surface of the dielectric layer may include a further interconnect metallization level, a direct connection to a semiconductor component formed in the substrate, etc.
- the dielectric layer 210 preferably has a relative permittivity of less than 4 and may be formed by spin application or spray application of a precursor material or precursor materials followed by a cure, in either an anaerobic or in an oxygen-containing atmosphere, at a temperature of less than 450C.
- a preferred choice for the dielectric material is benzocyclobutene (BCB).
- the surface of the dielectric layer 210 is conditioned, as at step
- the surface of the dielectric layer 210 may be conditioned using wet or dry chemical processes or through an ion milling process.
- the arrows 220 in Fig. 5A depict conditioning of the upper surface of the dielectric layer 210 by, for example, impinging argon or nitrogen ions.
- the upper surface may be conditioned by a brief (10 to 30 second) etch in a solution comprised of 1% to 2% hydrofluoric acid in deionized water.
- an optional bonding layer 230 may be applied to the surface of the dielectric layer 210.
- the bonding layer 230 may be comprised of, as noted above, aluminum, titanium, or chromium which has been deposited using a vapor deposition technique such as PVD.
- a barrier layer 240 is deposited over the bonding layer 230, if used, or directly onto the surface of the dielectric layer 210.
- the barrier layer 240 as illustrated, is deposited over a generally planar surface of a semiconductor workpiece thereby eliminating the need to apply the barrier layer material into high aspect ratio trenches and vias.
- the barrier layer 240 may be comprised of tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy, or tungsten nitride.
- a composite barrier comprised of two layers, as taught by Stevens in U.S. Patent No. 4,977,440 and in U.S. Patent No. 5,070,036 may be used for contact to semiconductor device contacts. It is noted that a deposited bonding layer is not required to achieve acceptable adhesion between a tantalum barrier layer and a
- the barrier layer 240 may be made to be sufficiently conductive to facilitate a subsequent electrochemical deposition process for depositing interconnect line and post metallization. However, if the conductivity of the barrier layer 240 is insufficient, a seed layer may be required.
- Fig. 5B and step 260 of Fig. 4 illustrate application of a seed layer 265 that is deposited, for example, in a PVD or CVD process.
- the seed layer 265 is typically copper, but may also be comprised of metals such as nickel, iridium, platinum, palladium, chromium, vanadium or other conductive materials such as iridium oxide.
- Preferred thicknesses for the seed and barrier layers are in the range of 200 to 600 A.
- a plasma treatment may be included as a final step in the photolithographic procedure or at any processing stage prior to the electrochemical deposition of the interconnect line metallization in order to remove photoresist residues from exposed portions of the seed layer surface.
- a treatment in HMDS may be employed to form a layer 270 that promotes adhesion between photoresist and the copper seed layer 265.
- a thin (less than 100 A) layer of copper oxide may be formed on the upper surface of the seed layer 265 to form layer 270 and thereby promote adhesion between the seed layer and photoresist.
- interconnect line metallization 285 is formed by selective electrochemical deposition of, for example, copper into the photoresist interconnect pattern.
- An acidic chemical bath is preferably employed for the electrochemical depositions.
- the chemical bath may be prepared by adding copper suifate and sulfuric acid to deionized water.
- small concentrations of materials which affect metal grain size and film conformability may optionally be included in the chemical bath.
- Removal of the photoresist may be accomplished by exposing the photoresist to a solvent or oxidant (such as ozonated DI water) followed by a rinse in water. Such a step is illustrated at steps 290 and 295 of Fig. 4 and should be sufficient to remove photoresist after selective metal depositions. The resultant structure is shown in Fig. 5D.
- a solvent or oxidant such as ozonated DI water
- a further photoresist pattern 305 is applied to the semiconductor workpiece in order to form openings through which the post metallization 307 may be electrochemically deposited as at step 308.
- a metallized post 307 is shown in Fig. 5F.
- the photoresist pattern is removed thereby leaving the interconnect structure of Fig. 5G
- the seed layer 265 is partially or completely removed by, for example, an electrochemical etching process.
- Electrochemical etching may be accomplished by exposing the seed layer to a suitable electrolyte solution, such as a solution containing phosphoric acid, while the seed layer 265 is held at a positive electrical potential relative to an electrode that is immersed in the electrolyte solution.
- a suitable electrolyte solution such as a solution containing phosphoric acid
- Fig. 5H Shown in Fig. 5H is a representative cross section after partial removal of the exposed seed layer followed by formation of copper tantalum oxide on the exposed surface of the barrier layer and formation of copper oxide on exposed surfaces of lines and posts.
- the seed layer 265 may be partially removed by immersion in electrolyte solution which contains phosphoric acid while the seed layer is held at a positive electrical potential relative to an electrode that is immersed in the same electrolyte solution.
- the seed layer that remains after electrochemical etching is then converted to copper oxide.
- the electrochemical etch may be omitted and the seed layer may be completely converted to copper oxide.
- exposed surfaces of the copper structures 285, 307, and 265 and the barrier layer 240 are oxidized by exposure to a solution comprised of air, oxygen, steam, water including dissolved oxygen, or ozone dissolved in water. Alternatively, the surfaces may be oxidized by heating in an oxygen containing atmosphere.
- the resultant copper oxide may be removed by exposure to a solution which contains sulfuric acid, hydrochloric acid, or both sulfuric and hydrochloric acid. Referring to Fig. 3, copper oxide removal may be accomplished at station 145 of tool set 25.
- a protective coating 370 is preferably provided over the remaining interconnect structures.
- Such a protective coating is preferably formed in an electrochemical process, such as at steps 375, that causes a material to deposit on the exposed copper but not on the oxide-coated, exposed barrier material.
- Materials for the protective coating preferably include those which impede copper migration into the dielectric and, further, which impede oxidation of the coated copper.
- Such materials include nickel, nickel alloys and chromium.
- Preferred thicknesses for the protective coating are in the range of 5 ⁇ A to 50 ⁇ A. The resultant structure is shown at Fig. 51.
- the barrier layer 240 and its overlying oxide layer may be removed where it is not covered by an overlying copper feature by a wet-chemical etch.
- the wet chemical etch may comprise a solution of 1% to 5% hydrofluoric acid in water, provided that the barrier removal procedure does not excessively attack either copper features of the interconnect structure 302 or the dielectric 210 that underlies the barrier layer 240.
- a further dielectric layer 410 is formed to a thickness sufficient to cover the upper surfaces of the posts of the interconnect structure.
- the further dielectric layer 410 is preferably formed by spin application or spray application of a precursor material or precursor materials followed by a cure, in either an anaerobic or in an oxygen- containing atmosphere, at a temperature of less than 450C.
- Composition of the dielectric layer 410 may be different than or the same as the composition of the dielectric layer 210.
- the upper surface of the layer 410 is etched back to expose upper contact regions 420 of the post structure 307.
- a blanket plasma etch may be employed to reduce the thickness of layer 410 until all upper surfaces 420 of the post structures 307 are exposed.
- Etching of BCB, for example, may be done in a plasma that contains oxygen and fluorine ions. Such a step is illustrated at step 425 of Fig. 4 and the resulting structure is shown at Fig. 5K.
- FIG. 7 A further embodiment of a tool architecture suitable for implementing the foregoing process steps is illustrated in Fig. 7.
- the tool architecture illustrated in Fig. 7 is similar to the specific embodiment of the tool sets shown in Fig. 3 as incorporated in the tool architecture of Fig. 6 (although it will be recognized that the more generic processing tools set designations of Fig. 6 may likewise be used in Fig. 7 without incorporating the specific tool set implementations disclosed in Fig. 3).
- the tool architecture of Fig. 7 includes an inspection tool set 600 that is used to check the semiconductor workpieces at intermediate stages of the application of a single metallization level. The intermediate checks are used, for example, to insure proper registration of the various photoresist patterns and corresponding metallization and, further, to insure proper dielectric etch-back.
- each semiconductor workpiece may be provided to the inspection tool set 600 after processing steps 270, 290, 300, 380 and 425 that are illustrated in Fig. 4.
- ten workpiece movements are used to transfer the semiconductor workpiece between the various tools of the tool processing architecture to form a single interconnect metallization level.
- the inspection tool set 600 may be implemented, for example, with inspection devices available from KLA-Tencor.
- At least four embodiments of a process for manufacturing a metallization level using hard mask patterning are disclosed.
- only the interconnect metallization pattern is formed using a hard mask dielectric layer.
- both the interconnect metallization pattern and the post pattern are formed using hard mask dielectric layers.
- the third and fourth process embodiments are respectively similar to the first and second process embodiments, except that intermediate inspections are performed during the processing to ensure proper formation of the interconnect line and post patterns. Processing architectures, processing tool sets, and workpiece movements are set forth with respect to each of the process embodiments.
- the tool sets comprise a film deposition tool set 1020, a hard mask formation tool set 1023, a pattern processing tool set 1025, a hard mask etch tool set 1027, an electrochemical/wet processing tool set 1030, and a dielectric processing tool set 1035.
- the film deposition tool set 1020 is preferably a vacuum deposition tool set.
- the film deposition tool set 1020 deposits one or more films on generally planar surfaces of the workpiece. Such film deposition is preferable to depositing the films in the micro-recessed features employed in damascene processing.
- low cost vacuum deposition techniques such as physical vapor deposition (PVD)
- PVD physical vapor deposition
- CVD chemical vapor deposition
- Fig. 9 includes a plurality of processing stations for conditioning a surface of the workpiece, depositing a bonding layer, depositing a barrier layer, and depositing a seed layer on the workpiece.
- the workpieces are first transferred to a conditioning station where the surface of a generally planar dielectric layer disposed exterior to the workpiece substrate is treated to enhance adhesion of a subsequent film layer.
- adhesion enhancement of the dielectric layer can be accomplished using any one or more known plasma processes.
- the workpieces are first transferred to a conditioning station where the surface of a generally planar dielectric layer disposed exterior to the workpiece substrate is treated to enhance adhesion of a subsequent film layer.
- Such adhesion enhancement of the dielectric layer can be accomplished using any one or more known plasma processes.
- SUBSTmrTE SHEET (RULE 26) characteristics of the dielectric layer and the subsequent film layer, adhesion enhancement may not be necessary. In such instances, a conditioning station need not be included in the film deposition tool set 20.
- Each workpiece is then provided to a bonding film application station where an optional bonding layer is applied exterior to (preferably, directly on) the dielectric layer.
- Materials suitable for the bonding layer include aluminum, titanium, and chromium.
- the bonding layer may not be desired and, as such, a bonding film application station need not be included in the film deposition tool set 1020.
- a barrier layer application station is used to apply a barrier layer material exterior to the dielectric material of the workpiece.
- the barrier layer may be comprised of tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy, or tungsten nitride.
- the interconnect level makes contact to terminals of semiconductor devices, it is advantageous to employ a composite barrier comprised of two layers, as taught by Stevens in U.S. Patent No. 4,977,440 and in U.S. Patent No. 5,070,036.
- the film deposition tool set 1020 preferably includes a seed layer application station.
- the seed layer application station preferably deposits the seed layer using a PVD or CVD process.
- the seed layer is preferably copper. After the seed layer has been applied, the workpieces are transferred to an output station for subsequent transfer to other processing tool sets.
- the hard mask formation tool set 1023 includes a plurality of processing stations which are used to provide a hard mask dielectric layer over the seed layer applied by the film deposition processing tool set 1020. This hard mask dielectric layer is ultimately patterned in accordance with a photoresist pattern applied by the pattern processing tool set 1025. One or more hard mask layers are applied to provide the patterned masks used for depositing one or both of the interconnect line and post metallization.
- the interconnect line pattern defines the regions in which primary conductor paths are provided for horizontal electrical interconnection in a plane of the workpiece, while the post pattern defines the regions in which primary conductor paths are provided for vertical electrical connections between adjacent planes of the workpiece.
- the hard mask formation tool set 1023 includes an input station 1465 that preferably receives the workpieces in multi-workpiece cassettes or in single-workpiece or multi- workpiece hygienic pods. From the input station 1465, a workpiece is provided to a coating station 1467 where the workpiece is coated with one or more precursor materials. The workpiece is then provided to a baking station 1470 to, for example, bake out solvents. The baking station 1470 is typically a hot plate. After processing at the baking station 1470, the workpiece is provided to a cure station 1473. Depending on the duration of the cure cycle, the cure station 1473 may be a hot plate or a small batch furnace. The curing cycle must not cause damage to the workpiece. After curing, the workpiece is provided to the output station 1475. Although the illustrated embodiment is shown with separate input and output stations, the stations may be combined into a single input/output station.
- the pattern processing tool set 1025 of Fig. 8 includes a plurality of processing stations which are used to provide an interconnect line pattern over the hard mask layer applied by the hard mask formation tool set 1023.
- the pattern processing tool set 1025 is also used to provide a post pattern over the interconnect metallization that is formed using the interconnect line pattern.
- the pattern processing tool set 1025 is used to provide a post pattern over a further hard mask layer deposited by the hard mask formation tool set 1023 which, in turn, provides a mask for the deposition of the post metallization.
- the pattern processing tool set 1025 is a photolithography tool set.
- the pattern processing tool set 1025 includes an input station receiving workpieces, such as semiconductor wafers, in multi-workpiece cassettes or in single-workpiece or multi-workpiece hygienic pods. Within tool set 1025 the workpieces sequentially undergo the standard photolithographic processes of conditioning, coating, and baking.
- the workpiece is transferred to the input station of a photoresist exposure apparatus such as a step and repeat apparatus that exposes the photoresist to ultra-violet light in a manner that selectively affects the photoresist layer so that portions of the photoresist layer may be subsequently removed to form the interconnect line or post patterns.
- a photoresist exposure apparatus such as a step and repeat apparatus that exposes the photoresist to ultra-violet light in a manner that selectively affects the photoresist layer so that portions of the photoresist layer may be subsequently removed to form the interconnect line or post patterns.
- the workpiece is provided to an output station for transfer to further processing stations that selectively remove the photoresist layer to form a pattern in the layer consistent with the pattern exposure in the photoresist exposure apparatus.
- processing stations include a photoresist development station and may include a plasma cleaning ("de-scum") station.
- the workpieces are transferred to an output station for provision to one or more further tool sets.
- the hard mask etch tool set 1027 includes an input station 1480 that preferably receives the workpieces in multi-workpiece cassettes or in single-workpiece or multi-workpiece hygienic pods. From the input station 1480, a workpiece is provided to an etching station 1483 where the hard mask layer is selectively etched through open regions of the patterned photoresist layer applied by the pattern processing tool set 1025. After the hard mask layer has been etched to form the desired mask pattern, the workpiece is provided to output station 1485.
- the hard mask etch tool set 1027 may be a plasma etch apparatus such as one sold by
- the electrochemical/wet processing tool set 1030 of Fig. 8 implements a wide range of processes used to form the interconnect line metallization and post metallization structures.
- the wet processing tool set 1030 may be implemented in an Equinox brand tool or an LT-210 brand tool, both of which are available from Semitool, Inc., of Kalispell, Montana.
- an electrochemical/wet processing tool set preferably includes input and output stations and a plurality of stations for performing electrochemical and wet chemical processes.
- the processing stations of the wet processing tool set 30 perform at least three primary wet processing operations.
- the wet processing tool set 30 includes processing stations used to apply copper metallization, using an electrochemical deposition process, into the interconnect line pattern and the post pattern formed using the pattern processing tool set 25 and/or the hard mask etch tool set 1027. Additionally, a conditioning station may be employed to condition surfaces of the workpiece that are to be electrochemically deposited with copper.
- the tool set 30 includes one or more processing stations used to remove the hard mask material that is used to define the interconnect line pattern and, in some process embodiments, the post pattern that is applied by the hard mask formation tool set 1023 and etched by the hard mask etch tool set 1027.
- the wet processing tool set 30 includes one or more processing stations used to remove the photoresist material that is employed to define the interconnect line pattern in the hard mask layer and, in some process embodiments, the photoresist material that is employed to define the post pattern. Typically, a solvent station and rinse/dry stations are provided for photoresist removal. Finally, one or more processing stations are employed to either remove portions of the seed layer and/or barrier layer that are not overlied by interconnect lines and/or to otherwise render such portions non-conductive.
- the processing tool 30 may be used to apply a protective coating over the interconnect line metallization and post metallization.
- an electrochemical deposition station may be used for this purpose.
- Materials for the protective coating are preferably those which impede both copper migration into the dielectric and oxidation of the coated copper.
- Materials that may be employed for the protective coating include, for example, nickel, nickel alloys and chromium.
- the dielectric processing tool set 1035 includes a plurality of processing stations that are used to form a dielectric layer over the interconnect line metallization and post metallization. Additionally, the dielectric processing tool set 1035 includes one or more processing stations for etching the deposited dielectric layer to expose upper connection regions of the post metallization. With respect to the specific embodiment of the dielectric processing tool set shown in Fig. 9, the workpieces are provided from an input station to a coating station where the surface of each workpiece is coated with a dielectric precursor or the like. After a workpiece has been coated, it is sequentially supplied to a baking station and a curing station to complete formation of a dielectric material that surrounds the interconnect line metallization and post metallization.
- the processing tool sets may be used to implement the manufacturing process procedures described below in connection with Fig. 11 with a minimal number of workpiece movements between the tool sets.
- Process steps 1215, 1225, 1237 and 1260 of Fig. 11 may be implemented in the film deposition tool set 1020.
- Process steps 1270 and 1308 may be implemented in the pattern processing tool set 1025.
- Process steps 1277, 1280, and 1309 through 1380 may be implemented in the wet processing tool set 1030.
- Process steps 1400 through 1425 are implemented in the dielectric processing tool set 1035.
- Process step 1261 may be implemented in the hard mask formation tool set 1023, and process step 1273 may be implemented in the hard mask etching tool set 1027.
- a single interconnect metallization level may be formed with no more than seven workpiece movements between the tool sets when a hard mask is used to pattern only the interconnect lines.
- a single interconnect metallization level as shown in Fig. 16, may be formed with no more than nine workpiece movements.
- a single workpiece movement designated at arrow 1500 of Fig. 8, is employed for transferring the workpieces between the film deposition tool set 1020 and the hard mask formation tool set 1023.
- One workpiece movement is employed to transfer the workpieces between the hard mask formation tool set 1023 and the pattern processing tool set 1025.
- Two workpiece movements 1510 and 1512 are used to transfer the workpieces between the pattern processing tool set 1025 and the wet processing tool set 1030.
- a single workpiece movement 1515 is used to transfer the workpieces between the pattern processing tool set 1025 and the hard mask etching tool set 1027.
- a single workpiece movement 1517 is used to transfer the workpieces between the hard mask etching tool set 1027 and the wet processing tool set 1030.
- a single workpiece movement 1520 is employed to transfer the workpieces between the wet chemical processing tool set 1030 and the dielectric processing tool set 1035.
- a hard mask dielectric layer 1263 is deposited over the seed layer 1265 at the hard mask formation tool set 1023.
- steps well-established in the photolithographic arts may be employed to deposit the interconnect line pattern over the hard mask dielectric layer 1263 using, for example, photoresist as an intermediate mask.
- the hard mask dielectric layer 1263 is then selectively etched through open portions of the photoresist layer 1272 as shown by step 1273.
- Step 1273 takes place at the hard mask etching station 1027.
- the photoresist layer 1272 is removed at a wet chemical processing station within tool set 1030 thereby leaving a patterned hard mask dielectric layer 1263 having substantially vertical walls for defining the interconnect metallization pattern.
- interconnect line metallization 1285 is formed by selective electrochemical deposition of, for example, copper into the hard-mask interconnect pattern.
- An acidic chemical bath is preferably employed for the electrochemical depositions.
- the chemical bath may be prepared by adding copper suifate and sulfuric acid to deionized water.
- small concentrations of materials which affect metal grain size and film conformability may optionally be included in the chemical bath.
- Fig. 12 The structure that results after the electrochemical deposition of the copper is illustrated in Fig. 12.
- the generally planar surface of the workpiece is illustrated at 1210
- a conditioned portion of the workpiece is illustrated at 1230
- the barrier layer is illustrated at 1240
- the hard mask layer is illustrated at 1263
- the seed layer is illustrated at 1265
- an exemplary interconnect metallized line is illustrated in cross-section at 1285.
- SUBSTTTUTE SHEET (RULE 26) using, for example, a photoresist layer that is applied and patterned using conventional photoresist patterning techniques. As at step 1308, this further photoresist pattern is applied to the workpiece in order to form openings through which the post metallization may be electrochemically deposited.
- Fig. 13 illustrates the structure that results after patterning of a photoresist layer 1305 and electrochemical deposition of the post metallization 1307 at step 1309 of Fig. 11.
- the photoresist pattern is removed at step 1310 and the hard mask dielectric layer is removed at step 1313. Removal of the hard mask dielectric layer preferably takes place within tool set 1030, but may also take place at the hard mask etching tool set 1027 with the addition of two further wafer movements.
- the hard mask dielectric layer 1263 may be removed prior to the formation of the patterned photoresist layer.
- Fig. 14 illustrates the structure that results after patterning of a photoresist layer 1305 and electrochemical deposition of the post metallization 1307.
- a treatment in HMDS may be employed to form a layer that promotes adhesion between photoresist 305 and the copper seed layer 1265.
- a thin (less than 100 A) layer of copper oxide may be formed on the upper surface of the seed layer 1265 to form layer 1278 and thereby promote adhesion between the seed layer and photoresist.
- the seed layer 1265 is partially or completely removed by, for example, an electrochemical etching process.
- Electrochemical etching may be accomplished by exposing the seed layer to a suitable electrolyte solution, such as a solution containing phosphoric acid, while the seed layer 1265 is held at a positive electrical potential relative to an electrode that is immersed in the electrolyte solution.
- a suitable electrolyte solution such as a solution containing phosphoric acid
- the barrier layer 1240 are oxidized by exposure to water including dissolved air, oxygen, or ozone. Alternatively, the surfaces may be oxidized by heating in an oxygen containing atmosphere. As illustrated at step 1325, the resultant copper oxide may be removed by exposure to a solution which contains sulfuric acid, hydrochloric acid, or both sulfuric and hydrochloric acid. Copper oxide removal may be accomplished, for example, at an etch station of tool set 30.
- a protective coating is preferably provided over the remaining interconnect structures.
- Such a protective coating is preferably formed in an electrochemical process, such as at step 1375, that causes a material to deposit on the exposed copper but not on the oxide-coated, exposed barrier material.
- Materials for the protective coating preferably include those which impede copper migration into the dielectric and, further, which impede oxidation of the coated copper.
- Such materials include nickel, nickel alloys and chromium.
- Preferred thicknesses for the protective coating are in the range of 5 ⁇ A to 50 ⁇ A. Referring to step 1380 of Fig. 11, the barrier layer 1240 and its overlying oxide layer may be removed where it is not covered by an overlying copper
- SHEET RULE 26 feature by a wet-chemical etch.
- the wet chemical etch may comprise a dilute acid, such as solution of 1% to 5% hydrofluoric acid in water, provided that the barrier removal procedure does not excessively attack either copper line and post features 1285 and 1307 or the dielectric 1210 that underlies the barrier layer 1240.
- a further dielectric layer is formed to a thickness sufficient to cover the upper surfaces of the posts of the interconnect structure.
- the further dielectric layer is preferably formed by spin application or spray application of a precursor material or precursor materials followed by a cure, in either an anaerobic or in an oxygen-containing atmosphere, at a temperature of less than 450C.
- Composition of the dielectric layer may be different than or the same as the composition of the dielectric layer 1210.
- the upper surface of the layer is etched back to expose upper contact regions of the post structure 1307.
- a blanket plasma etch may be employed to reduce the thickness of layer until all upper surfaces of the post structures 1307 are exposed.
- Etching of BCB for example, may be done in a plasma that contains oxygen and fluorine ions.
- a hard mask for patterning the posts as well as the interconnect lines.
- One embodiment of a process that utilizes a hard mask for patterning the post structures is illustrated in Fig. 15.
- the corresponding wafer movements between the tool sets are illustrated in Fig. 16.
- SUBSTfTUTE SHEET (RULE 26)
- the processing of the workpiece is substantially similar to the processing illustrated in Fig. 11.
- the principal difference occurs after electrochemical deposition step 1280.
- the workpiece is removed from the wet processing tool set 1030 and returned to the hard mask formation tool set 1023 wherein a further hard mask dielectric layer 1422 (Fig. 17) is disposed over the surface of the workpiece as illustrated at step 1427 of Fig. 15.
- the workpiece is transferred to the pattern forming tool set 1025 where, for example, a further photoresist layer 1432 is disposed over the further hard mask dielectric layer 1422 and patterned, as step 1429, in accordance with the desired post metallization pattern.
- the hard mask dielectric layer 1422 is then etched in accordance with this pattern at step 1443 to form the openings in which the post structures will be formed.
- the workpiece is then returned to the wet chemical processing tool set 1030 where the photoresist layer 1432 is stripped at step 1310 and the copper post structures are electrochemically deposited through the hard mask dielectric layer 1422 at step 1309.
- the entire metallization level can be formed with nine wafer movements between the illustrated tool sets.
- FIG. 19 and 20 Further enhancements to each of the foregoing processes and tool sets/wafer movements are illustrated in Figs. 19 and 20.
- the tool configurations of Figs. 19 and 20 each include an inspection tool set 600 that is used to check the workpieces at intermediate stages of the application of a single metallization level. The intermediate checks are used, for example, to insure proper registration of the various photoresist and/or hard mask patterns and corresponding metallization and, further, to insure proper dielectric etch-back.
- each workpiece may be provided to the inspection tool set 1600 after processing steps 1270, 1280, 1308, 1380 and 1425 that are illustrated in Fig. 11.
- Fig. 19 each workpiece may be provided to the inspection tool set 1600 after processing steps 1270, 1280, 1308, 1380 and 1425 that are illustrated in Fig. 11.
- Fig. 19 each workpiece may be provided to the inspection tool set 1600 after processing steps 1270, 1280, 1308, 1380 and 1425 that are illustrated in Fig. 11.
- each workpiece may be provided to the inspection tool set 1600 after processing steps 1270, 1280, 1429, 1380 and 1425 that are illustrated in Fig. 16.
- twelve workpiece movements are used to transfer the workpiece between the various tools of the tool processing architecture to form a single interconnect metallization level.
- fourteen workpiece movements are used to transfer the workpiece between the various tools of the tool processing architecture to form a single interconnect metallization level.
- the inspection tool set 600 may be implemented, for example, with inspection devices available from KLA-Tencor.
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Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US76565 | 1998-05-12 | ||
US76695 | 1998-05-12 | ||
US09/076,565 US6376374B1 (en) | 1998-05-12 | 1998-05-12 | Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece |
US09/076,695 US6143126A (en) | 1998-05-12 | 1998-05-12 | Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on an integrated circuit |
US128238 | 1998-08-03 | ||
US09/128,238 US6120641A (en) | 1998-05-12 | 1998-08-03 | Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece |
PCT/US1999/010331 WO1999059190A2 (en) | 1998-05-12 | 1999-05-12 | Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece |
Publications (1)
Publication Number | Publication Date |
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EP1086485A2 true EP1086485A2 (en) | 2001-03-28 |
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Application Number | Title | Priority Date | Filing Date |
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EP99922934A Withdrawn EP1086485A2 (en) | 1998-05-12 | 1999-05-12 | Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece |
Country Status (4)
Country | Link |
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EP (1) | EP1086485A2 (zh) |
JP (1) | JP2002515645A (zh) |
TW (1) | TW494443B (zh) |
WO (1) | WO1999059190A2 (zh) |
Families Citing this family (8)
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US8960099B2 (en) | 2002-07-22 | 2015-02-24 | Brooks Automation, Inc | Substrate processing apparatus |
TWI304391B (en) | 2002-07-22 | 2008-12-21 | Brooks Automation Inc | Substrate processing apparatus |
US7988398B2 (en) | 2002-07-22 | 2011-08-02 | Brooks Automation, Inc. | Linear substrate transport apparatus |
US7959395B2 (en) | 2002-07-22 | 2011-06-14 | Brooks Automation, Inc. | Substrate processing apparatus |
JP2011154380A (ja) * | 2003-03-20 | 2011-08-11 | Toshiba Mobile Display Co Ltd | 表示装置の形成方法 |
US7215006B2 (en) * | 2005-10-07 | 2007-05-08 | International Business Machines Corporation | Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
US20070117377A1 (en) * | 2005-11-23 | 2007-05-24 | Chih-Chao Yang | Conductor-dielectric structure and method for fabricating |
US8496790B2 (en) * | 2011-05-18 | 2013-07-30 | Applied Materials, Inc. | Electrochemical processor |
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US5178682A (en) * | 1988-06-21 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method for forming a thin layer on a semiconductor substrate and apparatus therefor |
US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
US5256565A (en) * | 1989-05-08 | 1993-10-26 | The United States Of America As Represented By The United States Department Of Energy | Electrochemical planarization |
JPH0812846B2 (ja) * | 1991-02-15 | 1996-02-07 | 株式会社半導体プロセス研究所 | 半導体製造装置 |
US5563095A (en) * | 1994-12-01 | 1996-10-08 | Frey; Jeffrey | Method for manufacturing semiconductor devices |
US5994678A (en) * | 1997-02-12 | 1999-11-30 | Applied Materials, Inc. | Apparatus for ceramic pedestal and metal shaft assembly |
US5933758A (en) * | 1997-05-12 | 1999-08-03 | Motorola, Inc. | Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer |
-
1999
- 1999-05-12 EP EP99922934A patent/EP1086485A2/en not_active Withdrawn
- 1999-05-12 JP JP2000548908A patent/JP2002515645A/ja active Pending
- 1999-05-12 TW TW088107682A patent/TW494443B/zh not_active IP Right Cessation
- 1999-05-12 WO PCT/US1999/010331 patent/WO1999059190A2/en active Search and Examination
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JP2002515645A (ja) | 2002-05-28 |
WO1999059190A3 (en) | 2000-04-06 |
TW494443B (en) | 2002-07-11 |
WO1999059190A2 (en) | 1999-11-18 |
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