EP1072057A1 - Method of manufacturing a vertical metal connection in an integrated circuit - Google Patents

Method of manufacturing a vertical metal connection in an integrated circuit

Info

Publication number
EP1072057A1
EP1072057A1 EP00910640A EP00910640A EP1072057A1 EP 1072057 A1 EP1072057 A1 EP 1072057A1 EP 00910640 A EP00910640 A EP 00910640A EP 00910640 A EP00910640 A EP 00910640A EP 1072057 A1 EP1072057 A1 EP 1072057A1
Authority
EP
European Patent Office
Prior art keywords
layer
cavity
copper
dielectric material
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00910640A
Other languages
German (de)
French (fr)
Other versions
EP1072057B1 (en
Inventor
Benoit Froment
Phillipe Gayet
Erik Van Der Vegt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
NXP BV
Original Assignee
STMicroelectronics SA
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA, Koninklijke Philips Electronics NV filed Critical STMicroelectronics SA
Publication of EP1072057A1 publication Critical patent/EP1072057A1/en
Application granted granted Critical
Publication of EP1072057B1 publication Critical patent/EP1072057B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper

Definitions

  • the invention relates to the manufacture of integrated circuits, more particularly the making of vertical metal connections (commonly referred to as “vias” by those skilled in the art) using a “damascene” type process, as it is called by those skilled in the art.
  • a damascene process may be carried out in a number of alternative ways, such as, in particular, the variant referred to as “single damascene”, or the variant referred to as “autoaligned dual damascene”, or the variant referred to as "inverse dual damascene”.
  • the via is formed by making a cavity in the dielectric material deposited between two metallization levels of the integrated circuit, whereafter the cavity is filled with a metal.
  • the cavities of the vias to be formed and the cavities of the future tracks of the upper metallization level are simultaneously etched. Next, all these cavities will be filled with a filling metal to form the vias and the tracks of the upper metallization level.
  • the inter-level dielectric material that is, the dielectric material situated between two adjacent metallization levels
  • the inter-track dielectric material situated at the metallization level n+1 that is, the dielectric material situated at the level n+1 between the tracks of this level
  • a stop layer which is typically made of silicon nitride.
  • the variant referred to as “inverse dual damascene” differs from the “autoaligned dual damascene” variant in that in the former variant it is possible to omit the silicon nitride layer between the inter-level dielectric material and the inter-track dielectric material.
  • the invention particularly relates to conductive materials, notably copper but also gold or alloys thereof, which diffuse or migrate into the dielectric materials and, more generally, into all materials used in microelectronics.
  • the invention applies to all types of damascene processes, more particularly to the variants mentioned hereinabove.
  • This object is achieved, in accordance with the invention, by a method of manufacturing a vertical metal connection which is supported by a portion of a metallization level of an integrated circuit.
  • Said portion being made of a conductive material (for example copper) and covered with an encapsulation layer, (e.g. of silicon nitride), said method includes, in accordance with a general characteristic of the invention, the deposition on said conductive portion thus covered of at least a layer of a dielectric material (typically ethyl tetraorthosilicate), whereafter the layer of dielectric material is etched so as to form a cavity at the location of the future vertical connection.
  • a dielectric material typically ethyl tetraorthosilicate
  • the method further includes the deposition of at least one protective layer in said cavity to preclude diffusion of the conductive material, whereafter the protective layer at the bottom of the cavity is anisotropically etched, and the encapsulation layer is also etched, after which the cavity is filled with a conductive filler material, such as copper, aluminium, tungsten.
  • a conductive filler material such as copper, aluminium, tungsten.
  • a single protective layer is used when a "single damascene" or “autoaligned dual damascene” type process is carried out.
  • the process in accordance with the invention advantageously includes, after the protective layer and the encapsulation layer at the bottom of the cavity have been etched, the deposition of a second protective layer at the bottom and on the walls of the cavity.
  • the protective layer is advantageously composed of a material selected particularly from the group formed by tantalum, tantalum nitride, titanium and titanium nitride.
  • the contaminating elements of copper resulting from etching the encapsulation layer, are situated on the right side of the protective layer, i.e. they do not contact the dielectric material.
  • the method in accordance with the invention protects the oxide from contamination by copper and enables a cleaning step using chemical agents to eliminate the contaminating copper particles to be omitted. Furthermore, the absence of the barrier layer at the bottom of the via enables a sizeable reduction of the resistance of the via when a single protective layer is deposited.
  • Figs, la through Id illustrate a method of carrying out the process in accordance with the invention, which can be used more particularly for an "autoaligned dual damascene" process
  • Figs. 2a through 2e illustrate another method of carrying out the process in accordance with the invention, which is applicable, more particularly, to an "inverse dual damascene" type of process
  • Figs. 3a through 3d illustrate another variant of the process in accordance with the invention, which is applicable, more particularly, to a process of the "single damascene" type.
  • An encapsulation layer typically of silicon nitride SiN, having a thickness of, for example, 40 nm is deposited on a metallization level (for example the metal level n) formed by copper tracks separated from each other by a dielectric material.
  • a metallization level for example the metal level n
  • an inter- level dielectric material is deposited, for example of ethyl tetraorthosilicate (Si(OC 2 H 5 ) 4 ; TEOS in English).
  • the inter-level dielectric layer typically has a thickness of 800 nm.
  • a 120 nm thick stop layer typically of silicon nitride SiN, is deposited on this layer of dielectric material.
  • the stop layer is locally etched using a specific mask to define the location of the vias to be formed.
  • another layer of a dielectric material for example also ethyl tetraorthosilicate, is deposited, said layer forming the inter-track dielectric material, i.e. it separates the metal tracks of the metallization level n+1 from each other.
  • the second layer of dielectric material is locally etched down to the silicon nitride stop layer in such a manner that cavities are formed which extend only in said second layer of dielectric material at the location of certain tracks to be formed at the metallization level n+1.
  • the etching process does not only include the second dielectric layer but also the first dielectric layer so as to form a cavity whose upper part is used, after it has been filled, to form a metal track at the metallization level n+1, and whose lower part (autoaligned with the upper part) serves, after metallization, to form a via, resulting in the formation of the metal connection between a track at the level n and the track at the level n+1.
  • the encapsulation layer is used, on the one hand, to avoid inter-level contamination of the dielectric material by the copper of the level n and, on the other hand, as a stop layer for etching the cavity.
  • FIG. la shows a part of the integrated circuit after the dielectric layers have been etched.
  • reference numeral 1 refers to a portion of the copper track at the metal level n, covered with the encapsulation layer 2.
  • This Fig. la also shows the stack formed by the first inter-level dielectric material 3, the stop layer of silicon nitride 4 and the second layer of dielectric material 5, which is an inter-track layer. Etching of the stop layer 4 has locally led to two portions 40 and 41, and the subsequent etching of the dielectric materials has led to the cavity 6 having an upper part 60 which is larger (or longer) than the lower part 61.
  • a protective layer 7 consisting of a material which forms a barrier with respect to the diffusion of copper particles (Fig. lb) is subsequently deposited on the structure obtained in Fig. la.
  • said layer 7 may be a layer of titanium nitride TiN having a thickness of several tens of nanometers, for example 25 nm.
  • etching treatment is, for example, a plasma-etching treatment using chlorinated or fluoridated ions diluted in argon.
  • etching treatment is, for example, a plasma-etching treatment using chlorinated or fluoridated ions diluted in argon.
  • the silicon nitride encapsulation layer 2 is subjected to an etching treatment.
  • etching treatment which is also carried out in a standard way by means of plasma etching on the basis of fluoridated ions diluted in argon, copper is locally pulverized, causing copper particles Cu to be deposited on a part of the vertical walls of the lower part 61 of the cavity 6.
  • the thickness of the pulverized copper Cu layer has been exaggerated in Fig. lc for clarity. These copper particles do not diffuse into the dielectric material 3 because of the presence of the protective layer 7.
  • the cavity 6 is filled with copper by means of electrodeposition. It would alternatively be possible to employ chemical deposition in the vapor phase (CVD) in which case it would be unnecessary to pulverize a fine copper layer on the side walls of the cavity prior to filling said cavity.
  • CVD chemical deposition in the vapor phase
  • Figs. 2a through 2e show a method of carrying out the process when it is applied to an inverse dual damascene process.
  • elements having the same structures and/or functions as those shown in Figs. 1 through Id bear the same reference numerals as those used in the Figs, la through Id. For the sake of simplification, only the differences between these two series of Figures are described hereinbelow.
  • the "inverse dual damascene” process differs from the “autoaligned dual damascene” process in that a nitride silicon stop layer 4 between the inter-level dielectric material and the inter-track dielectric material can be omitted. This has the advantage that the inter-level capacitance is reduced.
  • Figs. 3a through 3d show, in a simplified manner, an embodiment of the invention which is compatible with a "simple damascene" process. Also in this case, elements which are analogous to those shown in Figs, la through Id, or fulfill an analogous function, bear the same reference numerals as the reference numerals used in these Figures.
  • the via is obtained by etching the inter-level dielectric 3.
  • the protective layer 7 is deposited which is subsequently anisotropically etched at the bottom of the cavity 6.
  • etching of the encapsulation layer 2 causes copper particles to be pulverized at this location which, by virtue of the presence of the layer 7, do not diffuse into the dielectric material.
  • the via 81 is subsequently made by filling with copper, followed by mechano-chemical polishing.
  • the level n+1 could then be formed, for example, by means of a single damascene process or a customary process other than a "damascene"-type process.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

At least one layer of a dielectric material (3) is deposited on a copper track (1) covered with an encapsulation layer (2). A cavity (6) is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer (7) is deposited in said cavity to preclude diffusion of copper. The protective layer (7) at the bottom of the cavity (6) is subjected to an anisotropic etching treatment and also the encapsulation layer (2) is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching of the encapsulation layer do not contaminate the dielectric material.

Description

Method of manufacturing a vertical metal connection in an integrated circuit.
The invention relates to the manufacture of integrated circuits, more particularly the making of vertical metal connections (commonly referred to as "vias" by those skilled in the art) using a "damascene" type process, as it is called by those skilled in the art. A damascene process may be carried out in a number of alternative ways, such as, in particular, the variant referred to as "single damascene", or the variant referred to as "autoaligned dual damascene", or the variant referred to as "inverse dual damascene".
In the variant referred to as "single damascene", the via is formed by making a cavity in the dielectric material deposited between two metallization levels of the integrated circuit, whereafter the cavity is filled with a metal.
In the variant referred to as "autoaligned dual damascene", the cavities of the vias to be formed and the cavities of the future tracks of the upper metallization level are simultaneously etched. Next, all these cavities will be filled with a filling metal to form the vias and the tracks of the upper metallization level. In this variant, the inter-level dielectric material (that is, the dielectric material situated between two adjacent metallization levels) and the inter-track dielectric material situated at the metallization level n+1 (that is, the dielectric material situated at the level n+1 between the tracks of this level) are separated by a stop layer, which is typically made of silicon nitride.
The variant referred to as "inverse dual damascene" differs from the "autoaligned dual damascene" variant in that in the former variant it is possible to omit the silicon nitride layer between the inter-level dielectric material and the inter-track dielectric material.
It proved to be very interesting to use copper for the metal tracks of one metallization level because copper has a better conductivity than, for example, aluminum. Meanwhile, the use of such a material is very tricky because there is a risk of diffusion of copper atoms into the dielectric materials, which might cause leakage currents between vias or between metal tracks. In addition, the copper may diffuse to the transistors and have an adverse effect on the functioning thereof. The invention particularly relates to conductive materials, notably copper but also gold or alloys thereof, which diffuse or migrate into the dielectric materials and, more generally, into all materials used in microelectronics.
It is an object of the invention, in particular, to provide integrated circuits having metallization levels of copper, using a damascene-type process to make the vias of the integrated circuit, while precluding the diffusion of copper particles into the dielectric materials.
The invention applies to all types of damascene processes, more particularly to the variants mentioned hereinabove. This object is achieved, in accordance with the invention, by a method of manufacturing a vertical metal connection which is supported by a portion of a metallization level of an integrated circuit.
Said portion being made of a conductive material (for example copper) and covered with an encapsulation layer, (e.g. of silicon nitride), said method includes, in accordance with a general characteristic of the invention, the deposition on said conductive portion thus covered of at least a layer of a dielectric material (typically ethyl tetraorthosilicate), whereafter the layer of dielectric material is etched so as to form a cavity at the location of the future vertical connection. The method further includes the deposition of at least one protective layer in said cavity to preclude diffusion of the conductive material, whereafter the protective layer at the bottom of the cavity is anisotropically etched, and the encapsulation layer is also etched, after which the cavity is filled with a conductive filler material, such as copper, aluminium, tungsten.
In practice, a single protective layer is used when a "single damascene" or "autoaligned dual damascene" type process is carried out. On the other hand, when in accordance with the invention, an "inverse dual damascene" type process is used, the process in accordance with the invention advantageously includes, after the protective layer and the encapsulation layer at the bottom of the cavity have been etched, the deposition of a second protective layer at the bottom and on the walls of the cavity. This enables direct contact between the copper (for example) and the dielectric material to be avoided at the level of the intermediate, horizontal plane of the cavity. Therefore, the possibility of depositing a second protective layer can be considered in all damascene processes where there is a risk of direct contact between the copper and the dielectric material. The protective layer is advantageously composed of a material selected particularly from the group formed by tantalum, tantalum nitride, titanium and titanium nitride.
Thus, in accordance with the invention, the contaminating elements of copper, resulting from etching the encapsulation layer, are situated on the right side of the protective layer, i.e. they do not contact the dielectric material.
Thus, the method in accordance with the invention protects the oxide from contamination by copper and enables a cleaning step using chemical agents to eliminate the contaminating copper particles to be omitted. Furthermore, the absence of the barrier layer at the bottom of the via enables a sizeable reduction of the resistance of the via when a single protective layer is deposited.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter by way of non-limitative example.
In the drawings:
Figs, la through Id illustrate a method of carrying out the process in accordance with the invention, which can be used more particularly for an "autoaligned dual damascene" process, Figs. 2a through 2e illustrate another method of carrying out the process in accordance with the invention, which is applicable, more particularly, to an "inverse dual damascene" type of process; and
Figs. 3a through 3d illustrate another variant of the process in accordance with the invention, which is applicable, more particularly, to a process of the "single damascene" type.
Before giving a more detailed description of the method of carrying out the process shown in the Figs, la through Id, the preliminary steps of the "autoaligned dual damascene" process which have led to the structure shown in Fig. la are briefly described.
An encapsulation layer, typically of silicon nitride SiN, having a thickness of, for example, 40 nm is deposited on a metallization level (for example the metal level n) formed by copper tracks separated from each other by a dielectric material. Next, an inter- level dielectric material is deposited, for example of ethyl tetraorthosilicate (Si(OC2H5)4; TEOS in English). The inter-level dielectric layer typically has a thickness of 800 nm. Subsequently, a 120 nm thick stop layer, typically of silicon nitride SiN, is deposited on this layer of dielectric material. Next, the stop layer is locally etched using a specific mask to define the location of the vias to be formed. In the next stage, another layer of a dielectric material, for example also ethyl tetraorthosilicate, is deposited, said layer forming the inter-track dielectric material, i.e. it separates the metal tracks of the metallization level n+1 from each other.
To be more precise, by means of another specific mask, the second layer of dielectric material is locally etched down to the silicon nitride stop layer in such a manner that cavities are formed which extend only in said second layer of dielectric material at the location of certain tracks to be formed at the metallization level n+1. Moreover, in the regions which are free of stop layers, the etching process does not only include the second dielectric layer but also the first dielectric layer so as to form a cavity whose upper part is used, after it has been filled, to form a metal track at the metallization level n+1, and whose lower part (autoaligned with the upper part) serves, after metallization, to form a via, resulting in the formation of the metal connection between a track at the level n and the track at the level n+1. The encapsulation layer is used, on the one hand, to avoid inter-level contamination of the dielectric material by the copper of the level n and, on the other hand, as a stop layer for etching the cavity. Fig. la shows a part of the integrated circuit after the dielectric layers have been etched. To be more precise, in Fig. la, reference numeral 1 refers to a portion of the copper track at the metal level n, covered with the encapsulation layer 2. This Fig. la also shows the stack formed by the first inter-level dielectric material 3, the stop layer of silicon nitride 4 and the second layer of dielectric material 5, which is an inter-track layer. Etching of the stop layer 4 has locally led to two portions 40 and 41, and the subsequent etching of the dielectric materials has led to the cavity 6 having an upper part 60 which is larger (or longer) than the lower part 61.
In accordance with the invention, a protective layer 7 consisting of a material which forms a barrier with respect to the diffusion of copper particles (Fig. lb) is subsequently deposited on the structure obtained in Fig. la. To be more precise, said layer 7 may be a layer of titanium nitride TiN having a thickness of several tens of nanometers, for example 25 nm.
Subsequently, (Fig. lc) said protective layer is subjected to a first anisotropic etching treatment. This etching treatment is, for example, a plasma-etching treatment using chlorinated or fluoridated ions diluted in argon. As a result of this anisotropic etching operation, the titanium nitride remains on the vertical walls of the cavity 6.
Next, the silicon nitride encapsulation layer 2 is subjected to an etching treatment. During this etching process, which is also carried out in a standard way by means of plasma etching on the basis of fluoridated ions diluted in argon, copper is locally pulverized, causing copper particles Cu to be deposited on a part of the vertical walls of the lower part 61 of the cavity 6. The thickness of the pulverized copper Cu layer has been exaggerated in Fig. lc for clarity. These copper particles do not diffuse into the dielectric material 3 because of the presence of the protective layer 7. After providing a fine copper layer in a thickness of typically 130 nm by means of spray coating, which layer is not shown in the Figures for the sake of simplification, the cavity 6 is filled with copper by means of electrodeposition. It would alternatively be possible to employ chemical deposition in the vapor phase (CVD) in which case it would be unnecessary to pulverize a fine copper layer on the side walls of the cavity prior to filling said cavity. This finally results, as shown in Fig. Id after mechano-chemical polishing, in a copper part 8 comprising the portion 80 of the metal track of level n+1 and of the via 81 interconnecting this portion 80 and the portion 1.
In the example described hereinabove use is made of titanium or titanium nitride for the protecting layer 7, however, it would also be possible to use tantalum or tantalum nitride. In that case, an anisotropic plasma-etching treatment would be employed the characteristics of which are the same as for the etching of titanium or titanium nitride.
Figs. 2a through 2e show a method of carrying out the process when it is applied to an inverse dual damascene process. In these Figures, elements having the same structures and/or functions as those shown in Figs. 1 through Id bear the same reference numerals as those used in the Figs, la through Id. For the sake of simplification, only the differences between these two series of Figures are described hereinbelow.
The "inverse dual damascene" process differs from the "autoaligned dual damascene" process in that a nitride silicon stop layer 4 between the inter-level dielectric material and the inter-track dielectric material can be omitted. This has the advantage that the inter-level capacitance is reduced.
After the deposition of the protective layer 7 (Fig. 2b), and the subsequent anisotropic etching thereof as well as the etching of the encapsulation layer 2, the configuration shown in Fig. 2c is obtained. It is to be noted that as a result of anisotropically etching the protecting layer 7, the step 610 of the cavity 6 is exposed. Therefore, it is necessary, before filling the cavity with copper, to deposit a second protective layer 9 which may consist of the same material as that used for the first layer 7 (Fig. 2d). This second protective layer enables the dielectric material situated at the level of the step 610 to be protected before filling the cavity 6 with copper. This precaution would not be necessary in the "autoaligned dual damascene" process because the presence of the portion 41 of the SiN stop layer forming a barrier would avoid contamination of the dielectric material by the copper during filling the cavity 6.
Figs. 3a through 3d show, in a simplified manner, an embodiment of the invention which is compatible with a "simple damascene" process. Also in this case, elements which are analogous to those shown in Figs, la through Id, or fulfill an analogous function, bear the same reference numerals as the reference numerals used in these Figures. In the "simple damascene" process, the via is obtained by etching the inter-level dielectric 3. Next, the protective layer 7 is deposited which is subsequently anisotropically etched at the bottom of the cavity 6. Next, etching of the encapsulation layer 2 causes copper particles to be pulverized at this location which, by virtue of the presence of the layer 7, do not diffuse into the dielectric material. The via 81 is subsequently made by filling with copper, followed by mechano-chemical polishing. The level n+1 could then be formed, for example, by means of a single damascene process or a customary process other than a "damascene"-type process.

Claims

CLAIMS:
1. A method of manufacturing a vertical metal connection supported by a portion of a metallization level of an integrated circuit, characterized in that said portion (1) is made of a conductive material and covered with an encapsulation layer (2), which method includes the deposition, on said copper portion (1) which is covered as described hereinabove, of at least one layer of a dielectric material (3), whereafter the layer of dielectric material is etched so as to form a cavity (6) at the location of the future vertical connection, after which at least one protective layer precluding diffusion of the conductive material (7) is deposited in said cavity, whereafter the protective layer (7) at the bottom of the cavity (6) is anisotropically etched, and the encapsulation layer (2) is also etched, after which the cavity is filled with a conductive filler material.
2. A method as claimed in claim 1, characterized in that the protective layer (7) is composed of a material selected from the group formed by tantalum, tantalum nitride, titanium and titanium nitride.
3. A method as claimed in claim 1 or 2, characterized in that after etching the protective layer and the encapsulation layer at the bottom of the cavity, a second protective layer (9) is deposited at the bottom and on the walls of the cavity (6).
EP00910640A 1999-02-12 2000-02-04 Method of manufacturing a vertical metal connection in an integrated circuit Expired - Lifetime EP1072057B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9901741A FR2789803B1 (en) 1999-02-12 1999-02-12 METHOD OF MAKING A VERTICAL METAL CONNECTION IN AN INTEGRATED CIRCUIT
FR9901741 1999-02-12
PCT/EP2000/000884 WO2000048246A1 (en) 1999-02-12 2000-02-04 Method of manufacturing a vertical metal connection in an integrated circuit

Publications (2)

Publication Number Publication Date
EP1072057A1 true EP1072057A1 (en) 2001-01-31
EP1072057B1 EP1072057B1 (en) 2011-01-12

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US (1) US6627093B1 (en)
EP (1) EP1072057B1 (en)
JP (1) JP2002536846A (en)
DE (1) DE60045501D1 (en)
FR (1) FR2789803B1 (en)
WO (1) WO2000048246A1 (en)

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US6627093B1 (en) 2003-09-30
FR2789803A1 (en) 2000-08-18
EP1072057B1 (en) 2011-01-12

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