EP1071128A2 - Procédé d'identification en temps réel de sources de défauts sur des substrats semiconducteurs - Google Patents

Procédé d'identification en temps réel de sources de défauts sur des substrats semiconducteurs Download PDF

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Publication number
EP1071128A2
EP1071128A2 EP00306142A EP00306142A EP1071128A2 EP 1071128 A2 EP1071128 A2 EP 1071128A2 EP 00306142 A EP00306142 A EP 00306142A EP 00306142 A EP00306142 A EP 00306142A EP 1071128 A2 EP1071128 A2 EP 1071128A2
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EP
European Patent Office
Prior art keywords
defect
tool
wafer
defects
identifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00306142A
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German (de)
English (en)
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EP1071128A3 (fr
Inventor
Sasson Somekh
Amotz Maimon
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Applied Materials Inc
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Applied Materials Inc
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Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of EP1071128A2 publication Critical patent/EP1071128A2/fr
Publication of EP1071128A3 publication Critical patent/EP1071128A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
    • G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/50—Machine tool, machine tool null till machine tool work handling
    • G05B2219/50064—Camera inspects workpiece for errors, correction of workpiece at desired position
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/80—Management or planning

Definitions

  • the present invention relates to a method and apparatus for identifying the causes of defects on the surface of a semiconductor substrate.
  • the invention has particular applicability for in-line inspection of semiconductor wafers during manufacture of high-density semiconductor devices with submicron design features.
  • a number of the wafers in a cassette are inspected, typically at a stand-alone inspection tool, per instructions from the MES.
  • the inspection tool the surface of the wafer to be inspected is scanned by a high-speed inspection device; for example, an opto-electric converter such as a CCD (charge-coupled device) or a laser.
  • the inspection tool then informs the MES that it has completed its inspection.
  • Statistical methods are thereafter employed by the inspection tool to produce a defect map showing suspected locations on the wafer having a high probability of a defect.
  • a review of the potential defect sites is then conducted using the defect map, either at the inspection tool or at a separate stand-alone review station, typically by comparing images of suspected defect sites with reference images to positively determine the presence of a defect, and then analyzing the images to determine the nature of the defect (e.g., a defective pattern, a particle, or a scratch) and its cause.
  • process data from the MES, and inspection and review results from the inspection tools and review stations are periodically downloaded to another stand-alone computer software-implemented system called a “yield management system” (YMS), which employs statistical process control methods to monitor process quality. If the YMS determines that the process is performing outside predetermined control limits, it generates data, such as a list of tools visited by wafers exhibiting defects and the process parameters used at those tools, which are helpful in diagnosing processing problems. The user may then analyze this data to isolate the causes of the defects.
  • YMS yield management system
  • the YMS generates and reports its findings "off-line”; i.e., physically remote from the wafer processing tools and inspection tools, and remote in time from when the processing took place.
  • communication between the MES and the YMS occurs only once or twice a day and, therefore, data from the YMS reaches the user many hours after the wafer has visited the process and inspection tools.
  • the user does not receive YMS data in "real time”; i.e., at the time of wafer inspection when the user discovers that defects are occurring, the user does not have the benefit of this extremely valuable information when it is most needed; i.e., when making on-the-spot process adjustments or fault diagnoses.
  • An advantage of the present invention is the ability to automatically retrieve information relating to the tools visited by a semiconductor wafer at a wafer inspection tool at the time of inspection of the wafer, thereby enabling efficient identification of process problem areas.
  • a method of inspecting a semiconductor wafer comprises subjecting the wafer to a plurality of processing steps using a plurality of processing tools, each of the processing tools respectively associated with a different tool identifier and set of process parameters, and storing the tool identifiers and the set of process parameters.
  • the wafer is then inspected for defects with an inspection tool and a list of the tool identifiers generated, using the inspection tool.
  • the user of the present invention can then request a display of the set of process parameters associated with one of the listed tool identifiers.
  • Another aspect of the present invention is an apparatus for carrying out the steps of the above method.
  • a further aspect of the present invention is a computer-readable medium bearing instructions for inspecting a semiconductor wafer, which wafer has been subjected to a plurality of processing steps using a plurality of processing tools, each of the processing tools respectively associated with a different tool identifier, the instructions, when executed, being arranged to cause one or more processors to perform the steps of receiving the tool identifiers; inspecting the wafer for defects; and generating a list of the tool identifiers.
  • a semiconductor wafer is processed on a plurality of different processing tools, and a unique tool identifier is stored along with a set of process parameters for each tool, as by an MES.
  • the wafer is inspected using an inspection tool, such as the WF7xx SeriesTM Wafer Inspection System available from Applied Materials of Santa Clara, CA., and a list of the tool identifiers is generated from data retrieved from the MES, along with a defect map, and displayed at the inspection tool.
  • the user may then request that the set of process parameters, including tool parameters (e.g., preventive maintenance conditions), for any of the tools identified on the list be retrieved from the MES and displayed at the inspection tool.
  • tool parameters e.g., preventive maintenance conditions
  • the user is automatically provided with a list of the tools visited by the wafer and has easy access to the process parameters used at each of those tools.
  • This information along with the defect map (and other data gathered from defect review procedures, if performed), facilitates tracing the causes of defects to their source, such as to a particular process step or to a particular piece of processing equipment.
  • the process of tracing the causes of defects to their source is further automated. Suspected defect sites are reviewed, identified and classified, either at the inspection tool or at a stand-alone review machine. Then the classes of defects are correlated with the parameters of particular tools on the list of tools visited by the wafer. An alarm is generated if a total number of defects in a specific one of the defect classes is about equal to or greater than a predetermined number for the specific defect class, and the tool identifier associated with the specific one of the defect classes is displayed at the inspection tool, thereby pointing out a faulty tool that is a probable cause of the defects.
  • FIG. 1-4 An embodiment of the present invention is illustrated in Fig. 1-4.
  • the present invention is implemented at an inspection tool 300, as shown in Fig. 3, comprising an imager 310 for imaging the surface of a wafer at high speed, typically using a photo multiplier (PMT) or CCD and an illumination source such as a lamp or a laser.
  • Inspection tool 300 further comprises a processor 320, which preferably performs the analysis disclosed herein electronically, and a monitor 330 for displaying results of the analyses of processor 320.
  • Processor 320 is in communication with a conventional MES 340, a conventional YMS 380 and, in one embodiment of the invention described below, a review station 350.
  • a semiconductor wafer W is processed to have a plurality of patterned integrated circuit dies 1000.
  • wafer W is initially subjected to a processing step at a processing tool at step 200 (Fig. 2), then a tool identifier unique to the processing tool is stored in MES 340 (Fig. 3) along with a set of process parameters used at the tool (see step 205).
  • MES 340 Fig. 3
  • wafer W is brought to inspection tool 300 and imaged by imager 310 (see step 215).
  • a conventional defect map 400 is then produced at step 220 by processor 320 using statistical methods, typically involving algorithms and/or grey-scale analysis, to identify suspected locations 401 on wafer W having a high probability of having a defect.
  • a list of tool identifiers associated with tools visited by wafer W is generated by processor 320 retrieving the tool identifier data stored in MES 340 (see step 235) and the list is displayed at inspection tool 300 at monitor 330, along with defect map 400 (see step 240).
  • the list of tool identifiers can be displayed on monitor 330 as a list of tool names, such as "Etcher 5" or "Cleaning Station 2". Alternatively, the list may be displayed graphically, with icons representing different tool types.
  • the list may be generated and displayed automatically after inspection (i.e., with no intervention by the user) or only when requested by the user.
  • processor 320 determines a defect level for wafer W in a conventional manner, typically based on the number of suspected defect locations 401 and/or the density of suspected defect locations 401, and compares the defect level with a predetermined defect level that represents the highest acceptable defect level. If the defect level is lower than the predetermined defect level, processing of wafer W continues at step 230. However, if the defect level is about equal to or greater than the predetermined defect level, the list of tool identifiers associated with tools visited by wafer W is retrieved from MES 340, and processing continues at step 235.
  • the user can select one or more of the tools on the list of tool identifiers, such as by moving a cursor to the appropriate tool name or icon, and obtain a display of the set of process parameters, which can include tool parameters, retrieved at step 245 from MES 340 by processor 320 and displayed on monitor 330 at step 250.
  • the user can more readily identify a probable cause of defects at the time the defects are discovered. Additionally, this information can be fed to YMS 380 for further statistical analysis off-line.
  • defects are examined and classified, and the defect classes are correlated with the tools visited by wafer W.
  • suspected defect locations 401 are reviewed to identify actual defects, each of the defects is examined and classified, and the defect classes are correlated with the tools visited by wafer W.
  • a redetection procedure is carried out; e.g., after step 240, at each suspected defect location 401 to determine the exact location of the defects.
  • a conventional CCD imager such as imager 310, or a conventional stand-alone SEM review station 350 (employing a processor 370 and a SEM 360, such as SEMVisionTM available from Applied Materials of Santa Clara, CA), is used to image a pattern at a suspected defect location 401 and a reference pattern at a corresponding location on an adjacent or other die on the same wafer which is not suspected of having a defect (see step 500).
  • a suspected defect image is then compared to a corresponding reference pattern at step 505 by processor 320 (if the imaging is performed by imager 310) or by processor 370 (if the imaging is performed by SEM 360). If a difference is found between the suspected defective pattern and the reference pattern, the suspected defective pattern is determined to be a defect by processor 320 or processor 370 at step 510.
  • a more detailed review procedure is thereafter carried out on the individual defect sites, such as imaging with imager 310 or scanning with SEM 360 to produce a relatively high-resolution image, which is then analyzed at step 515 to determine the nature of the defect (e.g., a defective pattern, at particle, or a scratch) and to classify the defect accordingly.
  • the analysis and classification of the defects can be carried out, as by one of processors 320 and 370, using conventional pattern recognition techniques or using an automated technique as described in copending U.S. patent application Serial No. 09/111,454 (Attorney Docket No. 49959-013), filed July 8, 1998, entitled “Automatic Defect Classification With Invariant Core Classes", the entire disclosure of which is hereby incorporated by reference.
  • defects are classified, at step 500a, while the wafer is being inspected and defect map 400 is being made (e.g., after step 220).
  • This technique known as "On-The-Fly" Automatic Defect Classification, employs a modified version of inspection tool 300; for example, the WF-736 DUO wafer inspection tool available from Applied Materials of Santo Clara, CA, whose operation is based on the fact that different defect types have different optical scattering signatures, which signatures are registered at strategically positioned multiple detectors (e.g., photo multipliers) as they scan the wafer.
  • On-The-Fly Automatic Defect Classification is described in an article entitled "Enhanced Yield Potential Using 'On-the-fly' Automatic Defect Classification", by Reinhold Ott and Andy Skumanich, [publication name, date and pages], the entire disclosure of which is herein incorporation by reference. Since this technique enables the acquisition of important defect information while the inspection is being performed, defect classification is carried out without a loss in production throughput.
  • the tools on the list of tool identifiers are correlated to the defect classes by processor 320, based upon the user's experiential knowledge of the causes of particular classes of defects. For example, if wafer W visited a chemical-mechanical polishing (CMP) machine, defects classified as scratches may be correlated with the particular CMP machine wafer W visited, based on the user's past observations that CMP machines commonly cause scratch defects.
  • CMP chemical-mechanical polishing
  • Processor 320 or processor 370 preferably counts the number of defects in each class of defects (see step 525). It is determined at step 530, as by processor 320 or processor 370, whether the number of defects in one of the classes exceeds a predetermined amount reflecting the maximum allowable number of defects in that particular class, referred to as a "class alarm level". If the class alarm level is not reached, the next class is so analyzed (see step 535). If the number of defects in any one of the classes exceeds the predetermined class alarm level for that class, an alarm signal is generated, as by processor 320, and monitor 320 displays the tool identifier associated with the specific defect class, thereby indicating to the user a possibly faulty tool.
  • FIG. 6 is a block diagram that illustrates an embodiment of the invention shown in Fig. 3.
  • processor 320 includes a bus 602 or other communication mechanism for communicating information, and a central processing unit (CPU) 604 coupled with bus 602 for processing information.
  • Processor 320 also includes a main memory 606, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 602 for storing information and instructions to be executed by CPU 604.
  • Main memory 606 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by CPU 604.
  • Processor 320 further includes a read only memory (ROM) 608 or other static storage device coupled to bus 602 for storing static information and instructions for CPU 604.
  • ROM read only memory
  • a storage device 610 such as a magnetic disk or optical disk, is provided and coupled to bus 602 for storing information and instructions.
  • Processor 320 is coupled, as via bus 602, to monitor 330 (Fig. 3), such as a cathode ray tube (CRT), for displaying information to the user.
  • monitor 330 Fig. 3
  • An input device 614 is coupled to bus 602 for communicating information and command selections to CPU 604.
  • cursor control 616 is Another type of user input device, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to CPU 604 and for controlling cursor movement on monitor 330.
  • Imager 310 (Fig. 3) inputs data representative of images of a semiconductor wafer under inspection, as discussed above, to bus 602. Such data may be stored in main memory 606 and/or storage device 610, and used by CPU 604 as it executes instructions. Imager 310 may also receive instructions via bus 602 from CPU 604.
  • the invention is related to the use of processor 320 for inspecting the surface of a semiconductor wafer.
  • inspection of the surface of a semiconductor wafer is provided by processor 320 in response to CPU 604 executing one or more sequences of one or more instructions contained in main memory 606.
  • Such instructions may be read into main memory 606 from another computer-readable medium, such as storage device 610.
  • Execution of the sequences of instructions contained in main memory 606 causes CPU 604 to perform the process steps described above.
  • processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory 606.
  • hard-wired circuitry may be used in place of or in combination with software instructions to implement the invention.
  • embodiments of the invention are not limited to any specific combination of hardware circuitry and software.
  • the programming of the apparatus is readily accomplished by one of ordinary skill in the art provided with the flow charts of Fig. 2 and Fig. 5.
  • Non-volatile media include, for example, optical or magnetic disks, such as storage device 610.
  • Volatile media include dynamic memory, such as main memory 606.
  • Transmission media include coaxial cable, copper wire and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications.
  • RF radio frequency
  • IR infrared
  • Computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, or any other medium from which a computer can read.
  • Various forms of computer-readable media may be involved in carrying out one or more sequences of one or more instructions to CPU 604 for execution.
  • the instructions may initially be borne on a magnetic disk of a remote computer.
  • the remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem.
  • a modem local to processor 320 can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal.
  • An infrared detector coupled to bus 602 can receive the data carried in the infrared signal and place the data on bus 602.
  • Bus 602 carries the data to main memory 606, from which CPU 604 retrieves and executes the instructions.
  • the instructions received by main memory 606 may optionally be stored on storage device 610 either before or after execution by CPU 604.
  • the inventive semiconductor wafer inspection technique provides real-time information identifying the tools visited by wafers under inspection and the process parameters including tool parameters used at those tools, thereby facilitating investigation of the causes of defects and enabling effective corrective action to be implemented at the time the defects are discovered.
  • the present invention contributes to the maintenance of high production throughput.
  • the inventive methodology enables early identification of a faulty tool.
  • the present invention is applicable to the inspection of any semiconductor wafer, and is especially useful for in-process inspection of semiconductor wafers during manufacture of high density semiconductor devices with submicron design features.
EP00306142A 1999-07-21 2000-07-19 Procédé d'identification en temps réel de sources de défauts sur des substrats semiconducteurs Withdrawn EP1071128A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US358512 1999-07-21
US09/358,512 US6763130B1 (en) 1999-07-21 1999-07-21 Real time defect source identification

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EP1071128A2 true EP1071128A2 (fr) 2001-01-24
EP1071128A3 EP1071128A3 (fr) 2008-06-25

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EP (1) EP1071128A3 (fr)
JP (1) JP2001085491A (fr)
KR (1) KR100742425B1 (fr)
TW (1) TW484197B (fr)

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TW484197B (en) 2002-04-21
KR20010029984A (ko) 2001-04-16

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