EP0805387A1 - Dispositif de circuit intégré pour réduire la consommation d'énergie - Google Patents

Dispositif de circuit intégré pour réduire la consommation d'énergie Download PDF

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Publication number
EP0805387A1
EP0805387A1 EP97106403A EP97106403A EP0805387A1 EP 0805387 A1 EP0805387 A1 EP 0805387A1 EP 97106403 A EP97106403 A EP 97106403A EP 97106403 A EP97106403 A EP 97106403A EP 0805387 A1 EP0805387 A1 EP 0805387A1
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
control signal
functional unit
activated
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97106403A
Other languages
German (de)
English (en)
Inventor
Wolfgang Wagner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0805387A1 publication Critical patent/EP0805387A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode

Definitions

  • the invention relates to an integrated circuit arrangement for reducing the current consumption according to the preamble of claim 1.
  • Figure 2 of the present invention shows in principle the interconnection of such internal functional units.
  • 1 denotes the bus lines that lead from and / or to the central processing unit.
  • 2 shows a functional unit which contains logic, drivers, etc.
  • the output of the functional unit 2 is connected to external output lines 3 via drivers 4, of which only two are shown as examples.
  • the drivers 4 are activated by a control signal via line 5.
  • the object of the present invention is to provide an integrated circuit arrangement which reduces the current consumption of highly integrated CMOS circuits.
  • the advantage of the present invention is that only those functional units in a highly integrated module, such as a microprocessor or a microcontroller, the results of which are required on the respective output lines. All other functional units are uncoupled from the central bus at this time.
  • the release signal of the respective output drivers of the functional units can be used to decouple the functional units.
  • a simple latch can advantageously be used, which is connected between the central bus and the respective functional unit.
  • the latch can advantageously consist of a simple transfer gate.
  • the invention is based on the invention only the functional unit activated that is connected to the central processing unit at the respective time period.
  • a microprocessor has, for example, several processing units such as adding units, shifting units, etc., depending on the command, only the result of one unit is important and is processed further.
  • the logic circuit in the individual units is switched back and forth, although the result of this unit is not required.
  • CMOS circuits only the switching of the current signals is consumed. This is due to the cross current and mainly due to the reloading of the load capacities.
  • FIG. 1 This is remedied in FIG. 1 in that a latch 6 is connected in front of each functional unit. Only one functional unit 2 is shown in FIG. 1 and the internal central bus is indicated by four lines 1. A latch 6 is connected between this internal bus 1 and the logic unit 2, which is controlled by the control signal 5, which is usually used to control the output drivers 4. A separate control signal could also be censored.
  • the latch 6 can be switched to memory via the control input 5 of the latch 6 if the result is not required, so that no switching takes place within the unit 2 and therefore no current with the exception of leakage currents but are much smaller.
  • a transfer gate 7 in the intermediate storage unit is shown as an example for the lowest of the bus lines 1. This represents the simplest way of decoupling the functional unit from bus 1.
  • the aforementioned 16-bit SAB80C166 microcontroller essentially has five processing units. If a power-saving circuit according to the invention is used, the total power consumption of these units can be reduced to approx.
  • a particular advantage of this circuit according to the invention is that the user does not have to start or stop saving electricity by means of an artificial command, but that this takes place automatically. This saves electricity in all functional units and not only in the applications in which the developers activate the energy-saving modes, i.e. Functional units to be switched off specifically by software.
  • microcontrollers with integrated ROM are often sold as microcontrollers without ROM. In particular, this happens when the ROM cannot be used due to production errors. This results in a different power consumption for microcontrollers without ROM compared to microcontrollers with defective ROM. If such a microcontroller is provided with a circuit arrangement according to the invention, however, the ROM does not consume any more power due to the measures described above and there is no longer any difference in power consumption compared to the real ROM-less microcontroller.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP97106403A 1996-04-29 1997-04-17 Dispositif de circuit intégré pour réduire la consommation d'énergie Withdrawn EP0805387A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19617172 1996-04-29
DE19617172A DE19617172C2 (de) 1996-04-29 1996-04-29 Integrierte Schaltungsanordnung zur Reduzierung der Stromaufnahme

Publications (1)

Publication Number Publication Date
EP0805387A1 true EP0805387A1 (fr) 1997-11-05

Family

ID=7792822

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97106403A Withdrawn EP0805387A1 (fr) 1996-04-29 1997-04-17 Dispositif de circuit intégré pour réduire la consommation d'énergie

Country Status (3)

Country Link
US (1) US5915121A (fr)
EP (1) EP0805387A1 (fr)
DE (1) DE19617172C2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000065B2 (en) * 2002-01-02 2006-02-14 Intel Corporation Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers
US7216240B2 (en) * 2002-12-11 2007-05-08 Intel Corporation Apparatus and method for address bus power control
US7152167B2 (en) * 2002-12-11 2006-12-19 Intel Corporation Apparatus and method for data bus power control
US20040230188A1 (en) * 2003-05-12 2004-11-18 Iulian Cioanta Treatment catheters with thermally insulated regions
US7529955B2 (en) * 2005-06-30 2009-05-05 Intel Corporation Dynamic bus parking

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638858A1 (fr) * 1993-08-03 1995-02-15 Nec Corporation Appareil de traitement de données en pipeline à consommation de puissance réduite
DE4426808C1 (de) * 1994-07-28 1995-08-17 Siemens Ag Vorrichtung zur Pegelumsetzung
JPH07253881A (ja) * 1994-03-16 1995-10-03 Matsushita Electron Corp 半導体装置
JPH08307237A (ja) * 1995-05-11 1996-11-22 Oki Micro Design Miyazaki:Kk バス接続回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145354A (ja) * 1984-08-10 1986-03-05 Nec Corp マイクロプロセツサ
JPH04236682A (ja) * 1991-01-18 1992-08-25 Mitsubishi Electric Corp マイクロコンピュータシステム
JPH05217367A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 半導体記憶装置
JPH05250872A (ja) * 1992-03-09 1993-09-28 Oki Electric Ind Co Ltd ランダム・アクセス・メモリ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0638858A1 (fr) * 1993-08-03 1995-02-15 Nec Corporation Appareil de traitement de données en pipeline à consommation de puissance réduite
JPH07253881A (ja) * 1994-03-16 1995-10-03 Matsushita Electron Corp 半導体装置
DE4426808C1 (de) * 1994-07-28 1995-08-17 Siemens Ag Vorrichtung zur Pegelumsetzung
JPH08307237A (ja) * 1995-05-11 1996-11-22 Oki Micro Design Miyazaki:Kk バス接続回路

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 096, no. 002 29 February 1996 (1996-02-29) *
PATENT ABSTRACTS OF JAPAN vol. 097, no. 003 31 March 1997 (1997-03-31) *

Also Published As

Publication number Publication date
US5915121A (en) 1999-06-22
DE19617172A1 (de) 1997-11-06
DE19617172C2 (de) 1999-06-24

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