EP0717348A3 - Device and method for inserting an address into a data stream in a data processing system - Google Patents

Device and method for inserting an address into a data stream in a data processing system Download PDF

Info

Publication number
EP0717348A3
EP0717348A3 EP95119622A EP95119622A EP0717348A3 EP 0717348 A3 EP0717348 A3 EP 0717348A3 EP 95119622 A EP95119622 A EP 95119622A EP 95119622 A EP95119622 A EP 95119622A EP 0717348 A3 EP0717348 A3 EP 0717348A3
Authority
EP
European Patent Office
Prior art keywords
address
processing system
data processing
data stream
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP95119622A
Other languages
German (de)
French (fr)
Other versions
EP0717348A2 (en
Inventor
Leonid Smolansky
Shai Kowal
Avner Goren
David Galanti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0717348A2 publication Critical patent/EP0717348A2/en
Publication of EP0717348A3 publication Critical patent/EP0717348A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H04L49/9052—Buffering arrangements including multiple buffers, e.g. buffer pools with buffers of different sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
EP95119622A 1994-12-16 1995-12-13 Device and method for inserting an address into a data stream in a data processing system Ceased EP0717348A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35789894A 1994-12-16 1994-12-16
US357898 1994-12-16

Publications (2)

Publication Number Publication Date
EP0717348A2 EP0717348A2 (en) 1996-06-19
EP0717348A3 true EP0717348A3 (en) 1997-06-04

Family

ID=23407483

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95119622A Ceased EP0717348A3 (en) 1994-12-16 1995-12-13 Device and method for inserting an address into a data stream in a data processing system

Country Status (3)

Country Link
US (1) US5889948A (en)
EP (1) EP0717348A3 (en)
JP (1) JP3773574B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789150B1 (en) * 1998-02-16 2004-09-07 Infineon Technologies A.G. Integrated circuit having arbitrated switching between busses
US6313845B1 (en) * 1998-06-30 2001-11-06 3Dlabs Inc. Ltd. Method and apparatus for transporting information to a graphic accelerator card
NO993483L (en) 1999-07-15 2001-01-16 Ericsson Telefon Ab L M Method and apparatus for efficient transmission of data packets
US7680944B1 (en) * 2003-02-28 2010-03-16 Comtrol Corporation Rapid transport service in a network to peripheral device servers
US7716736B2 (en) * 2003-04-17 2010-05-11 Cybersoft, Inc. Apparatus, methods and articles of manufacture for computer virus testing
US20050188125A1 (en) * 2004-02-20 2005-08-25 Lim Ricardo T. Method and apparatus for burst mode data transfers between a CPU and a FIFO
CN114513545B (en) * 2022-04-19 2022-07-12 苏州浪潮智能科技有限公司 Request processing method, device, equipment and medium

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489504A2 (en) * 1990-11-30 1992-06-10 International Business Machines Corporation Bidirectional FIFO buffer for interfacing between two buses

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
US5113354B1 (en) * 1986-02-07 1993-11-09 System for optimizing data transmissions associated with addressable buffer devices
US4768190A (en) * 1986-04-30 1988-08-30 Og Corporation Packet switching network
US5327545A (en) * 1988-05-26 1994-07-05 International Business Machines Corporation Data processing apparatus for selectively posting write cycles using the 82385 cache controller
US5155810A (en) * 1989-01-10 1992-10-13 Bull Hn Information Systems Inc. Dual FIFO peripheral with combinatorial logic circuitry
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories
US5262997A (en) * 1991-11-25 1993-11-16 Industrial Technology Research Institute Extendable FIFO
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
WO1994018766A1 (en) * 1993-02-09 1994-08-18 Dsc Communications Corporation High-speed packet bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489504A2 (en) * 1990-11-30 1992-06-10 International Business Machines Corporation Bidirectional FIFO buffer for interfacing between two buses

Also Published As

Publication number Publication date
US5889948A (en) 1999-03-30
JPH08339290A (en) 1996-12-24
EP0717348A2 (en) 1996-06-19
JP3773574B2 (en) 2006-05-10

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