EP0688115A1 - Transmission system using at least two transmission channels between a transmitter and a receiver and a receiver for use in such a system - Google Patents

Abstract

Transmission system comprising at least two links for connecting a transmitter and a receiver. The receiver comprises receiver circuits (20 and 21) for receiving the data coming from the channels, a circuit for putting the data of the said channels back into coincidence (30), formed by: · an offset detector circuit (66, 67) between the channels channel data for providing offset information, · an offset circuit for shifting the data of at least one of said channels according to said offset information, a switching circuit (35) for connecting a user circuit to one of said channels .The shift circuit is formed: · of a first series-parallel circuit (98) to supply words of N binary elements from the received data, · of a permutation circuit (108) to supply words permuted in permuting the binary elements of words with N binary elements as a function of said offset information, a plurality of second series-parallel circuits (110) for parallelizing on M outputs each of the N outputs of the permutation circuit, by taking from me buffers the data according to the offset information.Application: microwave links.

Description

• des circuits récepteurs pour recevoir les données issues des voies,
• un circuit de remise en coïncidence des données desdites voies, formé :
  • · d'un circuit détecteur de décalage entre les données des voies pour fournir une information de décalage,
  • · d'un circuit de décalage pour décaler selon ladite information de décalage les données d'au moins une desdites voies,
• un circuit de commutation pour connecter un circuit utilisateur sur une desdites voies,

The present invention relates to a transmission system comprising at least two transmission channels for connecting a transmitter and a receiver, a system in which there is provided on the transmitter side:
means for transmitting on at least two channels data to be transmitted,
and on the receiver side:

• receiving circuits for receiving data from the channels,
• a circuit for resetting the data of said channels to coincide, formed:
  • · An offset detector circuit between the channel data to provide offset information,
  • An offset circuit for shifting according to said offset information the data of at least one of said channels,
• a switching circuit for connecting a user circuit on one of said channels,

The invention also relates to a receiver suitable for such a system.

Such systems find important applications in the field of transmission of digital data by radio-relay systems or others. In this type of system, means are provided to remedy the failures of a transmission channel. These means consist of the presence of an emergency route. The problem which then arises is the passage on this emergency route and the return to the normal route. These channel changes must take place without the user noticing anything, therefore without loss of data. We then speak of "hitless". This can only be done if the data coming from the two channels coincide binary element by binary element.

A system of this kind is described in European patent application No. 0 135 563. Although entirely satisfactory, it turned out that this system on the one hand, was not suitable, when the data coming from these channels present a deviation which exceeds a few binary elements and on the other hand, was not suitable for processing data at fast throughput.

The present invention proposes a system of the kind described in the preamble which offers the possibility of making up for large deviations: typically around ten and can operate for bit rates of the order of a few hundred binary mega-elements per second.

• · d'un premier circuit série-parallèle pour fournir des mots de N éléments binaires à partir des données reçues,
• · d'un circuit de permutation pour fournir des mots permutés en permutant les éléments binaires des mots à N éléments binaires en fonction de ladite information de décalage,
• · d'une pluralité de deuxièmes circuits série-parallèles pour paralléliser sur M sorties chacune des N sorties du circuit de permutation, en prélevant dans des mémoires tampons les données en fonction de l'information de décalage.

For this, such a system is remarkable in that the offset circuit is formed:

• · A first series-parallel circuit for supplying words of N binary elements from the data received,
• A permutation circuit for supplying permuted words by permuting the binary elements of the words with N binary elements as a function of said offset information,
• · A plurality of second series-parallel circuits for parallelizing on M outputs each of the N outputs of the permutation circuit, by taking data from buffers as a function of the offset information.

The following description, given with reference to the appended drawings, all given by way of nonlimiting example, will make it clear how the invention can be implemented.

Figure 1 shows a transmission system according to the invention.

Figure 2 shows the diagram of a coincidence circuit forming part of the system of the invention.

Figure 3 shows the detail of embodiment of the permutation circuit forming part of the system of the invention.

FIG. 4 is a time diagram for the explanation of the operation of a series-parallel circuit forming part of the system of the invention.

FIG. 5 shows the structure of a comparison circuit forming part of the system of the invention.

Figure 6 shows the diagram of a PLC circuit forming part of the system of the invention.

Figures 7 to 9 are flowcharts showing the operation of the PLC circuit of Figure 6.

The system shown in Figure 1 is formed by a transmitter assembly 1 and a receiver assembly 2. These two assemblies are connected by two transmission channels 5 and 10. For example, the transmission channel 5 is a radio channel connecting a transmitting antenna 12 attached to the transmitting assembly 1 with a receiving antenna 14 attached to the receiving assembly 2, while the channel 10 is a wire link connecting these two assemblies 1 and 2. These two channels can transmit the same information so that one can rescue the other. To receive information from these two channels, the receiver assembly 2 includes two reception circuits 20 and 21 assigned respectively to channels 5 and 10. Since channels 5 and 10 necessarily have different propagation times, it is advisable to provide a information matching circuit 30 so that by means of a switch 35, it is possible to switch to one of said channels without a user connected to an output terminal 40 noticing this change of channels .

The matching circuit 30 shown in Figure 2 has two ports 48 and 50 to connect to the output of the receiver circuit 20 and two ports 53 and 55 to connect to the output of the receiver circuit 21. The ports 48 and 53 are assigned to the data in serial form and the accesses 50 and 55 to the HHP and HHX clock signals accompanying them and giving the rhythm of these data transmitted in series. The data are applied respectively to shift circuits 66 and 67 which, under the guidance of signals EGA2-0 and DV3_4 shift the bits in order to ensure the above coincidence. This coincidence is detected by a comparison circuit 70 which supplies a result to a PLC circuit 71 so that the latter can supply the signals EGA2-0 and DV3_4. Buffer circuits 72 and 73 respectively provide the data at the rate of a clock signal HC coming from a local clock 80 controlled by one of the clock signals derived from accesses 50 and 55. This choice is obtained by a switch 85 whose inputs receive HP and HX signals derived from HHP and HHX signals. The control of this switch is the same as that of switch 35. This control is provided by a signal STCM which therefore defines the channel which is used at terminal 40.

According to the invention, the offset circuits 66 and 67 are formed by first series-parallel circuits 98 and 99 so that the data which is presented, in serial form, at the access 48 and 53 are put in parallel form. Words of eight binary elements are thus supplied at the output of these circuits 98 and 99. These words are accompanied by the associated clock signals HP and HX obtained by dividing circuits 102 and 103 which divide by eight the frequency of the signals HHP and HHX. These words are then applied to permutation circuits 108 and 109 which permute, according to a circular permutation, the binary elements constituting said words as a function of the offset information EGA2-0 produced by the automatic circuit 71. Pluralities of second circuits series-parallel shown in the form of blocks 110 and 111 in FIG. 2 put each of the eight outputs of the permutation circuits 108 and 109 in parallel. In the context of this example described, the order of paralleling is four, so that the number of outputs of blocks 110 and 111 is 32. Variable dividers 120 and 121 make it possible to further shift the information in a manner which will be explained below. The division rate, here three or four, is defined by the offset information DV3_4 developed by the circuit controller 71. It will be noted that the switch 35 switches the data in the form of thirty-two binary elements. This makes it possible to work at a frequency significantly lower than the rate of the serial data. A parallel-to-serial conversion circuit 130 can be used at the output of switch 35 if serial data is required at terminal 40.

The constitution of the permutation circuit 108 is shown in detail in FIG. 3. The structure of the circuit 109 can obviously be identical.

It is made up of a set of multiplexers MU0, MU1, ... MU7 whose inputs are connected in a manner that follows from what will be explained by means of table I below. The switching position of these multiplexers is controlled by a single signal established by a control circuit 200 which processes the signal EGA2-0. In what follows, we will use the following binary elements:
..., e₋₇, e₋₆, e₋₅, ..., e₀, e₁, e₂, e₃, ....
which are considered, at circuit 98 level, in times going from the past to the present. The binary elements at the output of these multiplexers MU7 to MU0 are given by table I below.

The circuit 108 also includes a memory element M0 to M7 for storing the binary element at the output of the multiplexers MU0 to MU7. Multiplexers MUS0 to MUS7 with two positions, also controlled by the control circuit 200, make it possible to supply the outputs of the circuits 108, either the binary element stored, ie the binary element at the output of the multiplexers MU0 to MU7. Table II below explains the word finally worked out by the permutation circuit 108. In this table we involve the binary elements e₋₁, e₋₂, ... which are successively prior to e₀.

The circuit 110 is developed from shift registers SP0 to SP7 which respectively receive the binary elements at the outputs of the multiplexers MUS0 to MUS7. These bits are shifted to the rhythm of the HP clock signals. The outputs in parallel of these registers are respectively connected to memory inputs BF0 to BF7. These memories are read at the rate of output signals from a divider 220 which divides the HP signals by four to provide an HP / 4 signal. These memories are written to the rhythm of the output signal of the variable divider 120. The memories provide words of thirty-two binary elements on groups of four outputs PA, PB, PC, PD, PE, PF, PG and PH. The groups of outputs of the equivalent memories of circuit 111 bear the references XA, XB, XC, XD, XE, XF, XG and XH.

When the division rate is equal to four the binary elements are presented in the manner indicated in table III below.

FIG. 4 shows a time diagram intended to explain the operation of the circuit 110. This time diagram relates more particularly to the register SP0 and the memory BF0. Thus, at the rate of the signal HP, the binary elements e₋₈, e₀, e₈, e₁₆, e₂₄, ... enter the shift register SP0 at the respective times t₋₁, t₀, t₁, t₂, t₃, .. Line DV / 4 gives the appearance of the write signals in memory BF0. On this time diagram, this line DV / 4 has shown two writing instants tw1 and tw2 when the division rate is four. The binary elements e₀, e₈, e₁₆, e₂₄ are then stored in the memory BF0 at the instant tw2. At time tw1, it was the binary elements e₋₃₂, e₋₂₄, e₋₁₆ and e₋₈ that were. We now consider line DV / 3 corresponding to the case where the division rate is three. We distinguish on this line the instants tw10 and tw11. The instant tw10 corresponds to the instant tw1. It is from this instant tw10 that the division rate goes to three. At time tw11, only three binary elements are recorded in the register SP0, so it is the binary elements e₋₈, e₀, e₈, e₁₆ which are finally stored in the memory BF0. Table IV below summarizes what has just been said for a division rate equal to three. We therefore notice that we obtained an offset of one byte. If we call M, the number of positions of the shift registers SP0 to SP7, and N the number of positions of the shift register 98 (and respectively 99), we can show that the resetting range is equal to: N × (M-1) binary elements, in our example 24:

The comparison circuit 70 shown in FIG. 5 consists of a first series of comparators CDA, CDB, ..., CDH which compare two by two the words of four binary elements at the outputs of PA, PB, ..., PH of circuit 110 and the corresponding outputs XA, XB, ..., XH of circuit 111. Thus the comparator CDA compares the word at the output PA with the word at the output XA. This provides logic signals on the DF0-7 outputs. A second series of comparators CAB, CAC, CAD, ..., CAH compares the word of the PA output with the words of the XB, XB, ..., XH outputs. Logical signals are then supplied on the DV1-7 outputs. These signals are used by the PLC circuit 71.

FIG. 6 shows a diagram on which this automatic circuit 71 is established.

It is formed around a state circuit 300. This circuit defines a plurality of states given in table V below. TABLE V STATES COMMENTS S0 rest S4 timeout S5 one byte offset (110) S7 switching state S8 swapping 1 eb (108) S9 permutation of 2 eb (108) S10 permutation of 3 eb (108) S11 permutation of 4 eb (108) S12 permutation of 5 eb (108) S13 permutation of 6 eb (108) S14 permutation of 7 eb (108) S15 permutation of 8 eb (108) eb: binary element
The changes of states are given in the flowcharts given in FIGS. 6, 7 and 8. The PLC circuit 71 comprises two logic circuits 302 and 304. The circuit 302 provides an SDF signal which is a logical "AND" of all the DF0 signals -7. This SDF signal, when its value is "1", indicates a coincidence of the binary elements of channel 5 with the binary elements of channel 10.
Circuit 304 provides an SDV signal which is a logical "AND" of the DV1-7 signals and the DF0 signal. The circuit also includes two counters 306 and 308 which respectively supply logic signals TC and TCN as a function of increment signals INC and INCN respectively. These counters are initialized by an LD signal. The signal TC, when it is equal to "1" means that the counter 306 is full. This counter actually counts the number of coincidences reported by the SDF signal (= "1"). The TCN signal, when it is equal to "1", means that the counter 308 is full. This counter actually counts the number of non-coincidences signaled by the SDF signal (= "0"). Thus, these counters make it possible not to take decisions too hasty at the appearance of SDF signals which do not always reflect a real situation. The SDV signal makes it possible to detect the case where the channels do not transmit useful signals and therefore to detect data signals of zero value or communication silences. The signals INC, INCN and LD therefore depend on the states of circuit 300. A circuit 310 detecting a state of circuit 300 supplies the signal DV3_4.
A logic circuit 320 supplies a signal CONF from the signal STCM and a signal COM, this external COM signal signifying that one wants to switch in an arbitrary manner on a certain channel, channel 5 or channel 10, the value CONF = 1 signifying that a lane change is requested and the value CONF = 0, that no lane change is necessary. A HOFI signal lights up an FLG indicator to indicate that a switching of channels has taken place without any coincidence between them.

It is now possible to explain the different organizational charts. To begin with, we consider box K0 in FIG. 7. This box corresponds to the idle state S0 of circuit 71. We examine in box K1 the value of signal TC. If it is zero, we go to box K3 and examine the value of the SDF signal. If this SDF signal is equal to "1", we go to box K5 where the value of the SDV signal is tested. If this is equal to "0", the INC signal is activated (box K7) so that the counter 306 increments and it remains in the S0 state. If the value of the signal SDV is equal to "1", we remain in this state S0 because we are in the phase of silence and we do not increment the counter 306.

If the TC signal tested in box K1 has the value "1", we go to box K10. Here, we examine the relation CONF = 1 which means that a change of lane is to be undertaken: if we are on lane 5, we seek to pass on lane 10 and if we is on channel 10, we are trying to go to channel 5. If we do not want to change channels, we reset the counters 306 and 308 by activating the signal LD (box K12). If you want to change, you reset these counters (box K14) and you go to the S7 state (box K16), the channel change is then made. After this channel switching, we return to the S0 state, if the TC value tested in box K18 is equal to "1". If the latter value is equal to "0", the SDF value is tested (box K20). If it is equal to "1", the counter 306, box K21, is incremented and the state S7 is returned. If this SDF value is "0", the TCN value is tested (box K22). A TCN value equal to "0" causes the counter 308, box K24, to increment and we return to state S7. If the TCN value tested in box K22 is equal to "1", the HOFI signal (box K27) is activated before returning to the S0 state. This HOFI signal shows that a switching has taken place when the data were not phased and did not coincide. This HOFI signal can trigger the illumination of an FLG indicator (figure 6).

The test indicated in box K3 can also be negative, that is to say that SDF = "0". This results in a test on the TCN value. If this value is zero, the content of counter 308 is incremented in box K28 and the box K0 is returned. If it is equal to "1", the counters 306 and 308 are then reset by activation of the signal LD (box K32). We then pass state S8 forming part of a block of boxes B10. If the tests explained in this block B10, in FIG. 8, are correct, we return to box K0. If these tests are not correct, we pass successively to states S9, ..., S14 of blocks B11, ..., B17. As soon as one is correct, we return to state S0 of box K0. If the tests of block B17 are not correct, we pass to block B20 which is associated with states S5, followed by state S4 which defines a time delay necessary for the implementation of the shifting process. The blocks B10 to B17 comprise, as shown in FIG. 8, boxes K100, K101, ... K132 which are to be compared with the boxes K0, K1, ..., K32. The block of boxes B20 represented in FIG. 9 is formed a first box K200 relating to the state S4, then we pass to the state S5, box K202. A box K203 is tested on the value of TC. If this value is zero, the counter 306 is incremented and we return to box K202. If this value is "1", we return to block B10 for a new search for coincidences.

Claims (5)

Transmission system comprising at least two transmission channels for connecting a transmitter and a receiver, system in which there is provided on the transmitter side:
means for transmitting on at least two channels data to be transmitted,
and on the receiver side: - receiver circuits to receive data from the channels, a circuit for resetting the data of said channels to coincide, formed: · An offset detector circuit between the channel data to provide offset information, An offset circuit for shifting according to said offset information the data of at least one of said channels, - a switching circuit for connecting a user circuit on one of said channels,
characterized in that the offset circuit is formed: · A first series-parallel circuit for supplying words of N binary elements from the data received, A permutation circuit for supplying permuted words by permuting the binary elements of the words with N binary elements as a function of said offset information, · A plurality of second series-parallel circuits for parallelizing on M outputs each of the N outputs of the permutation circuit, by taking data from buffers as a function of the offset information. Transmission system according to claim 1, characterized in that the offset information is constituted by non-coincidence information and in that there is a PLC circuit for controlling the offset circuit from the offset information, PLC circuit including: - a non-coincidence counter for counting the number of non-coincidences provided by said information non-coincidence and to provide an offset command to said offset circuit. Transmission system according to claim 1 or 2, characterized in that the offset information is constituted by coincidence information and in that there is provided a PLC circuit for controlling the offset circuit from the offset information, PLC circuit including: - a coincidence counter for counting the number of coincidences provided by said coincidence information and for monitoring the coincidence of said data. Transmission system according to one of claims 1 to 3, characterized in that the automatic circuit includes means for detecting silence data to annihilate the coincidence counter. Receiver suitable for a system according to one of claims 1 to 4, characterized in that it comprises: - receiver circuits to receive data from at least two channels, a circuit for resetting the data of said channels to coincide, formed: · An offset detector circuit between the channel data to provide offset information, An offset circuit for shifting according to said offset information the data of at least one of said channels, - a switching circuit for connecting a user circuit on one of said channels,
characterized in that the offset circuit is formed: · A first series-parallel circuit for supplying words of N binary elements from the data received, A permutation circuit for supplying permuted words by permuting the binary elements of the words with N binary elements as a function of said offset information, · A plurality of second series-parallel circuits for parallelizing on M outputs each of the N outputs of the permutation circuit, by taking from buffers the data according to the offset information.

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